Commit | Line | Data |
---|---|---|
0ebc4cda BH |
1 | /* |
2 | * This file contains the 64-bit "server" PowerPC variant | |
3 | * of the low level exception handling including exception | |
4 | * vectors, exception return, part of the slb and stab | |
5 | * handling and other fixed offset specific things. | |
6 | * | |
7 | * This file is meant to be #included from head_64.S due to | |
25985edc | 8 | * position dependent assembly. |
0ebc4cda BH |
9 | * |
10 | * Most of this originates from head_64.S and thus has the same | |
11 | * copyright history. | |
12 | * | |
13 | */ | |
14 | ||
8aa34ab8 | 15 | #include <asm/exception-64s.h> |
46f52210 | 16 | #include <asm/ptrace.h> |
8aa34ab8 | 17 | |
0ebc4cda BH |
18 | /* |
19 | * We layout physical memory as follows: | |
20 | * 0x0000 - 0x00ff : Secondary processor spin code | |
21 | * 0x0100 - 0x2fff : pSeries Interrupt prologs | |
22 | * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs | |
23 | * 0x6000 - 0x6fff : Initial (CPU0) segment table | |
24 | * 0x7000 - 0x7fff : FWNMI data area | |
25 | * 0x8000 - : Early init and support code | |
26 | */ | |
27 | ||
0ebc4cda BH |
28 | /* |
29 | * This is the start of the interrupt handlers for pSeries | |
30 | * This code runs with relocation off. | |
31 | * Code from here to __end_interrupts gets copied down to real | |
32 | * address 0x100 when we are running a relocatable kernel. | |
33 | * Therefore any relative branches in this section must only | |
34 | * branch to labels in this section. | |
35 | */ | |
36 | . = 0x100 | |
37 | .globl __start_interrupts | |
38 | __start_interrupts: | |
39 | ||
948cf67c BH |
40 | .globl system_reset_pSeries; |
41 | system_reset_pSeries: | |
42 | HMT_MEDIUM; | |
43 | DO_KVM 0x100; | |
44 | SET_SCRATCH0(r13) | |
45 | #ifdef CONFIG_PPC_P7_NAP | |
46 | BEGIN_FTR_SECTION | |
47 | /* Running native on arch 2.06 or later, check if we are | |
48 | * waking up from nap. We only handle no state loss and | |
49 | * supervisor state loss. We do -not- handle hypervisor | |
50 | * state loss at this time. | |
51 | */ | |
52 | mfspr r13,SPRN_SRR1 | |
53 | rlwinm r13,r13,47-31,30,31 | |
54 | cmpwi cr0,r13,1 | |
55 | bne 1f | |
56 | b .power7_wakeup_noloss | |
57 | 1: cmpwi cr0,r13,2 | |
58 | bne 1f | |
59 | b .power7_wakeup_loss | |
60 | /* Total loss of HV state is fatal, we could try to use the | |
61 | * PIR to locate a PACA, then use an emergency stack etc... | |
62 | * but for now, let's just stay stuck here | |
63 | */ | |
64 | 1: cmpwi cr0,r13,3 | |
65 | beq . | |
66 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE_206) | |
67 | #endif /* CONFIG_PPC_P7_NAP */ | |
68 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD) | |
0ebc4cda BH |
69 | |
70 | . = 0x200 | |
71 | _machine_check_pSeries: | |
72 | HMT_MEDIUM | |
842f2fed | 73 | DO_KVM 0x200 |
673b189a | 74 | SET_SCRATCH0(r13) |
a5d4f3ad | 75 | EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common, EXC_STD) |
0ebc4cda BH |
76 | |
77 | . = 0x300 | |
78 | .globl data_access_pSeries | |
79 | data_access_pSeries: | |
80 | HMT_MEDIUM | |
842f2fed | 81 | DO_KVM 0x300 |
673b189a | 82 | SET_SCRATCH0(r13) |
0ebc4cda | 83 | BEGIN_FTR_SECTION |
2dd60d79 | 84 | GET_PACA(r13) |
c5a8c0c9 BH |
85 | std r9,PACA_EXSLB+EX_R9(r13) |
86 | std r10,PACA_EXSLB+EX_R10(r13) | |
87 | mfspr r10,SPRN_DAR | |
88 | mfspr r9,SPRN_DSISR | |
89 | srdi r10,r10,60 | |
90 | rlwimi r10,r9,16,0x20 | |
91 | mfcr r9 | |
92 | cmpwi r10,0x2c | |
0ebc4cda | 93 | beq do_stab_bolted_pSeries |
c5a8c0c9 BH |
94 | ld r10,PACA_EXSLB+EX_R10(r13) |
95 | std r11,PACA_EXGEN+EX_R11(r13) | |
96 | ld r11,PACA_EXSLB+EX_R9(r13) | |
97 | std r12,PACA_EXGEN+EX_R12(r13) | |
673b189a | 98 | GET_SCRATCH0(r12) |
c5a8c0c9 BH |
99 | std r10,PACA_EXGEN+EX_R10(r13) |
100 | std r11,PACA_EXGEN+EX_R9(r13) | |
101 | std r12,PACA_EXGEN+EX_R13(r13) | |
a5d4f3ad | 102 | EXCEPTION_PROLOG_PSERIES_1(data_access_common, EXC_STD) |
c5a8c0c9 | 103 | FTR_SECTION_ELSE |
a5d4f3ad | 104 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common, EXC_STD) |
c5a8c0c9 | 105 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB) |
0ebc4cda BH |
106 | |
107 | . = 0x380 | |
108 | .globl data_access_slb_pSeries | |
109 | data_access_slb_pSeries: | |
110 | HMT_MEDIUM | |
842f2fed | 111 | DO_KVM 0x380 |
673b189a | 112 | SET_SCRATCH0(r13) |
2dd60d79 | 113 | GET_PACA(r13) |
0ebc4cda BH |
114 | std r3,PACA_EXSLB+EX_R3(r13) |
115 | mfspr r3,SPRN_DAR | |
116 | std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ | |
117 | mfcr r9 | |
118 | #ifdef __DISABLED__ | |
119 | /* Keep that around for when we re-implement dynamic VSIDs */ | |
120 | cmpdi r3,0 | |
121 | bge slb_miss_user_pseries | |
122 | #endif /* __DISABLED__ */ | |
123 | std r10,PACA_EXSLB+EX_R10(r13) | |
124 | std r11,PACA_EXSLB+EX_R11(r13) | |
125 | std r12,PACA_EXSLB+EX_R12(r13) | |
673b189a | 126 | GET_SCRATCH0(r10) |
0ebc4cda BH |
127 | std r10,PACA_EXSLB+EX_R13(r13) |
128 | mfspr r12,SPRN_SRR1 /* and SRR1 */ | |
129 | #ifndef CONFIG_RELOCATABLE | |
130 | b .slb_miss_realmode | |
131 | #else | |
132 | /* | |
133 | * We can't just use a direct branch to .slb_miss_realmode | |
134 | * because the distance from here to there depends on where | |
135 | * the kernel ends up being put. | |
136 | */ | |
137 | mfctr r11 | |
138 | ld r10,PACAKBASE(r13) | |
139 | LOAD_HANDLER(r10, .slb_miss_realmode) | |
140 | mtctr r10 | |
141 | bctr | |
142 | #endif | |
143 | ||
b3e6b5df | 144 | STD_EXCEPTION_PSERIES(0x400, 0x400, instruction_access) |
0ebc4cda BH |
145 | |
146 | . = 0x480 | |
147 | .globl instruction_access_slb_pSeries | |
148 | instruction_access_slb_pSeries: | |
149 | HMT_MEDIUM | |
842f2fed | 150 | DO_KVM 0x480 |
673b189a | 151 | SET_SCRATCH0(r13) |
2dd60d79 | 152 | GET_PACA(r13) |
0ebc4cda BH |
153 | std r3,PACA_EXSLB+EX_R3(r13) |
154 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
155 | std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ | |
156 | mfcr r9 | |
157 | #ifdef __DISABLED__ | |
158 | /* Keep that around for when we re-implement dynamic VSIDs */ | |
159 | cmpdi r3,0 | |
160 | bge slb_miss_user_pseries | |
161 | #endif /* __DISABLED__ */ | |
162 | std r10,PACA_EXSLB+EX_R10(r13) | |
163 | std r11,PACA_EXSLB+EX_R11(r13) | |
164 | std r12,PACA_EXSLB+EX_R12(r13) | |
673b189a | 165 | GET_SCRATCH0(r10) |
0ebc4cda BH |
166 | std r10,PACA_EXSLB+EX_R13(r13) |
167 | mfspr r12,SPRN_SRR1 /* and SRR1 */ | |
168 | #ifndef CONFIG_RELOCATABLE | |
169 | b .slb_miss_realmode | |
170 | #else | |
171 | mfctr r11 | |
172 | ld r10,PACAKBASE(r13) | |
173 | LOAD_HANDLER(r10, .slb_miss_realmode) | |
174 | mtctr r10 | |
175 | bctr | |
176 | #endif | |
177 | ||
b3e6b5df BH |
178 | /* We open code these as we can't have a ". = x" (even with |
179 | * x = "." within a feature section | |
180 | */ | |
a5d4f3ad | 181 | . = 0x500; |
b3e6b5df BH |
182 | .globl hardware_interrupt_pSeries; |
183 | .globl hardware_interrupt_hv; | |
a5d4f3ad | 184 | hardware_interrupt_pSeries: |
b3e6b5df | 185 | hardware_interrupt_hv: |
a5d4f3ad | 186 | BEGIN_FTR_SECTION |
b3e6b5df | 187 | _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt, EXC_STD) |
a5d4f3ad | 188 | FTR_SECTION_ELSE |
b3e6b5df | 189 | _MASKABLE_EXCEPTION_PSERIES(0x502, hardware_interrupt, EXC_HV) |
a5d4f3ad BH |
190 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_HVMODE_206) |
191 | ||
b3e6b5df BH |
192 | STD_EXCEPTION_PSERIES(0x600, 0x600, alignment) |
193 | STD_EXCEPTION_PSERIES(0x700, 0x700, program_check) | |
194 | STD_EXCEPTION_PSERIES(0x800, 0x800, fp_unavailable) | |
a5d4f3ad | 195 | |
b3e6b5df BH |
196 | MASKABLE_EXCEPTION_PSERIES(0x900, 0x900, decrementer) |
197 | MASKABLE_EXCEPTION_HV(0x980, 0x980, decrementer) | |
a5d4f3ad | 198 | |
b3e6b5df BH |
199 | STD_EXCEPTION_PSERIES(0xa00, 0xa00, trap_0a) |
200 | STD_EXCEPTION_PSERIES(0xb00, 0xb00, trap_0b) | |
0ebc4cda BH |
201 | |
202 | . = 0xc00 | |
203 | .globl system_call_pSeries | |
204 | system_call_pSeries: | |
205 | HMT_MEDIUM | |
842f2fed | 206 | DO_KVM 0xc00 |
0ebc4cda BH |
207 | BEGIN_FTR_SECTION |
208 | cmpdi r0,0x1ebe | |
209 | beq- 1f | |
210 | END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) | |
211 | mr r9,r13 | |
2dd60d79 | 212 | GET_PACA(r13) |
0ebc4cda BH |
213 | mfspr r11,SPRN_SRR0 |
214 | ld r12,PACAKBASE(r13) | |
215 | ld r10,PACAKMSR(r13) | |
216 | LOAD_HANDLER(r12, system_call_entry) | |
217 | mtspr SPRN_SRR0,r12 | |
218 | mfspr r12,SPRN_SRR1 | |
219 | mtspr SPRN_SRR1,r10 | |
220 | rfid | |
221 | b . /* prevent speculative execution */ | |
222 | ||
223 | /* Fast LE/BE switch system call */ | |
224 | 1: mfspr r12,SPRN_SRR1 | |
225 | xori r12,r12,MSR_LE | |
226 | mtspr SPRN_SRR1,r12 | |
227 | rfid /* return to userspace */ | |
228 | b . | |
229 | ||
b3e6b5df BH |
230 | STD_EXCEPTION_PSERIES(0xd00, 0xd00, single_step) |
231 | ||
232 | /* At 0xe??? we have a bunch of hypervisor exceptions, we branch | |
233 | * out of line to handle them | |
234 | */ | |
235 | . = 0xe00 | |
236 | b h_data_storage_hv | |
237 | . = 0xe20 | |
238 | b h_instr_storage_hv | |
239 | . = 0xe40 | |
240 | b emulation_assist_hv | |
241 | . = 0xe50 | |
242 | b hmi_exception_hv | |
243 | . = 0xe60 | |
244 | b hmi_exception_hv | |
0ebc4cda BH |
245 | |
246 | /* We need to deal with the Altivec unavailable exception | |
247 | * here which is at 0xf20, thus in the middle of the | |
248 | * prolog code of the PerformanceMonitor one. A little | |
249 | * trickery is thus necessary | |
250 | */ | |
c86e2ead | 251 | performance_monitor_pSeries_1: |
0ebc4cda BH |
252 | . = 0xf00 |
253 | b performance_monitor_pSeries | |
254 | ||
c86e2ead | 255 | altivec_unavailable_pSeries_1: |
0ebc4cda BH |
256 | . = 0xf20 |
257 | b altivec_unavailable_pSeries | |
258 | ||
c86e2ead | 259 | vsx_unavailable_pSeries_1: |
0ebc4cda BH |
260 | . = 0xf40 |
261 | b vsx_unavailable_pSeries | |
262 | ||
263 | #ifdef CONFIG_CBE_RAS | |
b3e6b5df | 264 | STD_EXCEPTION_HV(0x1200, 0x1202, cbe_system_error) |
0ebc4cda | 265 | #endif /* CONFIG_CBE_RAS */ |
b3e6b5df | 266 | STD_EXCEPTION_PSERIES(0x1300, 0x1300, instruction_breakpoint) |
0ebc4cda | 267 | #ifdef CONFIG_CBE_RAS |
b3e6b5df | 268 | STD_EXCEPTION_HV(0x1600, 0x1602, cbe_maintenance) |
0ebc4cda | 269 | #endif /* CONFIG_CBE_RAS */ |
b3e6b5df | 270 | STD_EXCEPTION_PSERIES(0x1700, 0x1700, altivec_assist) |
0ebc4cda | 271 | #ifdef CONFIG_CBE_RAS |
b3e6b5df | 272 | STD_EXCEPTION_HV(0x1800, 0x1802, cbe_thermal) |
0ebc4cda BH |
273 | #endif /* CONFIG_CBE_RAS */ |
274 | ||
275 | . = 0x3000 | |
276 | ||
b3e6b5df BH |
277 | /*** Out of line interrupts support ***/ |
278 | ||
279 | /* moved from 0xe00 */ | |
280 | STD_EXCEPTION_HV(., 0xe00, h_data_storage) | |
281 | STD_EXCEPTION_HV(., 0xe20, h_instr_storage) | |
282 | STD_EXCEPTION_HV(., 0xe40, emulation_assist) | |
283 | STD_EXCEPTION_HV(., 0xe60, hmi_exception) /* need to flush cache ? */ | |
0ebc4cda BH |
284 | |
285 | /* moved from 0xf00 */ | |
b3e6b5df BH |
286 | STD_EXCEPTION_PSERIES(., 0xf00, performance_monitor) |
287 | STD_EXCEPTION_PSERIES(., 0xf20, altivec_unavailable) | |
288 | STD_EXCEPTION_PSERIES(., 0xf40, vsx_unavailable) | |
0ebc4cda BH |
289 | |
290 | /* | |
291 | * An interrupt came in while soft-disabled; clear EE in SRR1, | |
292 | * clear paca->hard_enabled and return. | |
293 | */ | |
294 | masked_interrupt: | |
295 | stb r10,PACAHARDIRQEN(r13) | |
296 | mtcrf 0x80,r9 | |
297 | ld r9,PACA_EXGEN+EX_R9(r13) | |
298 | mfspr r10,SPRN_SRR1 | |
299 | rldicl r10,r10,48,1 /* clear MSR_EE */ | |
300 | rotldi r10,r10,16 | |
301 | mtspr SPRN_SRR1,r10 | |
302 | ld r10,PACA_EXGEN+EX_R10(r13) | |
673b189a | 303 | GET_SCRATCH0(r13) |
0ebc4cda BH |
304 | rfid |
305 | b . | |
306 | ||
a5d4f3ad BH |
307 | masked_Hinterrupt: |
308 | stb r10,PACAHARDIRQEN(r13) | |
309 | mtcrf 0x80,r9 | |
310 | ld r9,PACA_EXGEN+EX_R9(r13) | |
311 | mfspr r10,SPRN_HSRR1 | |
312 | rldicl r10,r10,48,1 /* clear MSR_EE */ | |
313 | rotldi r10,r10,16 | |
314 | mtspr SPRN_HSRR1,r10 | |
315 | ld r10,PACA_EXGEN+EX_R10(r13) | |
673b189a | 316 | GET_SCRATCH0(r13) |
a5d4f3ad BH |
317 | hrfid |
318 | b . | |
319 | ||
0ebc4cda BH |
320 | .align 7 |
321 | do_stab_bolted_pSeries: | |
c5a8c0c9 BH |
322 | std r11,PACA_EXSLB+EX_R11(r13) |
323 | std r12,PACA_EXSLB+EX_R12(r13) | |
673b189a | 324 | GET_SCRATCH0(r10) |
c5a8c0c9 | 325 | std r10,PACA_EXSLB+EX_R13(r13) |
a5d4f3ad | 326 | EXCEPTION_PROLOG_PSERIES_1(.do_stab_bolted, EXC_STD) |
0ebc4cda BH |
327 | |
328 | #ifdef CONFIG_PPC_PSERIES | |
329 | /* | |
330 | * Vectors for the FWNMI option. Share common code. | |
331 | */ | |
332 | .globl system_reset_fwnmi | |
333 | .align 7 | |
334 | system_reset_fwnmi: | |
335 | HMT_MEDIUM | |
673b189a | 336 | SET_SCRATCH0(r13) /* save r13 */ |
a5d4f3ad | 337 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD) |
0ebc4cda BH |
338 | |
339 | .globl machine_check_fwnmi | |
340 | .align 7 | |
341 | machine_check_fwnmi: | |
342 | HMT_MEDIUM | |
673b189a | 343 | SET_SCRATCH0(r13) /* save r13 */ |
a5d4f3ad | 344 | EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common, EXC_STD) |
0ebc4cda BH |
345 | |
346 | #endif /* CONFIG_PPC_PSERIES */ | |
347 | ||
348 | #ifdef __DISABLED__ | |
349 | /* | |
350 | * This is used for when the SLB miss handler has to go virtual, | |
351 | * which doesn't happen for now anymore but will once we re-implement | |
352 | * dynamic VSIDs for shared page tables | |
353 | */ | |
354 | slb_miss_user_pseries: | |
355 | std r10,PACA_EXGEN+EX_R10(r13) | |
356 | std r11,PACA_EXGEN+EX_R11(r13) | |
357 | std r12,PACA_EXGEN+EX_R12(r13) | |
673b189a | 358 | GET_SCRATCH0(r10) |
0ebc4cda BH |
359 | ld r11,PACA_EXSLB+EX_R9(r13) |
360 | ld r12,PACA_EXSLB+EX_R3(r13) | |
361 | std r10,PACA_EXGEN+EX_R13(r13) | |
362 | std r11,PACA_EXGEN+EX_R9(r13) | |
363 | std r12,PACA_EXGEN+EX_R3(r13) | |
364 | clrrdi r12,r13,32 | |
365 | mfmsr r10 | |
366 | mfspr r11,SRR0 /* save SRR0 */ | |
367 | ori r12,r12,slb_miss_user_common@l /* virt addr of handler */ | |
368 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI | |
369 | mtspr SRR0,r12 | |
370 | mfspr r12,SRR1 /* and SRR1 */ | |
371 | mtspr SRR1,r10 | |
372 | rfid | |
373 | b . /* prevent spec. execution */ | |
374 | #endif /* __DISABLED__ */ | |
375 | ||
a58ddea5 AG |
376 | /* KVM's trampoline code needs to be close to the interrupt handlers */ |
377 | ||
378 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER | |
379 | #include "../kvm/book3s_rmhandlers.S" | |
380 | #endif | |
381 | ||
0ebc4cda BH |
382 | .align 7 |
383 | .globl __end_interrupts | |
384 | __end_interrupts: | |
385 | ||
386 | /* | |
387 | * Code from here down to __end_handlers is invoked from the | |
388 | * exception prologs above. Because the prologs assemble the | |
389 | * addresses of these handlers using the LOAD_HANDLER macro, | |
390 | * which uses an addi instruction, these handlers must be in | |
391 | * the first 32k of the kernel image. | |
392 | */ | |
393 | ||
394 | /*** Common interrupt handlers ***/ | |
395 | ||
396 | STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception) | |
397 | ||
398 | /* | |
399 | * Machine check is different because we use a different | |
400 | * save area: PACA_EXMC instead of PACA_EXGEN. | |
401 | */ | |
402 | .align 7 | |
403 | .globl machine_check_common | |
404 | machine_check_common: | |
405 | EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) | |
406 | FINISH_NAP | |
407 | DISABLE_INTS | |
408 | bl .save_nvgprs | |
409 | addi r3,r1,STACK_FRAME_OVERHEAD | |
410 | bl .machine_check_exception | |
411 | b .ret_from_except | |
412 | ||
413 | STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt) | |
414 | STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception) | |
415 | STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception) | |
416 | STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception) | |
417 | STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception) | |
b3e6b5df BH |
418 | STD_EXCEPTION_COMMON(0xe40, emulation_assist, .program_check_exception) |
419 | STD_EXCEPTION_COMMON(0xe60, hmi_exception, .unknown_exception) | |
0ebc4cda BH |
420 | STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception) |
421 | STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception) | |
422 | #ifdef CONFIG_ALTIVEC | |
423 | STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception) | |
424 | #else | |
425 | STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception) | |
426 | #endif | |
427 | #ifdef CONFIG_CBE_RAS | |
428 | STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception) | |
429 | STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception) | |
430 | STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception) | |
431 | #endif /* CONFIG_CBE_RAS */ | |
432 | ||
433 | .align 7 | |
434 | system_call_entry: | |
435 | b system_call_common | |
436 | ||
437 | /* | |
438 | * Here we have detected that the kernel stack pointer is bad. | |
439 | * R9 contains the saved CR, r13 points to the paca, | |
440 | * r10 contains the (bad) kernel stack pointer, | |
441 | * r11 and r12 contain the saved SRR0 and SRR1. | |
442 | * We switch to using an emergency stack, save the registers there, | |
443 | * and call kernel_bad_stack(), which panics. | |
444 | */ | |
445 | bad_stack: | |
446 | ld r1,PACAEMERGSP(r13) | |
447 | subi r1,r1,64+INT_FRAME_SIZE | |
448 | std r9,_CCR(r1) | |
449 | std r10,GPR1(r1) | |
450 | std r11,_NIP(r1) | |
451 | std r12,_MSR(r1) | |
452 | mfspr r11,SPRN_DAR | |
453 | mfspr r12,SPRN_DSISR | |
454 | std r11,_DAR(r1) | |
455 | std r12,_DSISR(r1) | |
456 | mflr r10 | |
457 | mfctr r11 | |
458 | mfxer r12 | |
459 | std r10,_LINK(r1) | |
460 | std r11,_CTR(r1) | |
461 | std r12,_XER(r1) | |
462 | SAVE_GPR(0,r1) | |
463 | SAVE_GPR(2,r1) | |
464 | SAVE_4GPRS(3,r1) | |
465 | SAVE_2GPRS(7,r1) | |
466 | SAVE_10GPRS(12,r1) | |
467 | SAVE_10GPRS(22,r1) | |
468 | lhz r12,PACA_TRAP_SAVE(r13) | |
469 | std r12,_TRAP(r1) | |
470 | addi r11,r1,INT_FRAME_SIZE | |
471 | std r11,0(r1) | |
472 | li r12,0 | |
473 | std r12,0(r11) | |
474 | ld r2,PACATOC(r13) | |
475 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
476 | bl .kernel_bad_stack | |
477 | b 1b | |
478 | ||
479 | /* | |
480 | * Here r13 points to the paca, r9 contains the saved CR, | |
481 | * SRR0 and SRR1 are saved in r11 and r12, | |
482 | * r9 - r13 are saved in paca->exgen. | |
483 | */ | |
484 | .align 7 | |
485 | .globl data_access_common | |
486 | data_access_common: | |
487 | mfspr r10,SPRN_DAR | |
488 | std r10,PACA_EXGEN+EX_DAR(r13) | |
489 | mfspr r10,SPRN_DSISR | |
490 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
491 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) | |
492 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
493 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
494 | li r5,0x300 | |
495 | b .do_hash_page /* Try to handle as hpte fault */ | |
496 | ||
b3e6b5df BH |
497 | .align 7 |
498 | .globl h_data_storage_common | |
499 | h_data_storage_common: | |
500 | mfspr r10,SPRN_HDAR | |
501 | std r10,PACA_EXGEN+EX_DAR(r13) | |
502 | mfspr r10,SPRN_HDSISR | |
503 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
504 | EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) | |
505 | bl .save_nvgprs | |
506 | addi r3,r1,STACK_FRAME_OVERHEAD | |
507 | bl .unknown_exception | |
508 | b .ret_from_except | |
509 | ||
0ebc4cda BH |
510 | .align 7 |
511 | .globl instruction_access_common | |
512 | instruction_access_common: | |
513 | EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) | |
514 | ld r3,_NIP(r1) | |
515 | andis. r4,r12,0x5820 | |
516 | li r5,0x400 | |
517 | b .do_hash_page /* Try to handle as hpte fault */ | |
518 | ||
b3e6b5df BH |
519 | STD_EXCEPTION_COMMON(0xe20, h_instr_storage, .unknown_exception) |
520 | ||
0ebc4cda BH |
521 | /* |
522 | * Here is the common SLB miss user that is used when going to virtual | |
523 | * mode for SLB misses, that is currently not used | |
524 | */ | |
525 | #ifdef __DISABLED__ | |
526 | .align 7 | |
527 | .globl slb_miss_user_common | |
528 | slb_miss_user_common: | |
529 | mflr r10 | |
530 | std r3,PACA_EXGEN+EX_DAR(r13) | |
531 | stw r9,PACA_EXGEN+EX_CCR(r13) | |
532 | std r10,PACA_EXGEN+EX_LR(r13) | |
533 | std r11,PACA_EXGEN+EX_SRR0(r13) | |
534 | bl .slb_allocate_user | |
535 | ||
536 | ld r10,PACA_EXGEN+EX_LR(r13) | |
537 | ld r3,PACA_EXGEN+EX_R3(r13) | |
538 | lwz r9,PACA_EXGEN+EX_CCR(r13) | |
539 | ld r11,PACA_EXGEN+EX_SRR0(r13) | |
540 | mtlr r10 | |
541 | beq- slb_miss_fault | |
542 | ||
543 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | |
544 | beq- unrecov_user_slb | |
545 | mfmsr r10 | |
546 | ||
547 | .machine push | |
548 | .machine "power4" | |
549 | mtcrf 0x80,r9 | |
550 | .machine pop | |
551 | ||
552 | clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */ | |
553 | mtmsrd r10,1 | |
554 | ||
555 | mtspr SRR0,r11 | |
556 | mtspr SRR1,r12 | |
557 | ||
558 | ld r9,PACA_EXGEN+EX_R9(r13) | |
559 | ld r10,PACA_EXGEN+EX_R10(r13) | |
560 | ld r11,PACA_EXGEN+EX_R11(r13) | |
561 | ld r12,PACA_EXGEN+EX_R12(r13) | |
562 | ld r13,PACA_EXGEN+EX_R13(r13) | |
563 | rfid | |
564 | b . | |
565 | ||
566 | slb_miss_fault: | |
567 | EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN) | |
568 | ld r4,PACA_EXGEN+EX_DAR(r13) | |
569 | li r5,0 | |
570 | std r4,_DAR(r1) | |
571 | std r5,_DSISR(r1) | |
572 | b handle_page_fault | |
573 | ||
574 | unrecov_user_slb: | |
575 | EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN) | |
576 | DISABLE_INTS | |
577 | bl .save_nvgprs | |
578 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
579 | bl .unrecoverable_exception | |
580 | b 1b | |
581 | ||
582 | #endif /* __DISABLED__ */ | |
583 | ||
584 | ||
585 | /* | |
586 | * r13 points to the PACA, r9 contains the saved CR, | |
587 | * r12 contain the saved SRR1, SRR0 is still ready for return | |
588 | * r3 has the faulting address | |
589 | * r9 - r13 are saved in paca->exslb. | |
590 | * r3 is saved in paca->slb_r3 | |
591 | * We assume we aren't going to take any exceptions during this procedure. | |
592 | */ | |
593 | _GLOBAL(slb_miss_realmode) | |
594 | mflr r10 | |
595 | #ifdef CONFIG_RELOCATABLE | |
596 | mtctr r11 | |
597 | #endif | |
598 | ||
599 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
600 | std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ | |
601 | ||
602 | bl .slb_allocate_realmode | |
603 | ||
604 | /* All done -- return from exception. */ | |
605 | ||
606 | ld r10,PACA_EXSLB+EX_LR(r13) | |
607 | ld r3,PACA_EXSLB+EX_R3(r13) | |
608 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
609 | #ifdef CONFIG_PPC_ISERIES | |
610 | BEGIN_FW_FTR_SECTION | |
611 | ld r11,PACALPPACAPTR(r13) | |
612 | ld r11,LPPACASRR0(r11) /* get SRR0 value */ | |
613 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) | |
614 | #endif /* CONFIG_PPC_ISERIES */ | |
615 | ||
616 | mtlr r10 | |
617 | ||
618 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | |
619 | beq- 2f | |
620 | ||
621 | .machine push | |
622 | .machine "power4" | |
623 | mtcrf 0x80,r9 | |
624 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ | |
625 | .machine pop | |
626 | ||
627 | #ifdef CONFIG_PPC_ISERIES | |
628 | BEGIN_FW_FTR_SECTION | |
629 | mtspr SPRN_SRR0,r11 | |
630 | mtspr SPRN_SRR1,r12 | |
631 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) | |
632 | #endif /* CONFIG_PPC_ISERIES */ | |
633 | ld r9,PACA_EXSLB+EX_R9(r13) | |
634 | ld r10,PACA_EXSLB+EX_R10(r13) | |
635 | ld r11,PACA_EXSLB+EX_R11(r13) | |
636 | ld r12,PACA_EXSLB+EX_R12(r13) | |
637 | ld r13,PACA_EXSLB+EX_R13(r13) | |
638 | rfid | |
639 | b . /* prevent speculative execution */ | |
640 | ||
641 | 2: | |
642 | #ifdef CONFIG_PPC_ISERIES | |
643 | BEGIN_FW_FTR_SECTION | |
644 | b unrecov_slb | |
645 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) | |
646 | #endif /* CONFIG_PPC_ISERIES */ | |
647 | mfspr r11,SPRN_SRR0 | |
648 | ld r10,PACAKBASE(r13) | |
649 | LOAD_HANDLER(r10,unrecov_slb) | |
650 | mtspr SPRN_SRR0,r10 | |
651 | ld r10,PACAKMSR(r13) | |
652 | mtspr SPRN_SRR1,r10 | |
653 | rfid | |
654 | b . | |
655 | ||
656 | unrecov_slb: | |
657 | EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) | |
658 | DISABLE_INTS | |
659 | bl .save_nvgprs | |
660 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
661 | bl .unrecoverable_exception | |
662 | b 1b | |
663 | ||
664 | .align 7 | |
665 | .globl hardware_interrupt_common | |
666 | .globl hardware_interrupt_entry | |
667 | hardware_interrupt_common: | |
668 | EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN) | |
669 | FINISH_NAP | |
670 | hardware_interrupt_entry: | |
671 | DISABLE_INTS | |
672 | BEGIN_FTR_SECTION | |
673 | bl .ppc64_runlatch_on | |
674 | END_FTR_SECTION_IFSET(CPU_FTR_CTRL) | |
675 | addi r3,r1,STACK_FRAME_OVERHEAD | |
676 | bl .do_IRQ | |
677 | b .ret_from_except_lite | |
678 | ||
679 | #ifdef CONFIG_PPC_970_NAP | |
680 | power4_fixup_nap: | |
681 | andc r9,r9,r10 | |
682 | std r9,TI_LOCAL_FLAGS(r11) | |
683 | ld r10,_LINK(r1) /* make idle task do the */ | |
684 | std r10,_NIP(r1) /* equivalent of a blr */ | |
685 | blr | |
686 | #endif | |
687 | ||
688 | .align 7 | |
689 | .globl alignment_common | |
690 | alignment_common: | |
691 | mfspr r10,SPRN_DAR | |
692 | std r10,PACA_EXGEN+EX_DAR(r13) | |
693 | mfspr r10,SPRN_DSISR | |
694 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
695 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) | |
696 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
697 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
698 | std r3,_DAR(r1) | |
699 | std r4,_DSISR(r1) | |
700 | bl .save_nvgprs | |
701 | addi r3,r1,STACK_FRAME_OVERHEAD | |
702 | ENABLE_INTS | |
703 | bl .alignment_exception | |
704 | b .ret_from_except | |
705 | ||
706 | .align 7 | |
707 | .globl program_check_common | |
708 | program_check_common: | |
709 | EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) | |
710 | bl .save_nvgprs | |
711 | addi r3,r1,STACK_FRAME_OVERHEAD | |
712 | ENABLE_INTS | |
713 | bl .program_check_exception | |
714 | b .ret_from_except | |
715 | ||
716 | .align 7 | |
717 | .globl fp_unavailable_common | |
718 | fp_unavailable_common: | |
719 | EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) | |
720 | bne 1f /* if from user, just load it up */ | |
721 | bl .save_nvgprs | |
722 | addi r3,r1,STACK_FRAME_OVERHEAD | |
723 | ENABLE_INTS | |
724 | bl .kernel_fp_unavailable_exception | |
725 | BUG_OPCODE | |
726 | 1: bl .load_up_fpu | |
727 | b fast_exception_return | |
728 | ||
729 | .align 7 | |
730 | .globl altivec_unavailable_common | |
731 | altivec_unavailable_common: | |
732 | EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) | |
733 | #ifdef CONFIG_ALTIVEC | |
734 | BEGIN_FTR_SECTION | |
735 | beq 1f | |
736 | bl .load_up_altivec | |
737 | b fast_exception_return | |
738 | 1: | |
739 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
740 | #endif | |
741 | bl .save_nvgprs | |
742 | addi r3,r1,STACK_FRAME_OVERHEAD | |
743 | ENABLE_INTS | |
744 | bl .altivec_unavailable_exception | |
745 | b .ret_from_except | |
746 | ||
747 | .align 7 | |
748 | .globl vsx_unavailable_common | |
749 | vsx_unavailable_common: | |
750 | EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) | |
751 | #ifdef CONFIG_VSX | |
752 | BEGIN_FTR_SECTION | |
753 | bne .load_up_vsx | |
754 | 1: | |
755 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
756 | #endif | |
757 | bl .save_nvgprs | |
758 | addi r3,r1,STACK_FRAME_OVERHEAD | |
759 | ENABLE_INTS | |
760 | bl .vsx_unavailable_exception | |
761 | b .ret_from_except | |
762 | ||
763 | .align 7 | |
764 | .globl __end_handlers | |
765 | __end_handlers: | |
766 | ||
767 | /* | |
768 | * Return from an exception with minimal checks. | |
769 | * The caller is assumed to have done EXCEPTION_PROLOG_COMMON. | |
770 | * If interrupts have been enabled, or anything has been | |
771 | * done that might have changed the scheduling status of | |
772 | * any task or sent any task a signal, you should use | |
773 | * ret_from_except or ret_from_except_lite instead of this. | |
774 | */ | |
775 | fast_exc_return_irq: /* restores irq state too */ | |
776 | ld r3,SOFTE(r1) | |
777 | TRACE_AND_RESTORE_IRQ(r3); | |
778 | ld r12,_MSR(r1) | |
779 | rldicl r4,r12,49,63 /* get MSR_EE to LSB */ | |
780 | stb r4,PACAHARDIRQEN(r13) /* restore paca->hard_enabled */ | |
781 | b 1f | |
782 | ||
783 | .globl fast_exception_return | |
784 | fast_exception_return: | |
785 | ld r12,_MSR(r1) | |
786 | 1: ld r11,_NIP(r1) | |
787 | andi. r3,r12,MSR_RI /* check if RI is set */ | |
788 | beq- unrecov_fer | |
789 | ||
790 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | |
791 | andi. r3,r12,MSR_PR | |
792 | beq 2f | |
793 | ACCOUNT_CPU_USER_EXIT(r3, r4) | |
794 | 2: | |
795 | #endif | |
796 | ||
797 | ld r3,_CCR(r1) | |
798 | ld r4,_LINK(r1) | |
799 | ld r5,_CTR(r1) | |
800 | ld r6,_XER(r1) | |
801 | mtcr r3 | |
802 | mtlr r4 | |
803 | mtctr r5 | |
804 | mtxer r6 | |
805 | REST_GPR(0, r1) | |
806 | REST_8GPRS(2, r1) | |
807 | ||
808 | mfmsr r10 | |
809 | rldicl r10,r10,48,1 /* clear EE */ | |
810 | rldicr r10,r10,16,61 /* clear RI (LE is 0 already) */ | |
811 | mtmsrd r10,1 | |
812 | ||
813 | mtspr SPRN_SRR1,r12 | |
814 | mtspr SPRN_SRR0,r11 | |
815 | REST_4GPRS(10, r1) | |
816 | ld r1,GPR1(r1) | |
817 | rfid | |
818 | b . /* prevent speculative execution */ | |
819 | ||
820 | unrecov_fer: | |
821 | bl .save_nvgprs | |
822 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
823 | bl .unrecoverable_exception | |
824 | b 1b | |
825 | ||
826 | ||
827 | /* | |
828 | * Hash table stuff | |
829 | */ | |
830 | .align 7 | |
831 | _STATIC(do_hash_page) | |
832 | std r3,_DAR(r1) | |
833 | std r4,_DSISR(r1) | |
834 | ||
9c7cc234 | 835 | andis. r0,r4,0xa410 /* weird error? */ |
0ebc4cda | 836 | bne- handle_page_fault /* if not, try to insert a HPTE */ |
9c7cc234 P |
837 | andis. r0,r4,DSISR_DABRMATCH@h |
838 | bne- handle_dabr_fault | |
839 | ||
0ebc4cda BH |
840 | BEGIN_FTR_SECTION |
841 | andis. r0,r4,0x0020 /* Is it a segment table fault? */ | |
842 | bne- do_ste_alloc /* If so handle it */ | |
843 | END_FTR_SECTION_IFCLR(CPU_FTR_SLB) | |
844 | ||
9c1e1052 PM |
845 | clrrdi r11,r1,THREAD_SHIFT |
846 | lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ | |
847 | andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ | |
848 | bne 77f /* then don't call hash_page now */ | |
849 | ||
0ebc4cda BH |
850 | /* |
851 | * On iSeries, we soft-disable interrupts here, then | |
852 | * hard-enable interrupts so that the hash_page code can spin on | |
853 | * the hash_table_lock without problems on a shared processor. | |
854 | */ | |
855 | DISABLE_INTS | |
856 | ||
857 | /* | |
858 | * Currently, trace_hardirqs_off() will be called by DISABLE_INTS | |
859 | * and will clobber volatile registers when irq tracing is enabled | |
860 | * so we need to reload them. It may be possible to be smarter here | |
861 | * and move the irq tracing elsewhere but let's keep it simple for | |
862 | * now | |
863 | */ | |
864 | #ifdef CONFIG_TRACE_IRQFLAGS | |
865 | ld r3,_DAR(r1) | |
866 | ld r4,_DSISR(r1) | |
867 | ld r5,_TRAP(r1) | |
868 | ld r12,_MSR(r1) | |
869 | clrrdi r5,r5,4 | |
870 | #endif /* CONFIG_TRACE_IRQFLAGS */ | |
871 | /* | |
872 | * We need to set the _PAGE_USER bit if MSR_PR is set or if we are | |
873 | * accessing a userspace segment (even from the kernel). We assume | |
874 | * kernel addresses always have the high bit set. | |
875 | */ | |
876 | rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */ | |
877 | rotldi r0,r3,15 /* Move high bit into MSR_PR posn */ | |
878 | orc r0,r12,r0 /* MSR_PR | ~high_bit */ | |
879 | rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */ | |
880 | ori r4,r4,1 /* add _PAGE_PRESENT */ | |
881 | rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */ | |
882 | ||
883 | /* | |
884 | * r3 contains the faulting address | |
885 | * r4 contains the required access permissions | |
886 | * r5 contains the trap number | |
887 | * | |
888 | * at return r3 = 0 for success | |
889 | */ | |
890 | bl .hash_page /* build HPTE if possible */ | |
891 | cmpdi r3,0 /* see if hash_page succeeded */ | |
892 | ||
893 | BEGIN_FW_FTR_SECTION | |
894 | /* | |
895 | * If we had interrupts soft-enabled at the point where the | |
896 | * DSI/ISI occurred, and an interrupt came in during hash_page, | |
897 | * handle it now. | |
898 | * We jump to ret_from_except_lite rather than fast_exception_return | |
899 | * because ret_from_except_lite will check for and handle pending | |
900 | * interrupts if necessary. | |
901 | */ | |
902 | beq 13f | |
903 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) | |
904 | ||
905 | BEGIN_FW_FTR_SECTION | |
906 | /* | |
907 | * Here we have interrupts hard-disabled, so it is sufficient | |
908 | * to restore paca->{soft,hard}_enable and get out. | |
909 | */ | |
910 | beq fast_exc_return_irq /* Return from exception on success */ | |
911 | END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) | |
912 | ||
913 | /* For a hash failure, we don't bother re-enabling interrupts */ | |
914 | ble- 12f | |
915 | ||
916 | /* | |
917 | * hash_page couldn't handle it, set soft interrupt enable back | |
df9ee292 | 918 | * to what it was before the trap. Note that .arch_local_irq_restore |
0ebc4cda BH |
919 | * handles any interrupts pending at this point. |
920 | */ | |
921 | ld r3,SOFTE(r1) | |
922 | TRACE_AND_RESTORE_IRQ_PARTIAL(r3, 11f) | |
df9ee292 | 923 | bl .arch_local_irq_restore |
0ebc4cda BH |
924 | b 11f |
925 | ||
9c7cc234 P |
926 | /* We have a data breakpoint exception - handle it */ |
927 | handle_dabr_fault: | |
5aae8a53 | 928 | bl .save_nvgprs |
9c7cc234 P |
929 | ld r4,_DAR(r1) |
930 | ld r5,_DSISR(r1) | |
931 | addi r3,r1,STACK_FRAME_OVERHEAD | |
932 | bl .do_dabr | |
933 | b .ret_from_except_lite | |
934 | ||
0ebc4cda BH |
935 | /* Here we have a page fault that hash_page can't handle. */ |
936 | handle_page_fault: | |
937 | ENABLE_INTS | |
938 | 11: ld r4,_DAR(r1) | |
939 | ld r5,_DSISR(r1) | |
940 | addi r3,r1,STACK_FRAME_OVERHEAD | |
941 | bl .do_page_fault | |
942 | cmpdi r3,0 | |
943 | beq+ 13f | |
944 | bl .save_nvgprs | |
945 | mr r5,r3 | |
946 | addi r3,r1,STACK_FRAME_OVERHEAD | |
947 | lwz r4,_DAR(r1) | |
948 | bl .bad_page_fault | |
949 | b .ret_from_except | |
950 | ||
951 | 13: b .ret_from_except_lite | |
952 | ||
953 | /* We have a page fault that hash_page could handle but HV refused | |
954 | * the PTE insertion | |
955 | */ | |
956 | 12: bl .save_nvgprs | |
957 | mr r5,r3 | |
958 | addi r3,r1,STACK_FRAME_OVERHEAD | |
959 | ld r4,_DAR(r1) | |
960 | bl .low_hash_fault | |
961 | b .ret_from_except | |
962 | ||
9c1e1052 PM |
963 | /* |
964 | * We come here as a result of a DSI at a point where we don't want | |
965 | * to call hash_page, such as when we are accessing memory (possibly | |
966 | * user memory) inside a PMU interrupt that occurred while interrupts | |
967 | * were soft-disabled. We want to invoke the exception handler for | |
968 | * the access, or panic if there isn't a handler. | |
969 | */ | |
970 | 77: bl .save_nvgprs | |
971 | mr r4,r3 | |
972 | addi r3,r1,STACK_FRAME_OVERHEAD | |
973 | li r5,SIGSEGV | |
974 | bl .bad_page_fault | |
975 | b .ret_from_except | |
976 | ||
0ebc4cda BH |
977 | /* here we have a segment miss */ |
978 | do_ste_alloc: | |
979 | bl .ste_allocate /* try to insert stab entry */ | |
980 | cmpdi r3,0 | |
981 | bne- handle_page_fault | |
982 | b fast_exception_return | |
983 | ||
984 | /* | |
985 | * r13 points to the PACA, r9 contains the saved CR, | |
986 | * r11 and r12 contain the saved SRR0 and SRR1. | |
987 | * r9 - r13 are saved in paca->exslb. | |
988 | * We assume we aren't going to take any exceptions during this procedure. | |
989 | * We assume (DAR >> 60) == 0xc. | |
990 | */ | |
991 | .align 7 | |
992 | _GLOBAL(do_stab_bolted) | |
993 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
994 | std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */ | |
995 | ||
996 | /* Hash to the primary group */ | |
997 | ld r10,PACASTABVIRT(r13) | |
998 | mfspr r11,SPRN_DAR | |
999 | srdi r11,r11,28 | |
1000 | rldimi r10,r11,7,52 /* r10 = first ste of the group */ | |
1001 | ||
1002 | /* Calculate VSID */ | |
1003 | /* This is a kernel address, so protovsid = ESID */ | |
1004 | ASM_VSID_SCRAMBLE(r11, r9, 256M) | |
1005 | rldic r9,r11,12,16 /* r9 = vsid << 12 */ | |
1006 | ||
1007 | /* Search the primary group for a free entry */ | |
1008 | 1: ld r11,0(r10) /* Test valid bit of the current ste */ | |
1009 | andi. r11,r11,0x80 | |
1010 | beq 2f | |
1011 | addi r10,r10,16 | |
1012 | andi. r11,r10,0x70 | |
1013 | bne 1b | |
1014 | ||
1015 | /* Stick for only searching the primary group for now. */ | |
1016 | /* At least for now, we use a very simple random castout scheme */ | |
1017 | /* Use the TB as a random number ; OR in 1 to avoid entry 0 */ | |
1018 | mftb r11 | |
1019 | rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */ | |
1020 | ori r11,r11,0x10 | |
1021 | ||
1022 | /* r10 currently points to an ste one past the group of interest */ | |
1023 | /* make it point to the randomly selected entry */ | |
1024 | subi r10,r10,128 | |
1025 | or r10,r10,r11 /* r10 is the entry to invalidate */ | |
1026 | ||
1027 | isync /* mark the entry invalid */ | |
1028 | ld r11,0(r10) | |
1029 | rldicl r11,r11,56,1 /* clear the valid bit */ | |
1030 | rotldi r11,r11,8 | |
1031 | std r11,0(r10) | |
1032 | sync | |
1033 | ||
1034 | clrrdi r11,r11,28 /* Get the esid part of the ste */ | |
1035 | slbie r11 | |
1036 | ||
1037 | 2: std r9,8(r10) /* Store the vsid part of the ste */ | |
1038 | eieio | |
1039 | ||
1040 | mfspr r11,SPRN_DAR /* Get the new esid */ | |
1041 | clrrdi r11,r11,28 /* Permits a full 32b of ESID */ | |
1042 | ori r11,r11,0x90 /* Turn on valid and kp */ | |
1043 | std r11,0(r10) /* Put new entry back into the stab */ | |
1044 | ||
1045 | sync | |
1046 | ||
1047 | /* All done -- return from exception. */ | |
1048 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
1049 | ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */ | |
1050 | ||
1051 | andi. r10,r12,MSR_RI | |
1052 | beq- unrecov_slb | |
1053 | ||
1054 | mtcrf 0x80,r9 /* restore CR */ | |
1055 | ||
1056 | mfmsr r10 | |
1057 | clrrdi r10,r10,2 | |
1058 | mtmsrd r10,1 | |
1059 | ||
1060 | mtspr SPRN_SRR0,r11 | |
1061 | mtspr SPRN_SRR1,r12 | |
1062 | ld r9,PACA_EXSLB+EX_R9(r13) | |
1063 | ld r10,PACA_EXSLB+EX_R10(r13) | |
1064 | ld r11,PACA_EXSLB+EX_R11(r13) | |
1065 | ld r12,PACA_EXSLB+EX_R12(r13) | |
1066 | ld r13,PACA_EXSLB+EX_R13(r13) | |
1067 | rfid | |
1068 | b . /* prevent speculative execution */ | |
1069 | ||
0ebc4cda BH |
1070 | #ifdef CONFIG_PPC_PSERIES |
1071 | /* | |
1072 | * Data area reserved for FWNMI option. | |
1073 | * This address (0x7000) is fixed by the RPA. | |
1074 | */ | |
1075 | .= 0x7000 | |
1076 | .globl fwnmi_data_area | |
1077 | fwnmi_data_area: | |
1078 | #endif /* CONFIG_PPC_PSERIES */ | |
1079 | ||
1080 | /* iSeries does not use the FWNMI stuff, so it is safe to put | |
1081 | * this here, even if we later allow kernels that will boot on | |
1082 | * both pSeries and iSeries */ | |
1083 | #ifdef CONFIG_PPC_ISERIES | |
1084 | . = LPARMAP_PHYS | |
1085 | .globl xLparMap | |
1086 | xLparMap: | |
1087 | .quad HvEsidsToMap /* xNumberEsids */ | |
1088 | .quad HvRangesToMap /* xNumberRanges */ | |
1089 | .quad STAB0_PAGE /* xSegmentTableOffs */ | |
1090 | .zero 40 /* xRsvd */ | |
1091 | /* xEsids (HvEsidsToMap entries of 2 quads) */ | |
1092 | .quad PAGE_OFFSET_ESID /* xKernelEsid */ | |
1093 | .quad PAGE_OFFSET_VSID /* xKernelVsid */ | |
1094 | .quad VMALLOC_START_ESID /* xKernelEsid */ | |
1095 | .quad VMALLOC_START_VSID /* xKernelVsid */ | |
1096 | /* xRanges (HvRangesToMap entries of 3 quads) */ | |
1097 | .quad HvPagesToMap /* xPages */ | |
1098 | .quad 0 /* xOffset */ | |
1099 | .quad PAGE_OFFSET_VSID << (SID_SHIFT - HW_PAGE_SHIFT) /* xVPN */ | |
1100 | ||
1101 | #endif /* CONFIG_PPC_ISERIES */ | |
1102 | ||
1103 | #ifdef CONFIG_PPC_PSERIES | |
1104 | . = 0x8000 | |
1105 | #endif /* CONFIG_PPC_PSERIES */ | |
84493804 BH |
1106 | |
1107 | /* | |
1108 | * Space for CPU0's segment table. | |
1109 | * | |
1110 | * On iSeries, the hypervisor must fill in at least one entry before | |
1111 | * we get control (with relocate on). The address is given to the hv | |
1112 | * as a page number (see xLparMap above), so this must be at a | |
1113 | * fixed address (the linker can't compute (u64)&initial_stab >> | |
1114 | * PAGE_SHIFT). | |
1115 | */ | |
1116 | . = STAB0_OFFSET /* 0x8000 */ | |
1117 | .globl initial_stab | |
1118 | initial_stab: | |
1119 | .space 4096 |