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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
0ebc4cda BH |
2 | /* |
3 | * This file contains the 64-bit "server" PowerPC variant | |
4 | * of the low level exception handling including exception | |
5 | * vectors, exception return, part of the slb and stab | |
6 | * handling and other fixed offset specific things. | |
7 | * | |
8 | * This file is meant to be #included from head_64.S due to | |
25985edc | 9 | * position dependent assembly. |
0ebc4cda BH |
10 | * |
11 | * Most of this originates from head_64.S and thus has the same | |
12 | * copyright history. | |
13 | * | |
14 | */ | |
15 | ||
7230c564 | 16 | #include <asm/hw_irq.h> |
8aa34ab8 | 17 | #include <asm/exception-64s.h> |
46f52210 | 18 | #include <asm/ptrace.h> |
7cba160a | 19 | #include <asm/cpuidle.h> |
da2bc464 | 20 | #include <asm/head-64.h> |
2c86cd18 | 21 | #include <asm/feature-fixups.h> |
890274c2 | 22 | #include <asm/kup.h> |
8aa34ab8 | 23 | |
12a04809 NP |
24 | /* |
25 | * We're short on space and time in the exception prolog, so we can't | |
26 | * use the normal LOAD_REG_IMMEDIATE macro to load the address of label. | |
27 | * Instead we get the base of the kernel from paca->kernelbase and or in the low | |
28 | * part of label. This requires that the label be within 64KB of kernelbase, and | |
29 | * that kernelbase be 64K aligned. | |
30 | */ | |
31 | #define LOAD_HANDLER(reg, label) \ | |
32 | ld reg,PACAKBASE(r13); /* get high part of &label */ \ | |
33 | ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label) | |
34 | ||
35 | #define __LOAD_HANDLER(reg, label) \ | |
36 | ld reg,PACAKBASE(r13); \ | |
37 | ori reg,reg,(ABS_ADDR(label))@l | |
38 | ||
39 | /* | |
40 | * Branches from unrelocated code (e.g., interrupts) to labels outside | |
41 | * head-y require >64K offsets. | |
42 | */ | |
43 | #define __LOAD_FAR_HANDLER(reg, label) \ | |
44 | ld reg,PACAKBASE(r13); \ | |
45 | ori reg,reg,(ABS_ADDR(label))@l; \ | |
46 | addis reg,reg,(ABS_ADDR(label))@h | |
47 | ||
48 | /* Exception register prefixes */ | |
49 | #define EXC_HV 1 | |
50 | #define EXC_STD 0 | |
51 | ||
52 | #if defined(CONFIG_RELOCATABLE) | |
53 | /* | |
54 | * If we support interrupts with relocation on AND we're a relocatable kernel, | |
55 | * we need to use CTR to get to the 2nd level handler. So, save/restore it | |
56 | * when required. | |
57 | */ | |
58 | #define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13) | |
59 | #define GET_CTR(reg, area) ld reg,area+EX_CTR(r13) | |
60 | #define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg | |
61 | #else | |
62 | /* ...else CTR is unused and in register. */ | |
63 | #define SAVE_CTR(reg, area) | |
64 | #define GET_CTR(reg, area) mfctr reg | |
65 | #define RESTORE_CTR(reg, area) | |
66 | #endif | |
67 | ||
68 | /* | |
69 | * PPR save/restore macros used in exceptions-64s.S | |
70 | * Used for P7 or later processors | |
71 | */ | |
72 | #define SAVE_PPR(area, ra) \ | |
73 | BEGIN_FTR_SECTION_NESTED(940) \ | |
74 | ld ra,area+EX_PPR(r13); /* Read PPR from paca */ \ | |
75 | std ra,_PPR(r1); \ | |
76 | END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940) | |
77 | ||
78 | #define RESTORE_PPR_PACA(area, ra) \ | |
79 | BEGIN_FTR_SECTION_NESTED(941) \ | |
80 | ld ra,area+EX_PPR(r13); \ | |
81 | mtspr SPRN_PPR,ra; \ | |
82 | END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941) | |
83 | ||
84 | /* | |
85 | * Get an SPR into a register if the CPU has the given feature | |
86 | */ | |
87 | #define OPT_GET_SPR(ra, spr, ftr) \ | |
88 | BEGIN_FTR_SECTION_NESTED(943) \ | |
89 | mfspr ra,spr; \ | |
90 | END_FTR_SECTION_NESTED(ftr,ftr,943) | |
91 | ||
92 | /* | |
93 | * Set an SPR from a register if the CPU has the given feature | |
94 | */ | |
95 | #define OPT_SET_SPR(ra, spr, ftr) \ | |
96 | BEGIN_FTR_SECTION_NESTED(943) \ | |
97 | mtspr spr,ra; \ | |
98 | END_FTR_SECTION_NESTED(ftr,ftr,943) | |
99 | ||
100 | /* | |
101 | * Save a register to the PACA if the CPU has the given feature | |
102 | */ | |
103 | #define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \ | |
104 | BEGIN_FTR_SECTION_NESTED(943) \ | |
105 | std ra,offset(r13); \ | |
106 | END_FTR_SECTION_NESTED(ftr,ftr,943) | |
107 | ||
108 | .macro EXCEPTION_PROLOG_0 area | |
109 | GET_PACA(r13) | |
110 | std r9,\area\()+EX_R9(r13) /* save r9 */ | |
111 | OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR) | |
112 | HMT_MEDIUM | |
113 | std r10,\area\()+EX_R10(r13) /* save r10 - r12 */ | |
114 | OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR) | |
115 | .endm | |
116 | ||
117 | .macro EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, bitmask | |
118 | OPT_SAVE_REG_TO_PACA(\area\()+EX_PPR, r9, CPU_FTR_HAS_PPR) | |
119 | OPT_SAVE_REG_TO_PACA(\area\()+EX_CFAR, r10, CPU_FTR_CFAR) | |
120 | INTERRUPT_TO_KERNEL | |
121 | SAVE_CTR(r10, \area\()) | |
122 | mfcr r9 | |
123 | .if \kvm | |
124 | KVMTEST \hsrr \vec | |
125 | .endif | |
126 | .if \bitmask | |
127 | lbz r10,PACAIRQSOFTMASK(r13) | |
128 | andi. r10,r10,\bitmask | |
129 | /* Associate vector numbers with bits in paca->irq_happened */ | |
130 | .if \vec == 0x500 || \vec == 0xea0 | |
131 | li r10,PACA_IRQ_EE | |
132 | .elseif \vec == 0x900 | |
133 | li r10,PACA_IRQ_DEC | |
134 | .elseif \vec == 0xa00 || \vec == 0xe80 | |
135 | li r10,PACA_IRQ_DBELL | |
136 | .elseif \vec == 0xe60 | |
137 | li r10,PACA_IRQ_HMI | |
138 | .elseif \vec == 0xf00 | |
139 | li r10,PACA_IRQ_PMI | |
140 | .else | |
141 | .abort "Bad maskable vector" | |
142 | .endif | |
143 | ||
144 | .if \hsrr | |
145 | bne masked_Hinterrupt | |
146 | .else | |
147 | bne masked_interrupt | |
148 | .endif | |
149 | .endif | |
150 | ||
151 | std r11,\area\()+EX_R11(r13) | |
152 | std r12,\area\()+EX_R12(r13) | |
153 | GET_SCRATCH0(r10) | |
154 | std r10,\area\()+EX_R13(r13) | |
155 | .endm | |
156 | ||
157 | .macro EXCEPTION_PROLOG_2_REAL label, hsrr, set_ri | |
158 | ld r10,PACAKMSR(r13) /* get MSR value for kernel */ | |
159 | .if ! \set_ri | |
160 | xori r10,r10,MSR_RI /* Clear MSR_RI */ | |
161 | .endif | |
162 | .if \hsrr | |
163 | mfspr r11,SPRN_HSRR0 /* save HSRR0 */ | |
164 | .else | |
165 | mfspr r11,SPRN_SRR0 /* save SRR0 */ | |
166 | .endif | |
167 | LOAD_HANDLER(r12, \label\()) | |
168 | .if \hsrr | |
169 | mtspr SPRN_HSRR0,r12 | |
170 | mfspr r12,SPRN_HSRR1 /* and HSRR1 */ | |
171 | mtspr SPRN_HSRR1,r10 | |
172 | HRFI_TO_KERNEL | |
173 | .else | |
174 | mtspr SPRN_SRR0,r12 | |
175 | mfspr r12,SPRN_SRR1 /* and SRR1 */ | |
176 | mtspr SPRN_SRR1,r10 | |
177 | RFI_TO_KERNEL | |
178 | .endif | |
179 | b . /* prevent speculative execution */ | |
180 | .endm | |
181 | ||
182 | .macro EXCEPTION_PROLOG_2_VIRT label, hsrr | |
183 | #ifdef CONFIG_RELOCATABLE | |
184 | .if \hsrr | |
185 | mfspr r11,SPRN_HSRR0 /* save HSRR0 */ | |
186 | .else | |
187 | mfspr r11,SPRN_SRR0 /* save SRR0 */ | |
188 | .endif | |
189 | LOAD_HANDLER(r12, \label\()) | |
190 | mtctr r12 | |
191 | .if \hsrr | |
192 | mfspr r12,SPRN_HSRR1 /* and HSRR1 */ | |
193 | .else | |
194 | mfspr r12,SPRN_SRR1 /* and HSRR1 */ | |
195 | .endif | |
196 | li r10,MSR_RI | |
197 | mtmsrd r10,1 /* Set RI (EE=0) */ | |
198 | bctr | |
199 | #else | |
200 | .if \hsrr | |
201 | mfspr r11,SPRN_HSRR0 /* save HSRR0 */ | |
202 | mfspr r12,SPRN_HSRR1 /* and HSRR1 */ | |
203 | .else | |
204 | mfspr r11,SPRN_SRR0 /* save SRR0 */ | |
205 | mfspr r12,SPRN_SRR1 /* and SRR1 */ | |
206 | .endif | |
207 | li r10,MSR_RI | |
208 | mtmsrd r10,1 /* Set RI (EE=0) */ | |
209 | b \label | |
210 | #endif | |
211 | .endm | |
212 | ||
213 | /* | |
214 | * Branch to label using its 0xC000 address. This results in instruction | |
215 | * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned | |
216 | * on using mtmsr rather than rfid. | |
217 | * | |
218 | * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than | |
219 | * load KBASE for a slight optimisation. | |
220 | */ | |
221 | #define BRANCH_TO_C000(reg, label) \ | |
222 | __LOAD_HANDLER(reg, label); \ | |
223 | mtctr reg; \ | |
224 | bctr | |
225 | ||
226 | #ifdef CONFIG_RELOCATABLE | |
12a04809 NP |
227 | #define BRANCH_LINK_TO_FAR(label) \ |
228 | __LOAD_FAR_HANDLER(r12, label); \ | |
229 | mtctr r12; \ | |
230 | bctrl | |
231 | ||
232 | #else | |
12a04809 NP |
233 | #define BRANCH_LINK_TO_FAR(label) \ |
234 | bl label | |
235 | #endif | |
236 | ||
237 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER | |
12a04809 NP |
238 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
239 | /* | |
240 | * If hv is possible, interrupts come into to the hv version | |
241 | * of the kvmppc_interrupt code, which then jumps to the PR handler, | |
242 | * kvmppc_interrupt_pr, if the guest is a PR guest. | |
243 | */ | |
244 | #define kvmppc_interrupt kvmppc_interrupt_hv | |
245 | #else | |
246 | #define kvmppc_interrupt kvmppc_interrupt_pr | |
247 | #endif | |
248 | ||
249 | .macro KVMTEST hsrr, n | |
250 | lbz r10,HSTATE_IN_GUEST(r13) | |
251 | cmpwi r10,0 | |
252 | .if \hsrr | |
253 | bne do_kvm_H\n | |
254 | .else | |
255 | bne do_kvm_\n | |
256 | .endif | |
257 | .endm | |
258 | ||
259 | .macro KVM_HANDLER area, hsrr, n, skip | |
260 | .if \skip | |
261 | cmpwi r10,KVM_GUEST_MODE_SKIP | |
262 | beq 89f | |
263 | .else | |
bf66e3c4 | 264 | BEGIN_FTR_SECTION_NESTED(947) |
12a04809 NP |
265 | ld r10,\area+EX_CFAR(r13) |
266 | std r10,HSTATE_CFAR(r13) | |
bf66e3c4 | 267 | END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947) |
12a04809 NP |
268 | .endif |
269 | ||
bf66e3c4 | 270 | BEGIN_FTR_SECTION_NESTED(948) |
12a04809 NP |
271 | ld r10,\area+EX_PPR(r13) |
272 | std r10,HSTATE_PPR(r13) | |
bf66e3c4 | 273 | END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948) |
12a04809 NP |
274 | ld r10,\area+EX_R10(r13) |
275 | std r12,HSTATE_SCRATCH0(r13) | |
276 | sldi r12,r9,32 | |
277 | /* HSRR variants have the 0x2 bit added to their trap number */ | |
278 | .if \hsrr | |
279 | ori r12,r12,(\n + 0x2) | |
280 | .else | |
281 | ori r12,r12,(\n) | |
282 | .endif | |
64e41351 NP |
283 | |
284 | #ifdef CONFIG_RELOCATABLE | |
285 | /* | |
286 | * KVM requires __LOAD_FAR_HANDLER beause kvmppc_interrupt lives | |
287 | * outside the head section. CONFIG_RELOCATABLE KVM expects CTR | |
288 | * to be saved in HSTATE_SCRATCH1. | |
289 | */ | |
290 | mfctr r9 | |
291 | std r9,HSTATE_SCRATCH1(r13) | |
292 | __LOAD_FAR_HANDLER(r9, kvmppc_interrupt) | |
293 | mtctr r9 | |
294 | ld r9,\area+EX_R9(r13) | |
295 | bctr | |
296 | #else | |
297 | ld r9,\area+EX_R9(r13) | |
298 | b kvmppc_interrupt | |
299 | #endif | |
300 | ||
12a04809 NP |
301 | |
302 | .if \skip | |
303 | 89: mtocrf 0x80,r9 | |
304 | ld r9,\area+EX_R9(r13) | |
305 | ld r10,\area+EX_R10(r13) | |
306 | .if \hsrr | |
307 | b kvmppc_skip_Hinterrupt | |
308 | .else | |
309 | b kvmppc_skip_interrupt | |
310 | .endif | |
311 | .endif | |
312 | .endm | |
313 | ||
314 | #else | |
315 | .macro KVMTEST hsrr, n | |
316 | .endm | |
317 | .macro KVM_HANDLER area, hsrr, n, skip | |
318 | .endm | |
319 | #endif | |
320 | ||
321 | #define EXCEPTION_PROLOG_COMMON_1() \ | |
322 | std r9,_CCR(r1); /* save CR in stackframe */ \ | |
323 | std r11,_NIP(r1); /* save SRR0 in stackframe */ \ | |
324 | std r12,_MSR(r1); /* save SRR1 in stackframe */ \ | |
325 | std r10,0(r1); /* make stack chain pointer */ \ | |
326 | std r0,GPR0(r1); /* save r0 in stackframe */ \ | |
327 | std r10,GPR1(r1); /* save r1 in stackframe */ \ | |
328 | ||
12a04809 NP |
329 | /* Save original regs values from save area to stack frame. */ |
330 | #define EXCEPTION_PROLOG_COMMON_2(area) \ | |
331 | ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ | |
332 | ld r10,area+EX_R10(r13); \ | |
333 | std r9,GPR9(r1); \ | |
334 | std r10,GPR10(r1); \ | |
335 | ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ | |
336 | ld r10,area+EX_R12(r13); \ | |
337 | ld r11,area+EX_R13(r13); \ | |
338 | std r9,GPR11(r1); \ | |
339 | std r10,GPR12(r1); \ | |
340 | std r11,GPR13(r1); \ | |
bf66e3c4 | 341 | BEGIN_FTR_SECTION_NESTED(66); \ |
12a04809 NP |
342 | ld r10,area+EX_CFAR(r13); \ |
343 | std r10,ORIG_GPR3(r1); \ | |
bf66e3c4 | 344 | END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \ |
12a04809 NP |
345 | GET_CTR(r10, area); \ |
346 | std r10,_CTR(r1); | |
347 | ||
d064151f | 348 | #define EXCEPTION_PROLOG_COMMON_3(trap) \ |
12a04809 NP |
349 | std r2,GPR2(r1); /* save r2 in stackframe */ \ |
350 | SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ | |
351 | SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ | |
352 | mflr r9; /* Get LR, later save to stack */ \ | |
353 | ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ | |
354 | std r9,_LINK(r1); \ | |
355 | lbz r10,PACAIRQSOFTMASK(r13); \ | |
356 | mfspr r11,SPRN_XER; /* save XER in stackframe */ \ | |
357 | std r10,SOFTE(r1); \ | |
358 | std r11,_XER(r1); \ | |
d064151f | 359 | li r9,(trap)+1; \ |
12a04809 NP |
360 | std r9,_TRAP(r1); /* set trap number */ \ |
361 | li r10,0; \ | |
362 | ld r11,exception_marker@toc(r2); \ | |
363 | std r10,RESULT(r1); /* clear regs->result */ \ | |
364 | std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ | |
365 | ||
d064151f NP |
366 | /* |
367 | * On entry r13 points to the paca, r9-r13 are saved in the paca, | |
368 | * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and | |
369 | * SRR1, and relocation is on. | |
370 | */ | |
371 | #define EXCEPTION_COMMON(area, trap) \ | |
372 | andi. r10,r12,MSR_PR; /* See if coming from user */ \ | |
373 | mr r10,r1; /* Save r1 */ \ | |
374 | subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ | |
375 | beq- 1f; \ | |
376 | ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ | |
377 | 1: cmpdi cr1,r1,-INT_FRAME_SIZE; /* check if r1 is in userspace */ \ | |
378 | blt+ cr1,3f; /* abort if it is */ \ | |
379 | li r1,(trap); /* will be reloaded later */ \ | |
380 | sth r1,PACA_TRAP_SAVE(r13); \ | |
381 | std r3,area+EX_R3(r13); \ | |
382 | addi r3,r13,area; /* r3 -> where regs are saved*/ \ | |
383 | RESTORE_CTR(r1, area); \ | |
384 | b bad_stack; \ | |
385 | 3: EXCEPTION_PROLOG_COMMON_1(); \ | |
386 | kuap_save_amr_and_lock r9, r10, cr1, cr0; \ | |
387 | beq 4f; /* if from kernel mode */ \ | |
388 | ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \ | |
389 | SAVE_PPR(area, r9); \ | |
390 | 4: EXCEPTION_PROLOG_COMMON_2(area); \ | |
391 | EXCEPTION_PROLOG_COMMON_3(trap); \ | |
392 | ACCOUNT_STOLEN_TIME | |
12a04809 | 393 | |
12a04809 NP |
394 | |
395 | /* | |
d064151f NP |
396 | * Exception where stack is already set in r1, r1 is saved in r10. |
397 | * PPR save and CPU accounting is not done (for some reason). | |
12a04809 NP |
398 | */ |
399 | #define EXCEPTION_COMMON_STACK(area, trap) \ | |
400 | EXCEPTION_PROLOG_COMMON_1(); \ | |
401 | kuap_save_amr_and_lock r9, r10, cr1; \ | |
402 | EXCEPTION_PROLOG_COMMON_2(area); \ | |
403 | EXCEPTION_PROLOG_COMMON_3(trap) | |
404 | ||
d064151f NP |
405 | |
406 | #define RUNLATCH_ON \ | |
407 | BEGIN_FTR_SECTION \ | |
408 | ld r3, PACA_THREAD_INFO(r13); \ | |
409 | ld r4,TI_LOCAL_FLAGS(r3); \ | |
410 | andi. r0,r4,_TLF_RUNLATCH; \ | |
411 | beql ppc64_runlatch_on_trampoline; \ | |
412 | END_FTR_SECTION_IFSET(CPU_FTR_CTRL) | |
413 | ||
12a04809 NP |
414 | /* |
415 | * When the idle code in power4_idle puts the CPU into NAP mode, | |
416 | * it has to do so in a loop, and relies on the external interrupt | |
417 | * and decrementer interrupt entry code to get it out of the loop. | |
418 | * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags | |
419 | * to signal that it is in the loop and needs help to get out. | |
420 | */ | |
421 | #ifdef CONFIG_PPC_970_NAP | |
422 | #define FINISH_NAP \ | |
423 | BEGIN_FTR_SECTION \ | |
424 | ld r11, PACA_THREAD_INFO(r13); \ | |
425 | ld r9,TI_LOCAL_FLAGS(r11); \ | |
426 | andi. r10,r9,_TLF_NAPPING; \ | |
427 | bnel power4_fixup_nap; \ | |
428 | END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) | |
429 | #else | |
430 | #define FINISH_NAP | |
431 | #endif | |
432 | ||
a0502434 NP |
433 | /* |
434 | * Following are the BOOK3S exception handler helper macros. | |
435 | * Handlers come in a number of types, and each type has a number of varieties. | |
436 | * | |
437 | * EXC_REAL_* - real, unrelocated exception vectors | |
438 | * EXC_VIRT_* - virt (AIL), unrelocated exception vectors | |
439 | * TRAMP_REAL_* - real, unrelocated helpers (virt can call these) | |
440 | * TRAMP_VIRT_* - virt, unreloc helpers (in practice, real can use) | |
441 | * TRAMP_KVM - KVM handlers that get put into real, unrelocated | |
442 | * EXC_COMMON - virt, relocated common handlers | |
443 | * | |
444 | * The EXC handlers are given a name, and branch to name_common, or the | |
445 | * appropriate KVM or masking function. Vector handler verieties are as | |
446 | * follows: | |
447 | * | |
448 | * EXC_{REAL|VIRT}_BEGIN/END - used to open-code the exception | |
449 | * | |
450 | * EXC_{REAL|VIRT} - standard exception | |
451 | * | |
452 | * EXC_{REAL|VIRT}_suffix | |
453 | * where _suffix is: | |
454 | * - _MASKABLE - maskable exception | |
455 | * - _OOL - out of line with trampoline to common handler | |
456 | * - _HV - HV exception | |
457 | * | |
458 | * There can be combinations, e.g., EXC_VIRT_OOL_MASKABLE_HV | |
459 | * | |
460 | * The one unusual case is __EXC_REAL_OOL_HV_DIRECT, which is | |
461 | * an OOL vector that branches to a specified handler rather than the usual | |
462 | * trampoline that goes to common. It, and other underscore macros, should | |
463 | * be used with care. | |
464 | * | |
465 | * KVM handlers come in the following verieties: | |
466 | * TRAMP_KVM | |
467 | * TRAMP_KVM_SKIP | |
468 | * TRAMP_KVM_HV | |
469 | * TRAMP_KVM_HV_SKIP | |
470 | * | |
471 | * COMMON handlers come in the following verieties: | |
472 | * EXC_COMMON_BEGIN/END - used to open-code the handler | |
473 | * EXC_COMMON | |
474 | * EXC_COMMON_ASYNC | |
475 | * | |
476 | * TRAMP_REAL and TRAMP_VIRT can be used with BEGIN/END. KVM | |
477 | * and OOL handlers are implemented as types of TRAMP and TRAMP_VIRT handlers. | |
478 | */ | |
479 | ||
480 | #define __EXC_REAL(name, start, size, area) \ | |
481 | EXC_REAL_BEGIN(name, start, size); \ | |
482 | SET_SCRATCH0(r13); /* save r13 */ \ | |
483 | EXCEPTION_PROLOG_0 area ; \ | |
484 | EXCEPTION_PROLOG_1 EXC_STD, area, 1, start, 0 ; \ | |
485 | EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 ; \ | |
486 | EXC_REAL_END(name, start, size) | |
487 | ||
488 | #define EXC_REAL(name, start, size) \ | |
489 | __EXC_REAL(name, start, size, PACA_EXGEN) | |
490 | ||
491 | #define __EXC_VIRT(name, start, size, realvec, area) \ | |
492 | EXC_VIRT_BEGIN(name, start, size); \ | |
493 | SET_SCRATCH0(r13); /* save r13 */ \ | |
494 | EXCEPTION_PROLOG_0 area ; \ | |
495 | EXCEPTION_PROLOG_1 EXC_STD, area, 0, realvec, 0; \ | |
496 | EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD ; \ | |
497 | EXC_VIRT_END(name, start, size) | |
498 | ||
499 | #define EXC_VIRT(name, start, size, realvec) \ | |
500 | __EXC_VIRT(name, start, size, realvec, PACA_EXGEN) | |
501 | ||
502 | #define EXC_REAL_MASKABLE(name, start, size, bitmask) \ | |
503 | EXC_REAL_BEGIN(name, start, size); \ | |
504 | SET_SCRATCH0(r13); /* save r13 */ \ | |
505 | EXCEPTION_PROLOG_0 PACA_EXGEN ; \ | |
506 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, start, bitmask ; \ | |
507 | EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 ; \ | |
508 | EXC_REAL_END(name, start, size) | |
509 | ||
510 | #define EXC_VIRT_MASKABLE(name, start, size, realvec, bitmask) \ | |
511 | EXC_VIRT_BEGIN(name, start, size); \ | |
512 | SET_SCRATCH0(r13); /* save r13 */ \ | |
513 | EXCEPTION_PROLOG_0 PACA_EXGEN ; \ | |
514 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, realvec, bitmask ; \ | |
515 | EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD ; \ | |
516 | EXC_VIRT_END(name, start, size) | |
517 | ||
518 | #define EXC_REAL_HV(name, start, size) \ | |
519 | EXC_REAL_BEGIN(name, start, size); \ | |
520 | SET_SCRATCH0(r13); /* save r13 */ \ | |
521 | EXCEPTION_PROLOG_0 PACA_EXGEN; \ | |
522 | EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, start, 0 ; \ | |
523 | EXCEPTION_PROLOG_2_REAL name##_common, EXC_HV, 1 ; \ | |
524 | EXC_REAL_END(name, start, size) | |
525 | ||
526 | #define EXC_VIRT_HV(name, start, size, realvec) \ | |
527 | EXC_VIRT_BEGIN(name, start, size); \ | |
528 | SET_SCRATCH0(r13); /* save r13 */ \ | |
529 | EXCEPTION_PROLOG_0 PACA_EXGEN; \ | |
530 | EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, 0 ; \ | |
531 | EXCEPTION_PROLOG_2_VIRT name##_common, EXC_HV ; \ | |
532 | EXC_VIRT_END(name, start, size) | |
533 | ||
534 | #define __EXC_REAL_OOL(name, start, size) \ | |
535 | EXC_REAL_BEGIN(name, start, size); \ | |
536 | SET_SCRATCH0(r13); \ | |
537 | EXCEPTION_PROLOG_0 PACA_EXGEN ; \ | |
538 | b tramp_real_##name ; \ | |
539 | EXC_REAL_END(name, start, size) | |
540 | ||
541 | #define __TRAMP_REAL_OOL(name, vec) \ | |
542 | TRAMP_REAL_BEGIN(tramp_real_##name); \ | |
543 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec, 0 ; \ | |
544 | EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 | |
545 | ||
546 | #define EXC_REAL_OOL(name, start, size) \ | |
547 | __EXC_REAL_OOL(name, start, size); \ | |
548 | __TRAMP_REAL_OOL(name, start) | |
549 | ||
550 | #define __EXC_REAL_OOL_MASKABLE(name, start, size) \ | |
551 | __EXC_REAL_OOL(name, start, size) | |
552 | ||
553 | #define __TRAMP_REAL_OOL_MASKABLE(name, vec, bitmask) \ | |
554 | TRAMP_REAL_BEGIN(tramp_real_##name); \ | |
555 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec, bitmask ; \ | |
556 | EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 | |
557 | ||
558 | #define EXC_REAL_OOL_MASKABLE(name, start, size, bitmask) \ | |
559 | __EXC_REAL_OOL_MASKABLE(name, start, size); \ | |
560 | __TRAMP_REAL_OOL_MASKABLE(name, start, bitmask) | |
561 | ||
562 | #define __EXC_REAL_OOL_HV_DIRECT(name, start, size, handler) \ | |
563 | EXC_REAL_BEGIN(name, start, size); \ | |
564 | SET_SCRATCH0(r13); \ | |
565 | EXCEPTION_PROLOG_0 PACA_EXGEN ; \ | |
566 | b handler; \ | |
567 | EXC_REAL_END(name, start, size) | |
568 | ||
569 | #define __EXC_REAL_OOL_HV(name, start, size) \ | |
570 | __EXC_REAL_OOL(name, start, size) | |
571 | ||
572 | #define __TRAMP_REAL_OOL_HV(name, vec) \ | |
573 | TRAMP_REAL_BEGIN(tramp_real_##name); \ | |
574 | EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, 0 ; \ | |
575 | EXCEPTION_PROLOG_2_REAL name##_common, EXC_HV, 1 | |
576 | ||
577 | #define EXC_REAL_OOL_HV(name, start, size) \ | |
578 | __EXC_REAL_OOL_HV(name, start, size); \ | |
579 | __TRAMP_REAL_OOL_HV(name, start) | |
580 | ||
581 | #define __EXC_REAL_OOL_MASKABLE_HV(name, start, size) \ | |
582 | __EXC_REAL_OOL(name, start, size) | |
583 | ||
584 | #define __TRAMP_REAL_OOL_MASKABLE_HV(name, vec, bitmask) \ | |
585 | TRAMP_REAL_BEGIN(tramp_real_##name); \ | |
586 | EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, bitmask ; \ | |
587 | EXCEPTION_PROLOG_2_REAL name##_common, EXC_HV, 1 | |
588 | ||
589 | #define EXC_REAL_OOL_MASKABLE_HV(name, start, size, bitmask) \ | |
590 | __EXC_REAL_OOL_MASKABLE_HV(name, start, size); \ | |
591 | __TRAMP_REAL_OOL_MASKABLE_HV(name, start, bitmask) | |
592 | ||
593 | #define __EXC_VIRT_OOL(name, start, size) \ | |
594 | EXC_VIRT_BEGIN(name, start, size); \ | |
595 | SET_SCRATCH0(r13); \ | |
596 | EXCEPTION_PROLOG_0 PACA_EXGEN ; \ | |
597 | b tramp_virt_##name; \ | |
598 | EXC_VIRT_END(name, start, size) | |
599 | ||
600 | #define __TRAMP_VIRT_OOL(name, realvec) \ | |
601 | TRAMP_VIRT_BEGIN(tramp_virt_##name); \ | |
602 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, vec, 0 ; \ | |
603 | EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD | |
604 | ||
605 | #define EXC_VIRT_OOL(name, start, size, realvec) \ | |
606 | __EXC_VIRT_OOL(name, start, size); \ | |
607 | __TRAMP_VIRT_OOL(name, realvec) | |
608 | ||
609 | #define __EXC_VIRT_OOL_MASKABLE(name, start, size) \ | |
610 | __EXC_VIRT_OOL(name, start, size) | |
611 | ||
612 | #define __TRAMP_VIRT_OOL_MASKABLE(name, realvec, bitmask) \ | |
613 | TRAMP_VIRT_BEGIN(tramp_virt_##name); \ | |
614 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, realvec, bitmask ; \ | |
615 | EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 | |
616 | ||
617 | #define EXC_VIRT_OOL_MASKABLE(name, start, size, realvec, bitmask) \ | |
618 | __EXC_VIRT_OOL_MASKABLE(name, start, size); \ | |
619 | __TRAMP_VIRT_OOL_MASKABLE(name, realvec, bitmask) | |
620 | ||
621 | #define __EXC_VIRT_OOL_HV(name, start, size) \ | |
622 | __EXC_VIRT_OOL(name, start, size) | |
623 | ||
624 | #define __TRAMP_VIRT_OOL_HV(name, realvec) \ | |
625 | TRAMP_VIRT_BEGIN(tramp_virt_##name); \ | |
626 | EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, 0 ; \ | |
627 | EXCEPTION_PROLOG_2_VIRT name##_common, EXC_HV | |
628 | ||
629 | #define EXC_VIRT_OOL_HV(name, start, size, realvec) \ | |
630 | __EXC_VIRT_OOL_HV(name, start, size); \ | |
631 | __TRAMP_VIRT_OOL_HV(name, realvec) | |
632 | ||
633 | #define __EXC_VIRT_OOL_MASKABLE_HV(name, start, size) \ | |
634 | __EXC_VIRT_OOL(name, start, size) | |
635 | ||
636 | #define __TRAMP_VIRT_OOL_MASKABLE_HV(name, realvec, bitmask) \ | |
637 | TRAMP_VIRT_BEGIN(tramp_virt_##name); \ | |
638 | EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, bitmask ; \ | |
639 | EXCEPTION_PROLOG_2_VIRT name##_common, EXC_HV | |
640 | ||
641 | #define EXC_VIRT_OOL_MASKABLE_HV(name, start, size, realvec, bitmask) \ | |
642 | __EXC_VIRT_OOL_MASKABLE_HV(name, start, size); \ | |
643 | __TRAMP_VIRT_OOL_MASKABLE_HV(name, realvec, bitmask) | |
644 | ||
645 | #define TRAMP_KVM(area, n) \ | |
646 | TRAMP_KVM_BEGIN(do_kvm_##n); \ | |
647 | KVM_HANDLER area, EXC_STD, n, 0 | |
648 | ||
649 | #define TRAMP_KVM_SKIP(area, n) \ | |
650 | TRAMP_KVM_BEGIN(do_kvm_##n); \ | |
651 | KVM_HANDLER area, EXC_STD, n, 1 | |
652 | ||
653 | #define TRAMP_KVM_HV(area, n) \ | |
654 | TRAMP_KVM_BEGIN(do_kvm_H##n); \ | |
655 | KVM_HANDLER area, EXC_HV, n, 0 | |
656 | ||
657 | #define TRAMP_KVM_HV_SKIP(area, n) \ | |
658 | TRAMP_KVM_BEGIN(do_kvm_H##n); \ | |
659 | KVM_HANDLER area, EXC_HV, n, 1 | |
660 | ||
661 | #define EXC_COMMON(name, realvec, hdlr) \ | |
662 | EXC_COMMON_BEGIN(name); \ | |
663 | EXCEPTION_COMMON(PACA_EXGEN, realvec); \ | |
664 | bl save_nvgprs; \ | |
665 | RECONCILE_IRQ_STATE(r10, r11); \ | |
666 | addi r3,r1,STACK_FRAME_OVERHEAD; \ | |
667 | bl hdlr; \ | |
668 | b ret_from_except | |
669 | ||
670 | /* | |
671 | * Like EXC_COMMON, but for exceptions that can occur in the idle task and | |
672 | * therefore need the special idle handling (finish nap and runlatch) | |
673 | */ | |
674 | #define EXC_COMMON_ASYNC(name, realvec, hdlr) \ | |
675 | EXC_COMMON_BEGIN(name); \ | |
676 | EXCEPTION_COMMON(PACA_EXGEN, realvec); \ | |
677 | FINISH_NAP; \ | |
678 | RECONCILE_IRQ_STATE(r10, r11); \ | |
679 | RUNLATCH_ON; \ | |
680 | addi r3,r1,STACK_FRAME_OVERHEAD; \ | |
681 | bl hdlr; \ | |
682 | b ret_from_except_lite | |
683 | ||
12a04809 | 684 | |
0ebc4cda | 685 | /* |
57f26649 NP |
686 | * There are a few constraints to be concerned with. |
687 | * - Real mode exceptions code/data must be located at their physical location. | |
688 | * - Virtual mode exceptions must be mapped at their 0xc000... location. | |
689 | * - Fixed location code must not call directly beyond the __end_interrupts | |
690 | * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence | |
691 | * must be used. | |
692 | * - LOAD_HANDLER targets must be within first 64K of physical 0 / | |
693 | * virtual 0xc00... | |
694 | * - Conditional branch targets must be within +/-32K of caller. | |
695 | * | |
696 | * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and | |
697 | * therefore don't have to run in physically located code or rfid to | |
698 | * virtual mode kernel code. However on relocatable kernels they do have | |
699 | * to branch to KERNELBASE offset because the rest of the kernel (outside | |
700 | * the exception vectors) may be located elsewhere. | |
701 | * | |
702 | * Virtual exceptions correspond with physical, except their entry points | |
703 | * are offset by 0xc000000000000000 and also tend to get an added 0x4000 | |
704 | * offset applied. Virtual exceptions are enabled with the Alternate | |
705 | * Interrupt Location (AIL) bit set in the LPCR. However this does not | |
706 | * guarantee they will be delivered virtually. Some conditions (see the ISA) | |
707 | * cause exceptions to be delivered in real mode. | |
708 | * | |
709 | * It's impossible to receive interrupts below 0x300 via AIL. | |
710 | * | |
711 | * KVM: None of the virtual exceptions are from the guest. Anything that | |
712 | * escalated to HV=1 from HV=0 is delivered via real mode handlers. | |
713 | * | |
714 | * | |
0ebc4cda BH |
715 | * We layout physical memory as follows: |
716 | * 0x0000 - 0x00ff : Secondary processor spin code | |
57f26649 NP |
717 | * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors |
718 | * 0x1900 - 0x3fff : Real mode trampolines | |
719 | * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors | |
720 | * 0x5900 - 0x6fff : Relon mode trampolines | |
0ebc4cda | 721 | * 0x7000 - 0x7fff : FWNMI data area |
57f26649 NP |
722 | * 0x8000 - .... : Common interrupt handlers, remaining early |
723 | * setup code, rest of kernel. | |
e0319829 NP |
724 | * |
725 | * We could reclaim 0x4000-0x42ff for real mode trampolines if the space | |
726 | * is necessary. Until then it's more consistent to explicitly put VIRT_NONE | |
727 | * vectors there. | |
57f26649 NP |
728 | */ |
729 | OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) | |
730 | OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000) | |
731 | OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900) | |
732 | OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) | |
ccd47702 NP |
733 | |
734 | #ifdef CONFIG_PPC_POWERNV | |
bd3524fe NP |
735 | .globl start_real_trampolines |
736 | .globl end_real_trampolines | |
737 | .globl start_virt_trampolines | |
738 | .globl end_virt_trampolines | |
ccd47702 NP |
739 | #endif |
740 | ||
57f26649 NP |
741 | #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) |
742 | /* | |
743 | * Data area reserved for FWNMI option. | |
744 | * This address (0x7000) is fixed by the RPA. | |
745 | * pseries and powernv need to keep the whole page from | |
746 | * 0x7000 to 0x8000 free for use by the firmware | |
0ebc4cda | 747 | */ |
57f26649 NP |
748 | ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) |
749 | OPEN_TEXT_SECTION(0x8000) | |
750 | #else | |
751 | OPEN_TEXT_SECTION(0x7000) | |
752 | #endif | |
753 | ||
754 | USE_FIXED_SECTION(real_vectors) | |
755 | ||
0ebc4cda BH |
756 | /* |
757 | * This is the start of the interrupt handlers for pSeries | |
758 | * This code runs with relocation off. | |
759 | * Code from here to __end_interrupts gets copied down to real | |
760 | * address 0x100 when we are running a relocatable kernel. | |
761 | * Therefore any relative branches in this section must only | |
762 | * branch to labels in this section. | |
763 | */ | |
0ebc4cda BH |
764 | .globl __start_interrupts |
765 | __start_interrupts: | |
766 | ||
e0319829 | 767 | /* No virt vectors corresponding with 0x0..0x100 */ |
1a6822d1 | 768 | EXC_VIRT_NONE(0x4000, 0x100) |
e0319829 | 769 | |
fb479e44 | 770 | |
a7c1ca19 NP |
771 | EXC_REAL_BEGIN(system_reset, 0x100, 0x100) |
772 | SET_SCRATCH0(r13) | |
5dba1d50 | 773 | EXCEPTION_PROLOG_0 PACA_EXNMI |
a7c1ca19 NP |
774 | |
775 | /* This is EXCEPTION_PROLOG_1 with the idle feature section added */ | |
776 | OPT_SAVE_REG_TO_PACA(PACA_EXNMI+EX_PPR, r9, CPU_FTR_HAS_PPR) | |
777 | OPT_SAVE_REG_TO_PACA(PACA_EXNMI+EX_CFAR, r10, CPU_FTR_CFAR) | |
778 | INTERRUPT_TO_KERNEL | |
779 | SAVE_CTR(r10, PACA_EXNMI) | |
780 | mfcr r9 | |
781 | ||
948cf67c | 782 | #ifdef CONFIG_PPC_P7_NAP |
fb479e44 NP |
783 | /* |
784 | * If running native on arch 2.06 or later, check if we are waking up | |
ba6d334a BH |
785 | * from nap/sleep/winkle, and branch to idle handler. This tests SRR1 |
786 | * bits 46:47. A non-0 value indicates that we are coming from a power | |
787 | * saving state. The idle wakeup handler initially runs in real mode, | |
788 | * but we branch to the 0xc000... address so we can turn on relocation | |
789 | * with mtmsr. | |
948cf67c | 790 | */ |
bf66e3c4 | 791 | BEGIN_FTR_SECTION |
a7c1ca19 NP |
792 | mfspr r10,SPRN_SRR1 |
793 | rlwinm. r10,r10,47-31,30,31 | |
794 | beq- 1f | |
795 | cmpwi cr1,r10,2 | |
796 | mfspr r3,SPRN_SRR1 | |
797 | bltlr cr1 /* no state loss, return to idle caller */ | |
798 | BRANCH_TO_C000(r10, system_reset_idle_common) | |
799 | 1: | |
bf66e3c4 | 800 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
fb479e44 | 801 | #endif |
371fefd6 | 802 | |
a7c1ca19 NP |
803 | KVMTEST EXC_STD 0x100 |
804 | std r11,PACA_EXNMI+EX_R11(r13) | |
805 | std r12,PACA_EXNMI+EX_R12(r13) | |
806 | GET_SCRATCH0(r10) | |
807 | std r10,PACA_EXNMI+EX_R13(r13) | |
808 | ||
809 | EXCEPTION_PROLOG_2_REAL system_reset_common, EXC_STD, 0 | |
c4f3b52c NP |
810 | /* |
811 | * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is | |
812 | * being used, so a nested NMI exception would corrupt it. | |
813 | */ | |
fb479e44 | 814 | |
1a6822d1 NP |
815 | EXC_REAL_END(system_reset, 0x100, 0x100) |
816 | EXC_VIRT_NONE(0x4100, 0x100) | |
6de6638b | 817 | TRAMP_KVM(PACA_EXNMI, 0x100) |
fb479e44 NP |
818 | |
819 | #ifdef CONFIG_PPC_P7_NAP | |
820 | EXC_COMMON_BEGIN(system_reset_idle_common) | |
10d91611 NP |
821 | /* |
822 | * This must be a direct branch (without linker branch stub) because | |
823 | * we can not use TOC at this point as r2 may not be restored yet. | |
824 | */ | |
825 | b idle_return_gpr_loss | |
371fefd6 PM |
826 | #endif |
827 | ||
a3d96f70 | 828 | EXC_COMMON_BEGIN(system_reset_common) |
c4f3b52c NP |
829 | /* |
830 | * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able | |
831 | * to recover, but nested NMI will notice in_nmi and not recover | |
832 | * because of the use of the NMI stack. in_nmi reentrancy is tested in | |
833 | * system_reset_exception. | |
834 | */ | |
835 | lhz r10,PACA_IN_NMI(r13) | |
836 | addi r10,r10,1 | |
837 | sth r10,PACA_IN_NMI(r13) | |
838 | li r10,MSR_RI | |
839 | mtmsrd r10,1 | |
aca79d2b | 840 | |
b1ee8a3d NP |
841 | mr r10,r1 |
842 | ld r1,PACA_NMI_EMERG_SP(r13) | |
843 | subi r1,r1,INT_FRAME_SIZE | |
47169fba NP |
844 | EXCEPTION_COMMON_STACK(PACA_EXNMI, 0x100) |
845 | bl save_nvgprs | |
846 | /* | |
847 | * Set IRQS_ALL_DISABLED unconditionally so arch_irqs_disabled does | |
848 | * the right thing. We do not want to reconcile because that goes | |
849 | * through irq tracing which we don't want in NMI. | |
850 | * | |
851 | * Save PACAIRQHAPPENED because some code will do a hard disable | |
852 | * (e.g., xmon). So we want to restore this back to where it was | |
853 | * when we return. DAR is unused in the stack, so save it there. | |
854 | */ | |
855 | li r10,IRQS_ALL_DISABLED | |
856 | stb r10,PACAIRQSOFTMASK(r13) | |
857 | lbz r10,PACAIRQHAPPENED(r13) | |
858 | std r10,_DAR(r1) | |
859 | ||
c06075f3 NP |
860 | addi r3,r1,STACK_FRAME_OVERHEAD |
861 | bl system_reset_exception | |
15b4dd79 NP |
862 | |
863 | /* This (and MCE) can be simplified with mtmsrd L=1 */ | |
864 | /* Clear MSR_RI before setting SRR0 and SRR1. */ | |
865 | li r0,MSR_RI | |
866 | mfmsr r9 | |
867 | andc r9,r9,r0 | |
868 | mtmsrd r9,1 | |
c4f3b52c NP |
869 | |
870 | /* | |
15b4dd79 | 871 | * MSR_RI is clear, now we can decrement paca->in_nmi. |
c4f3b52c NP |
872 | */ |
873 | lhz r10,PACA_IN_NMI(r13) | |
874 | subi r10,r10,1 | |
875 | sth r10,PACA_IN_NMI(r13) | |
876 | ||
15b4dd79 NP |
877 | /* |
878 | * Restore soft mask settings. | |
879 | */ | |
880 | ld r10,_DAR(r1) | |
881 | stb r10,PACAIRQHAPPENED(r13) | |
882 | ld r10,SOFTE(r1) | |
883 | stb r10,PACAIRQSOFTMASK(r13) | |
884 | ||
885 | /* | |
886 | * Keep below code in synch with MACHINE_CHECK_HANDLER_WINDUP. | |
887 | * Should share common bits... | |
888 | */ | |
889 | ||
890 | /* Move original SRR0 and SRR1 into the respective regs */ | |
891 | ld r9,_MSR(r1) | |
892 | mtspr SPRN_SRR1,r9 | |
893 | ld r3,_NIP(r1) | |
894 | mtspr SPRN_SRR0,r3 | |
895 | ld r9,_CTR(r1) | |
896 | mtctr r9 | |
897 | ld r9,_XER(r1) | |
898 | mtxer r9 | |
899 | ld r9,_LINK(r1) | |
900 | mtlr r9 | |
901 | REST_GPR(0, r1) | |
902 | REST_8GPRS(2, r1) | |
903 | REST_GPR(10, r1) | |
904 | ld r11,_CCR(r1) | |
905 | mtcr r11 | |
906 | REST_GPR(11, r1) | |
907 | REST_2GPRS(12, r1) | |
908 | /* restore original r1. */ | |
909 | ld r1,GPR1(r1) | |
910 | RFI_TO_USER_OR_KERNEL | |
582baf44 NP |
911 | |
912 | #ifdef CONFIG_PPC_PSERIES | |
913 | /* | |
914 | * Vectors for the FWNMI option. Share common code. | |
915 | */ | |
916 | TRAMP_REAL_BEGIN(system_reset_fwnmi) | |
917 | SET_SCRATCH0(r13) /* save r13 */ | |
fc557537 NP |
918 | /* See comment at system_reset exception, don't turn on RI */ |
919 | EXCEPTION_PROLOG_0 PACA_EXNMI | |
920 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXNMI, 0, 0x100, 0 | |
921 | EXCEPTION_PROLOG_2_REAL system_reset_common, EXC_STD, 0 | |
922 | ||
582baf44 NP |
923 | #endif /* CONFIG_PPC_PSERIES */ |
924 | ||
0ebc4cda | 925 | |
1a6822d1 | 926 | EXC_REAL_BEGIN(machine_check, 0x200, 0x100) |
b01c8b54 PM |
927 | /* This is moved out of line as it can be patched by FW, but |
928 | * some code path might still want to branch into the original | |
929 | * vector | |
930 | */ | |
1707dd16 | 931 | SET_SCRATCH0(r13) /* save r13 */ |
5dba1d50 | 932 | EXCEPTION_PROLOG_0 PACA_EXMC |
1e9b4507 | 933 | BEGIN_FTR_SECTION |
db7d31ac | 934 | b machine_check_common_early |
1e9b4507 | 935 | FTR_SECTION_ELSE |
1707dd16 | 936 | b machine_check_pSeries_0 |
1e9b4507 | 937 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
1a6822d1 NP |
938 | EXC_REAL_END(machine_check, 0x200, 0x100) |
939 | EXC_VIRT_NONE(0x4200, 0x100) | |
db7d31ac | 940 | TRAMP_REAL_BEGIN(machine_check_common_early) |
fa4cf6b7 | 941 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 0, 0x200, 0 |
afcf0095 NP |
942 | /* |
943 | * Register contents: | |
944 | * R13 = PACA | |
945 | * R9 = CR | |
946 | * Original R9 to R13 is saved on PACA_EXMC | |
947 | * | |
948 | * Switch to mc_emergency stack and handle re-entrancy (we limit | |
949 | * the nested MCE upto level 4 to avoid stack overflow). | |
950 | * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 | |
951 | * | |
952 | * We use paca->in_mce to check whether this is the first entry or | |
953 | * nested machine check. We increment paca->in_mce to track nested | |
954 | * machine checks. | |
955 | * | |
956 | * If this is the first entry then set stack pointer to | |
957 | * paca->mc_emergency_sp, otherwise r1 is already pointing to | |
958 | * stack frame on mc_emergency stack. | |
959 | * | |
960 | * NOTE: We are here with MSR_ME=0 (off), which means we risk a | |
961 | * checkstop if we get another machine check exception before we do | |
962 | * rfid with MSR_ME=1. | |
1945bc45 NP |
963 | * |
964 | * This interrupt can wake directly from idle. If that is the case, | |
965 | * the machine check is handled then the idle wakeup code is called | |
2bf1071a | 966 | * to restore state. |
afcf0095 NP |
967 | */ |
968 | mr r11,r1 /* Save r1 */ | |
969 | lhz r10,PACA_IN_MCE(r13) | |
970 | cmpwi r10,0 /* Are we in nested machine check */ | |
971 | bne 0f /* Yes, we are. */ | |
972 | /* First machine check entry */ | |
973 | ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ | |
974 | 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
975 | addi r10,r10,1 /* increment paca->in_mce */ | |
976 | sth r10,PACA_IN_MCE(r13) | |
977 | /* Limit nested MCE to level 4 to avoid stack overflow */ | |
ba41e1e1 | 978 | cmpwi r10,MAX_MCE_DEPTH |
afcf0095 NP |
979 | bgt 2f /* Check if we hit limit of 4 */ |
980 | std r11,GPR1(r1) /* Save r1 on the stack. */ | |
981 | std r11,0(r1) /* make stack chain pointer */ | |
982 | mfspr r11,SPRN_SRR0 /* Save SRR0 */ | |
983 | std r11,_NIP(r1) | |
984 | mfspr r11,SPRN_SRR1 /* Save SRR1 */ | |
985 | std r11,_MSR(r1) | |
986 | mfspr r11,SPRN_DAR /* Save DAR */ | |
987 | std r11,_DAR(r1) | |
988 | mfspr r11,SPRN_DSISR /* Save DSISR */ | |
989 | std r11,_DSISR(r1) | |
990 | std r9,_CCR(r1) /* Save CR in stackframe */ | |
e13e7cd4 | 991 | /* We don't touch AMR here, we never go to virtual mode */ |
afcf0095 NP |
992 | /* Save r9 through r13 from EXMC save area to stack frame. */ |
993 | EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) | |
994 | mfmsr r11 /* get MSR value */ | |
db7d31ac | 995 | BEGIN_FTR_SECTION |
afcf0095 | 996 | ori r11,r11,MSR_ME /* turn on ME bit */ |
db7d31ac | 997 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) |
afcf0095 NP |
998 | ori r11,r11,MSR_RI /* turn on RI bit */ |
999 | LOAD_HANDLER(r12, machine_check_handle_early) | |
1000 | 1: mtspr SPRN_SRR0,r12 | |
1001 | mtspr SPRN_SRR1,r11 | |
222f20f1 | 1002 | RFI_TO_KERNEL |
afcf0095 NP |
1003 | b . /* prevent speculative execution */ |
1004 | 2: | |
1005 | /* Stack overflow. Stay on emergency stack and panic. | |
1006 | * Keep the ME bit off while panic-ing, so that if we hit | |
1007 | * another machine check we checkstop. | |
1008 | */ | |
1009 | addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ | |
1010 | ld r11,PACAKMSR(r13) | |
1011 | LOAD_HANDLER(r12, unrecover_mce) | |
1012 | li r10,MSR_ME | |
1013 | andc r11,r11,r10 /* Turn off MSR_ME */ | |
1014 | b 1b | |
1015 | b . /* prevent speculative execution */ | |
afcf0095 NP |
1016 | |
1017 | TRAMP_REAL_BEGIN(machine_check_pSeries) | |
1018 | .globl machine_check_fwnmi | |
1019 | machine_check_fwnmi: | |
1020 | SET_SCRATCH0(r13) /* save r13 */ | |
5dba1d50 | 1021 | EXCEPTION_PROLOG_0 PACA_EXMC |
a43c1590 | 1022 | BEGIN_FTR_SECTION |
db7d31ac | 1023 | b machine_check_common_early |
a43c1590 | 1024 | END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE) |
afcf0095 | 1025 | machine_check_pSeries_0: |
fa4cf6b7 | 1026 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 1, 0x200, 0 |
afcf0095 | 1027 | /* |
83a980f7 NP |
1028 | * MSR_RI is not enabled, because PACA_EXMC is being used, so a |
1029 | * nested machine check corrupts it. machine_check_common enables | |
1030 | * MSR_RI. | |
afcf0095 | 1031 | */ |
2d046308 | 1032 | EXCEPTION_PROLOG_2_REAL machine_check_common, EXC_STD, 0 |
afcf0095 NP |
1033 | |
1034 | TRAMP_KVM_SKIP(PACA_EXMC, 0x200) | |
1035 | ||
1036 | EXC_COMMON_BEGIN(machine_check_common) | |
1037 | /* | |
1038 | * Machine check is different because we use a different | |
1039 | * save area: PACA_EXMC instead of PACA_EXGEN. | |
1040 | */ | |
1041 | mfspr r10,SPRN_DAR | |
1042 | std r10,PACA_EXMC+EX_DAR(r13) | |
1043 | mfspr r10,SPRN_DSISR | |
1044 | stw r10,PACA_EXMC+EX_DSISR(r13) | |
d064151f | 1045 | EXCEPTION_COMMON(PACA_EXMC, 0x200) |
afcf0095 NP |
1046 | FINISH_NAP |
1047 | RECONCILE_IRQ_STATE(r10, r11) | |
1048 | ld r3,PACA_EXMC+EX_DAR(r13) | |
1049 | lwz r4,PACA_EXMC+EX_DSISR(r13) | |
1050 | /* Enable MSR_RI when finished with PACA_EXMC */ | |
1051 | li r10,MSR_RI | |
1052 | mtmsrd r10,1 | |
1053 | std r3,_DAR(r1) | |
1054 | std r4,_DSISR(r1) | |
1055 | bl save_nvgprs | |
1056 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1057 | bl machine_check_exception | |
1058 | b ret_from_except | |
1059 | ||
1060 | #define MACHINE_CHECK_HANDLER_WINDUP \ | |
1061 | /* Clear MSR_RI before setting SRR0 and SRR1. */\ | |
1062 | li r0,MSR_RI; \ | |
1063 | mfmsr r9; /* get MSR value */ \ | |
1064 | andc r9,r9,r0; \ | |
1065 | mtmsrd r9,1; /* Clear MSR_RI */ \ | |
1066 | /* Move original SRR0 and SRR1 into the respective regs */ \ | |
1067 | ld r9,_MSR(r1); \ | |
1068 | mtspr SPRN_SRR1,r9; \ | |
1069 | ld r3,_NIP(r1); \ | |
1070 | mtspr SPRN_SRR0,r3; \ | |
1071 | ld r9,_CTR(r1); \ | |
1072 | mtctr r9; \ | |
1073 | ld r9,_XER(r1); \ | |
1074 | mtxer r9; \ | |
1075 | ld r9,_LINK(r1); \ | |
1076 | mtlr r9; \ | |
1077 | REST_GPR(0, r1); \ | |
1078 | REST_8GPRS(2, r1); \ | |
1079 | REST_GPR(10, r1); \ | |
1080 | ld r11,_CCR(r1); \ | |
1081 | mtcr r11; \ | |
1082 | /* Decrement paca->in_mce. */ \ | |
1083 | lhz r12,PACA_IN_MCE(r13); \ | |
1084 | subi r12,r12,1; \ | |
1085 | sth r12,PACA_IN_MCE(r13); \ | |
1086 | REST_GPR(11, r1); \ | |
1087 | REST_2GPRS(12, r1); \ | |
1088 | /* restore original r1. */ \ | |
1089 | ld r1,GPR1(r1) | |
1090 | ||
1945bc45 NP |
1091 | #ifdef CONFIG_PPC_P7_NAP |
1092 | /* | |
1093 | * This is an idle wakeup. Low level machine check has already been | |
1094 | * done. Queue the event then call the idle code to do the wake up. | |
1095 | */ | |
1096 | EXC_COMMON_BEGIN(machine_check_idle_common) | |
1097 | bl machine_check_queue_event | |
1098 | ||
1099 | /* | |
1100 | * We have not used any non-volatile GPRs here, and as a rule | |
1101 | * most exception code including machine check does not. | |
1102 | * Therefore PACA_NAPSTATELOST does not need to be set. Idle | |
1103 | * wakeup will restore volatile registers. | |
1104 | * | |
1105 | * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce. | |
1106 | * | |
1107 | * Then decrement MCE nesting after finishing with the stack. | |
1108 | */ | |
1109 | ld r3,_MSR(r1) | |
10d91611 | 1110 | ld r4,_LINK(r1) |
1945bc45 NP |
1111 | |
1112 | lhz r11,PACA_IN_MCE(r13) | |
1113 | subi r11,r11,1 | |
1114 | sth r11,PACA_IN_MCE(r13) | |
1115 | ||
10d91611 NP |
1116 | mtlr r4 |
1117 | rlwinm r10,r3,47-31,30,31 | |
1118 | cmpwi cr1,r10,2 | |
1119 | bltlr cr1 /* no state loss, return to idle caller */ | |
1120 | b idle_return_gpr_loss | |
1945bc45 | 1121 | #endif |
afcf0095 NP |
1122 | /* |
1123 | * Handle machine check early in real mode. We come here with | |
1124 | * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. | |
1125 | */ | |
1126 | EXC_COMMON_BEGIN(machine_check_handle_early) | |
1127 | std r0,GPR0(r1) /* Save r0 */ | |
1128 | EXCEPTION_PROLOG_COMMON_3(0x200) | |
1129 | bl save_nvgprs | |
1130 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1131 | bl machine_check_early | |
1132 | std r3,RESULT(r1) /* Save result */ | |
1133 | ld r12,_MSR(r1) | |
db7d31ac MS |
1134 | BEGIN_FTR_SECTION |
1135 | b 4f | |
1136 | END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE) | |
1945bc45 | 1137 | |
afcf0095 NP |
1138 | #ifdef CONFIG_PPC_P7_NAP |
1139 | /* | |
1140 | * Check if thread was in power saving mode. We come here when any | |
1141 | * of the following is true: | |
1142 | * a. thread wasn't in power saving mode | |
1143 | * b. thread was in power saving mode with no state loss, | |
1144 | * supervisor state loss or hypervisor state loss. | |
1145 | * | |
1146 | * Go back to nap/sleep/winkle mode again if (b) is true. | |
1147 | */ | |
bf66e3c4 | 1148 | BEGIN_FTR_SECTION |
1945bc45 | 1149 | rlwinm. r11,r12,47-31,30,31 |
6102c005 | 1150 | bne machine_check_idle_common |
bf66e3c4 | 1151 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
afcf0095 | 1152 | #endif |
1945bc45 | 1153 | |
afcf0095 NP |
1154 | /* |
1155 | * Check if we are coming from hypervisor userspace. If yes then we | |
1156 | * continue in host kernel in V mode to deliver the MC event. | |
1157 | */ | |
1158 | rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ | |
1159 | beq 5f | |
db7d31ac | 1160 | 4: andi. r11,r12,MSR_PR /* See if coming from user. */ |
afcf0095 NP |
1161 | bne 9f /* continue in V mode if we are. */ |
1162 | ||
1163 | 5: | |
1164 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER | |
db7d31ac | 1165 | BEGIN_FTR_SECTION |
afcf0095 NP |
1166 | /* |
1167 | * We are coming from kernel context. Check if we are coming from | |
1168 | * guest. if yes, then we can continue. We will fall through | |
1169 | * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. | |
1170 | */ | |
1171 | lbz r11,HSTATE_IN_GUEST(r13) | |
1172 | cmpwi r11,0 /* Check if coming from guest */ | |
1173 | bne 9f /* continue if we are. */ | |
db7d31ac | 1174 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) |
afcf0095 NP |
1175 | #endif |
1176 | /* | |
1177 | * At this point we are not sure about what context we come from. | |
1178 | * Queue up the MCE event and return from the interrupt. | |
1179 | * But before that, check if this is an un-recoverable exception. | |
1180 | * If yes, then stay on emergency stack and panic. | |
1181 | */ | |
1182 | andi. r11,r12,MSR_RI | |
1183 | bne 2f | |
1184 | 1: mfspr r11,SPRN_SRR0 | |
1185 | LOAD_HANDLER(r10,unrecover_mce) | |
1186 | mtspr SPRN_SRR0,r10 | |
1187 | ld r10,PACAKMSR(r13) | |
1188 | /* | |
1189 | * We are going down. But there are chances that we might get hit by | |
1190 | * another MCE during panic path and we may run into unstable state | |
1191 | * with no way out. Hence, turn ME bit off while going down, so that | |
1192 | * when another MCE is hit during panic path, system will checkstop | |
1193 | * and hypervisor will get restarted cleanly by SP. | |
1194 | */ | |
1195 | li r3,MSR_ME | |
1196 | andc r10,r10,r3 /* Turn off MSR_ME */ | |
1197 | mtspr SPRN_SRR1,r10 | |
222f20f1 | 1198 | RFI_TO_KERNEL |
afcf0095 NP |
1199 | b . |
1200 | 2: | |
1201 | /* | |
1202 | * Check if we have successfully handled/recovered from error, if not | |
1203 | * then stay on emergency stack and panic. | |
1204 | */ | |
1205 | ld r3,RESULT(r1) /* Load result */ | |
1206 | cmpdi r3,0 /* see if we handled MCE successfully */ | |
1207 | ||
1208 | beq 1b /* if !handled then panic */ | |
db7d31ac | 1209 | BEGIN_FTR_SECTION |
afcf0095 NP |
1210 | /* |
1211 | * Return from MC interrupt. | |
1212 | * Queue up the MCE event so that we can log it later, while | |
1213 | * returning from kernel or opal call. | |
1214 | */ | |
1215 | bl machine_check_queue_event | |
1216 | MACHINE_CHECK_HANDLER_WINDUP | |
222f20f1 | 1217 | RFI_TO_USER_OR_KERNEL |
db7d31ac MS |
1218 | FTR_SECTION_ELSE |
1219 | /* | |
1220 | * pSeries: Return from MC interrupt. Before that stay on emergency | |
1221 | * stack and call machine_check_exception to log the MCE event. | |
1222 | */ | |
1223 | LOAD_HANDLER(r10,mce_return) | |
1224 | mtspr SPRN_SRR0,r10 | |
1225 | ld r10,PACAKMSR(r13) | |
1226 | mtspr SPRN_SRR1,r10 | |
1227 | RFI_TO_KERNEL | |
1228 | b . | |
1229 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) | |
afcf0095 NP |
1230 | 9: |
1231 | /* Deliver the machine check to host kernel in V mode. */ | |
1232 | MACHINE_CHECK_HANDLER_WINDUP | |
db7d31ac | 1233 | SET_SCRATCH0(r13) /* save r13 */ |
5dba1d50 | 1234 | EXCEPTION_PROLOG_0 PACA_EXMC |
db7d31ac | 1235 | b machine_check_pSeries_0 |
afcf0095 NP |
1236 | |
1237 | EXC_COMMON_BEGIN(unrecover_mce) | |
1238 | /* Invoke machine_check_exception to print MCE event and panic. */ | |
1239 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1240 | bl machine_check_exception | |
1241 | /* | |
1242 | * We will not reach here. Even if we did, there is no way out. Call | |
1243 | * unrecoverable_exception and die. | |
1244 | */ | |
1245 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
1246 | bl unrecoverable_exception | |
1247 | b 1b | |
1248 | ||
a43c1590 MS |
1249 | EXC_COMMON_BEGIN(mce_return) |
1250 | /* Invoke machine_check_exception to print MCE event and return. */ | |
1251 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1252 | bl machine_check_exception | |
db7d31ac | 1253 | MACHINE_CHECK_HANDLER_WINDUP |
a43c1590 MS |
1254 | RFI_TO_KERNEL |
1255 | b . | |
0ebc4cda | 1256 | |
e779fc93 | 1257 | EXC_REAL_BEGIN(data_access, 0x300, 0x80) |
bf66e3c4 NP |
1258 | SET_SCRATCH0(r13) /* save r13 */ |
1259 | EXCEPTION_PROLOG_0 PACA_EXGEN | |
e779fc93 NP |
1260 | b tramp_real_data_access |
1261 | EXC_REAL_END(data_access, 0x300, 0x80) | |
1262 | ||
1263 | TRAMP_REAL_BEGIN(tramp_real_data_access) | |
bf66e3c4 | 1264 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x300, 0 |
38555434 NP |
1265 | /* |
1266 | * DAR/DSISR must be read before setting MSR[RI], because | |
1267 | * a d-side MCE will clobber those registers so is not | |
1268 | * recoverable if they are live. | |
1269 | */ | |
1270 | mfspr r10,SPRN_DAR | |
1271 | mfspr r11,SPRN_DSISR | |
1272 | std r10,PACA_EXGEN+EX_DAR(r13) | |
1273 | stw r11,PACA_EXGEN+EX_DSISR(r13) | |
2d046308 | 1274 | EXCEPTION_PROLOG_2_REAL data_access_common, EXC_STD, 1 |
e779fc93 NP |
1275 | |
1276 | EXC_VIRT_BEGIN(data_access, 0x4300, 0x80) | |
bf66e3c4 NP |
1277 | SET_SCRATCH0(r13) /* save r13 */ |
1278 | EXCEPTION_PROLOG_0 PACA_EXGEN | |
1279 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x300, 0 | |
38555434 NP |
1280 | mfspr r10,SPRN_DAR |
1281 | mfspr r11,SPRN_DSISR | |
1282 | std r10,PACA_EXGEN+EX_DAR(r13) | |
1283 | stw r11,PACA_EXGEN+EX_DSISR(r13) | |
2d046308 | 1284 | EXCEPTION_PROLOG_2_VIRT data_access_common, EXC_STD |
e779fc93 NP |
1285 | EXC_VIRT_END(data_access, 0x4300, 0x80) |
1286 | ||
80795e6c NP |
1287 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x300) |
1288 | ||
1289 | EXC_COMMON_BEGIN(data_access_common) | |
1290 | /* | |
1291 | * Here r13 points to the paca, r9 contains the saved CR, | |
1292 | * SRR0 and SRR1 are saved in r11 and r12, | |
1293 | * r9 - r13 are saved in paca->exgen. | |
38555434 | 1294 | * EX_DAR and EX_DSISR have saved DAR/DSISR |
80795e6c | 1295 | */ |
d064151f | 1296 | EXCEPTION_COMMON(PACA_EXGEN, 0x300) |
80795e6c NP |
1297 | RECONCILE_IRQ_STATE(r10, r11) |
1298 | ld r12,_MSR(r1) | |
1299 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
1300 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
1301 | li r5,0x300 | |
1302 | std r3,_DAR(r1) | |
1303 | std r4,_DSISR(r1) | |
1304 | BEGIN_MMU_FTR_SECTION | |
1305 | b do_hash_page /* Try to handle as hpte fault */ | |
1306 | MMU_FTR_SECTION_ELSE | |
1307 | b handle_page_fault | |
1308 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
1309 | ||
0ebc4cda | 1310 | |
1a6822d1 | 1311 | EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80) |
bf66e3c4 NP |
1312 | SET_SCRATCH0(r13) /* save r13 */ |
1313 | EXCEPTION_PROLOG_0 PACA_EXSLB | |
e779fc93 | 1314 | b tramp_real_data_access_slb |
1a6822d1 | 1315 | EXC_REAL_END(data_access_slb, 0x380, 0x80) |
0ebc4cda | 1316 | |
e779fc93 | 1317 | TRAMP_REAL_BEGIN(tramp_real_data_access_slb) |
bf66e3c4 | 1318 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 1, 0x380, 0 |
38555434 NP |
1319 | mfspr r10,SPRN_DAR |
1320 | std r10,PACA_EXSLB+EX_DAR(r13) | |
bf66e3c4 | 1321 | EXCEPTION_PROLOG_2_REAL data_access_slb_common, EXC_STD, 1 |
e779fc93 | 1322 | |
1a6822d1 | 1323 | EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80) |
bf66e3c4 NP |
1324 | SET_SCRATCH0(r13) /* save r13 */ |
1325 | EXCEPTION_PROLOG_0 PACA_EXSLB | |
1326 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 0, 0x380, 0 | |
38555434 NP |
1327 | mfspr r10,SPRN_DAR |
1328 | std r10,PACA_EXSLB+EX_DAR(r13) | |
bf66e3c4 | 1329 | EXCEPTION_PROLOG_2_VIRT data_access_slb_common, EXC_STD |
1a6822d1 | 1330 | EXC_VIRT_END(data_access_slb, 0x4380, 0x80) |
48e7b769 | 1331 | |
2b9af6e4 NP |
1332 | TRAMP_KVM_SKIP(PACA_EXSLB, 0x380) |
1333 | ||
48e7b769 | 1334 | EXC_COMMON_BEGIN(data_access_slb_common) |
d064151f | 1335 | EXCEPTION_COMMON(PACA_EXSLB, 0x380) |
48e7b769 NP |
1336 | ld r4,PACA_EXSLB+EX_DAR(r13) |
1337 | std r4,_DAR(r1) | |
1338 | addi r3,r1,STACK_FRAME_OVERHEAD | |
7100e870 NP |
1339 | BEGIN_MMU_FTR_SECTION |
1340 | /* HPT case, do SLB fault */ | |
48e7b769 NP |
1341 | bl do_slb_fault |
1342 | cmpdi r3,0 | |
1343 | bne- 1f | |
1344 | b fast_exception_return | |
1345 | 1: /* Error case */ | |
7100e870 NP |
1346 | MMU_FTR_SECTION_ELSE |
1347 | /* Radix case, access is outside page table range */ | |
1348 | li r3,-EFAULT | |
1349 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
48e7b769 NP |
1350 | std r3,RESULT(r1) |
1351 | bl save_nvgprs | |
1352 | RECONCILE_IRQ_STATE(r10, r11) | |
1353 | ld r4,_DAR(r1) | |
1354 | ld r5,RESULT(r1) | |
1355 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1356 | bl do_bad_slb_fault | |
1357 | b ret_from_except | |
1358 | ||
2b9af6e4 | 1359 | |
1a6822d1 NP |
1360 | EXC_REAL(instruction_access, 0x400, 0x80) |
1361 | EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400) | |
27ce77df NP |
1362 | TRAMP_KVM(PACA_EXGEN, 0x400) |
1363 | ||
1364 | EXC_COMMON_BEGIN(instruction_access_common) | |
d064151f | 1365 | EXCEPTION_COMMON(PACA_EXGEN, 0x400) |
27ce77df NP |
1366 | RECONCILE_IRQ_STATE(r10, r11) |
1367 | ld r12,_MSR(r1) | |
1368 | ld r3,_NIP(r1) | |
475b581f | 1369 | andis. r4,r12,DSISR_SRR1_MATCH_64S@h |
27ce77df NP |
1370 | li r5,0x400 |
1371 | std r3,_DAR(r1) | |
1372 | std r4,_DSISR(r1) | |
1373 | BEGIN_MMU_FTR_SECTION | |
1374 | b do_hash_page /* Try to handle as hpte fault */ | |
1375 | MMU_FTR_SECTION_ELSE | |
1376 | b handle_page_fault | |
1377 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
1378 | ||
0ebc4cda | 1379 | |
fc557537 NP |
1380 | __EXC_REAL(instruction_access_slb, 0x480, 0x80, PACA_EXSLB) |
1381 | __EXC_VIRT(instruction_access_slb, 0x4480, 0x80, 0x480, PACA_EXSLB) | |
48e7b769 | 1382 | TRAMP_KVM(PACA_EXSLB, 0x480) |
54be0b9c | 1383 | |
48e7b769 | 1384 | EXC_COMMON_BEGIN(instruction_access_slb_common) |
d064151f | 1385 | EXCEPTION_COMMON(PACA_EXSLB, 0x480) |
48e7b769 NP |
1386 | ld r4,_NIP(r1) |
1387 | addi r3,r1,STACK_FRAME_OVERHEAD | |
7100e870 NP |
1388 | BEGIN_MMU_FTR_SECTION |
1389 | /* HPT case, do SLB fault */ | |
48e7b769 NP |
1390 | bl do_slb_fault |
1391 | cmpdi r3,0 | |
1392 | bne- 1f | |
1393 | b fast_exception_return | |
1394 | 1: /* Error case */ | |
7100e870 NP |
1395 | MMU_FTR_SECTION_ELSE |
1396 | /* Radix case, access is outside page table range */ | |
1397 | li r3,-EFAULT | |
1398 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
48e7b769 | 1399 | std r3,RESULT(r1) |
8d04631a | 1400 | bl save_nvgprs |
8d04631a | 1401 | RECONCILE_IRQ_STATE(r10, r11) |
48e7b769 NP |
1402 | ld r4,_NIP(r1) |
1403 | ld r5,RESULT(r1) | |
1404 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1405 | bl do_bad_slb_fault | |
8d04631a NP |
1406 | b ret_from_except |
1407 | ||
48e7b769 | 1408 | |
1a6822d1 | 1409 | EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100) |
80bd9177 NP |
1410 | SET_SCRATCH0(r13) /* save r13 */ |
1411 | EXCEPTION_PROLOG_0 PACA_EXGEN | |
bf66e3c4 NP |
1412 | BEGIN_FTR_SECTION |
1413 | EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0x500, IRQS_DISABLED | |
1414 | EXCEPTION_PROLOG_2_REAL hardware_interrupt_common, EXC_HV, 1 | |
1415 | FTR_SECTION_ELSE | |
1416 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x500, IRQS_DISABLED | |
1417 | EXCEPTION_PROLOG_2_REAL hardware_interrupt_common, EXC_STD, 1 | |
1418 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) | |
1a6822d1 | 1419 | EXC_REAL_END(hardware_interrupt, 0x500, 0x100) |
da2bc464 | 1420 | |
1a6822d1 | 1421 | EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100) |
80bd9177 NP |
1422 | SET_SCRATCH0(r13) /* save r13 */ |
1423 | EXCEPTION_PROLOG_0 PACA_EXGEN | |
bf66e3c4 NP |
1424 | BEGIN_FTR_SECTION |
1425 | EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0x500, IRQS_DISABLED | |
1426 | EXCEPTION_PROLOG_2_VIRT hardware_interrupt_common, EXC_HV | |
1427 | FTR_SECTION_ELSE | |
1428 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x500, IRQS_DISABLED | |
1429 | EXCEPTION_PROLOG_2_VIRT hardware_interrupt_common, EXC_STD | |
1430 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) | |
1a6822d1 | 1431 | EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100) |
c138e588 | 1432 | |
7ede5317 NP |
1433 | TRAMP_KVM(PACA_EXGEN, 0x500) |
1434 | TRAMP_KVM_HV(PACA_EXGEN, 0x500) | |
c138e588 NP |
1435 | EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) |
1436 | ||
1437 | ||
e779fc93 | 1438 | EXC_REAL_BEGIN(alignment, 0x600, 0x100) |
bf66e3c4 NP |
1439 | SET_SCRATCH0(r13) /* save r13 */ |
1440 | EXCEPTION_PROLOG_0 PACA_EXGEN | |
1441 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x600, 0 | |
38555434 NP |
1442 | mfspr r10,SPRN_DAR |
1443 | mfspr r11,SPRN_DSISR | |
1444 | std r10,PACA_EXGEN+EX_DAR(r13) | |
1445 | stw r11,PACA_EXGEN+EX_DSISR(r13) | |
bf66e3c4 | 1446 | EXCEPTION_PROLOG_2_REAL alignment_common, EXC_STD, 1 |
e779fc93 NP |
1447 | EXC_REAL_END(alignment, 0x600, 0x100) |
1448 | ||
1449 | EXC_VIRT_BEGIN(alignment, 0x4600, 0x100) | |
bf66e3c4 NP |
1450 | SET_SCRATCH0(r13) /* save r13 */ |
1451 | EXCEPTION_PROLOG_0 PACA_EXGEN | |
1452 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x600, 0 | |
38555434 NP |
1453 | mfspr r10,SPRN_DAR |
1454 | mfspr r11,SPRN_DSISR | |
1455 | std r10,PACA_EXGEN+EX_DAR(r13) | |
1456 | stw r11,PACA_EXGEN+EX_DSISR(r13) | |
bf66e3c4 | 1457 | EXCEPTION_PROLOG_2_VIRT alignment_common, EXC_STD |
e779fc93 NP |
1458 | EXC_VIRT_END(alignment, 0x4600, 0x100) |
1459 | ||
da2bc464 | 1460 | TRAMP_KVM(PACA_EXGEN, 0x600) |
f9aa6714 | 1461 | EXC_COMMON_BEGIN(alignment_common) |
d064151f | 1462 | EXCEPTION_COMMON(PACA_EXGEN, 0x600) |
f9aa6714 NP |
1463 | ld r3,PACA_EXGEN+EX_DAR(r13) |
1464 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
1465 | std r3,_DAR(r1) | |
1466 | std r4,_DSISR(r1) | |
1467 | bl save_nvgprs | |
1468 | RECONCILE_IRQ_STATE(r10, r11) | |
1469 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1470 | bl alignment_exception | |
1471 | b ret_from_except | |
1472 | ||
da2bc464 | 1473 | |
1a6822d1 NP |
1474 | EXC_REAL(program_check, 0x700, 0x100) |
1475 | EXC_VIRT(program_check, 0x4700, 0x100, 0x700) | |
da2bc464 | 1476 | TRAMP_KVM(PACA_EXGEN, 0x700) |
11e87346 | 1477 | EXC_COMMON_BEGIN(program_check_common) |
265e60a1 CB |
1478 | /* |
1479 | * It's possible to receive a TM Bad Thing type program check with | |
1480 | * userspace register values (in particular r1), but with SRR1 reporting | |
1481 | * that we came from the kernel. Normally that would confuse the bad | |
1482 | * stack logic, and we would report a bad kernel stack pointer. Instead | |
1483 | * we switch to the emergency stack if we're taking a TM Bad Thing from | |
1484 | * the kernel. | |
1485 | */ | |
1486 | li r10,MSR_PR /* Build a mask of MSR_PR .. */ | |
1487 | oris r10,r10,0x200000@h /* .. and SRR1_PROGTM */ | |
1488 | and r10,r10,r12 /* Mask SRR1 with that. */ | |
1489 | srdi r10,r10,8 /* Shift it so we can compare */ | |
1490 | cmpldi r10,(0x200000 >> 8) /* .. with an immediate. */ | |
1491 | bne 1f /* If != go to normal path. */ | |
1492 | ||
1493 | /* SRR1 had PR=0 and SRR1_PROGTM=1, so use the emergency stack */ | |
1494 | andi. r10,r12,MSR_PR; /* Set CR0 correctly for label */ | |
1495 | /* 3 in EXCEPTION_PROLOG_COMMON */ | |
1496 | mr r10,r1 /* Save r1 */ | |
1497 | ld r1,PACAEMERGSP(r13) /* Use emergency stack */ | |
1498 | subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
1499 | b 3f /* Jump into the macro !! */ | |
d064151f | 1500 | 1: EXCEPTION_COMMON(PACA_EXGEN, 0x700) |
11e87346 NP |
1501 | bl save_nvgprs |
1502 | RECONCILE_IRQ_STATE(r10, r11) | |
1503 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1504 | bl program_check_exception | |
1505 | b ret_from_except | |
1506 | ||
b01c8b54 | 1507 | |
1a6822d1 NP |
1508 | EXC_REAL(fp_unavailable, 0x800, 0x100) |
1509 | EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800) | |
da2bc464 | 1510 | TRAMP_KVM(PACA_EXGEN, 0x800) |
c78d9b97 | 1511 | EXC_COMMON_BEGIN(fp_unavailable_common) |
d064151f | 1512 | EXCEPTION_COMMON(PACA_EXGEN, 0x800) |
c78d9b97 NP |
1513 | bne 1f /* if from user, just load it up */ |
1514 | bl save_nvgprs | |
1515 | RECONCILE_IRQ_STATE(r10, r11) | |
1516 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1517 | bl kernel_fp_unavailable_exception | |
1518 | BUG_OPCODE | |
1519 | 1: | |
1520 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1521 | BEGIN_FTR_SECTION | |
1522 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1523 | * transaction), go do TM stuff | |
1524 | */ | |
1525 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1526 | bne- 2f | |
1527 | END_FTR_SECTION_IFSET(CPU_FTR_TM) | |
1528 | #endif | |
1529 | bl load_up_fpu | |
1530 | b fast_exception_return | |
1531 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1532 | 2: /* User process was in a transaction */ | |
1533 | bl save_nvgprs | |
1534 | RECONCILE_IRQ_STATE(r10, r11) | |
1535 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1536 | bl fp_unavailable_tm | |
1537 | b ret_from_except | |
1538 | #endif | |
1539 | ||
a5d4f3ad | 1540 | |
a048a07d | 1541 | EXC_REAL_OOL_MASKABLE(decrementer, 0x900, 0x80, IRQS_DISABLED) |
f14e953b | 1542 | EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900, IRQS_DISABLED) |
39c0da57 NP |
1543 | TRAMP_KVM(PACA_EXGEN, 0x900) |
1544 | EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) | |
1545 | ||
a485c709 | 1546 | |
1a6822d1 NP |
1547 | EXC_REAL_HV(hdecrementer, 0x980, 0x80) |
1548 | EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980) | |
facc6d74 NP |
1549 | TRAMP_KVM_HV(PACA_EXGEN, 0x980) |
1550 | EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) | |
1551 | ||
a5d4f3ad | 1552 | |
f14e953b MS |
1553 | EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100, IRQS_DISABLED) |
1554 | EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00, IRQS_DISABLED) | |
da2bc464 | 1555 | TRAMP_KVM(PACA_EXGEN, 0xa00) |
ca243163 NP |
1556 | #ifdef CONFIG_PPC_DOORBELL |
1557 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) | |
1558 | #else | |
1559 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) | |
1560 | #endif | |
1561 | ||
0ebc4cda | 1562 | |
1a6822d1 NP |
1563 | EXC_REAL(trap_0b, 0xb00, 0x100) |
1564 | EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00) | |
da2bc464 | 1565 | TRAMP_KVM(PACA_EXGEN, 0xb00) |
341215dc NP |
1566 | EXC_COMMON(trap_0b_common, 0xb00, unknown_exception) |
1567 | ||
acd7d8ce NP |
1568 | /* |
1569 | * system call / hypercall (0xc00, 0x4c00) | |
1570 | * | |
1571 | * The system call exception is invoked with "sc 0" and does not alter HV bit. | |
1572 | * There is support for kernel code to invoke system calls but there are no | |
1573 | * in-tree users. | |
1574 | * | |
1575 | * The hypercall is invoked with "sc 1" and sets HV=1. | |
1576 | * | |
1577 | * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to | |
1578 | * 0x4c00 virtual mode. | |
1579 | * | |
1580 | * Call convention: | |
1581 | * | |
1582 | * syscall register convention is in Documentation/powerpc/syscall64-abi.txt | |
1583 | * | |
1584 | * For hypercalls, the register convention is as follows: | |
1585 | * r0 volatile | |
1586 | * r1-2 nonvolatile | |
1587 | * r3 volatile parameter and return value for status | |
1588 | * r4-r10 volatile input and output value | |
1589 | * r11 volatile hypercall number and output value | |
76fc0cfc | 1590 | * r12 volatile input and output value |
acd7d8ce NP |
1591 | * r13-r31 nonvolatile |
1592 | * LR nonvolatile | |
1593 | * CTR volatile | |
1594 | * XER volatile | |
1595 | * CR0-1 CR5-7 volatile | |
1596 | * CR2-4 nonvolatile | |
1597 | * Other registers nonvolatile | |
1598 | * | |
1599 | * The intersection of volatile registers that don't contain possible | |
76fc0cfc NP |
1600 | * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry |
1601 | * without saving, though xer is not a good idea to use, as hardware may | |
1602 | * interpret some bits so it may be costly to change them. | |
acd7d8ce | 1603 | */ |
1b4d4a79 | 1604 | .macro SYSTEM_CALL virt |
bc355125 | 1605 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
acd7d8ce NP |
1606 | /* |
1607 | * There is a little bit of juggling to get syscall and hcall | |
76fc0cfc NP |
1608 | * working well. Save r13 in ctr to avoid using SPRG scratch |
1609 | * register. | |
acd7d8ce NP |
1610 | * |
1611 | * Userspace syscalls have already saved the PPR, hcalls must save | |
1612 | * it before setting HMT_MEDIUM. | |
1613 | */ | |
1b4d4a79 NP |
1614 | mtctr r13 |
1615 | GET_PACA(r13) | |
1616 | std r10,PACA_EXGEN+EX_R10(r13) | |
1617 | INTERRUPT_TO_KERNEL | |
1618 | KVMTEST EXC_STD 0xc00 /* uses r10, branch to do_kvm_0xc00_system_call */ | |
1619 | HMT_MEDIUM | |
1620 | mfctr r9 | |
bc355125 | 1621 | #else |
1b4d4a79 NP |
1622 | HMT_MEDIUM |
1623 | mr r9,r13 | |
1624 | GET_PACA(r13) | |
1625 | INTERRUPT_TO_KERNEL | |
bc355125 | 1626 | #endif |
d807ad37 | 1627 | |
727f1361 | 1628 | #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH |
1b4d4a79 NP |
1629 | BEGIN_FTR_SECTION |
1630 | cmpdi r0,0x1ebe | |
1631 | beq- 1f | |
1632 | END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) | |
1633 | #endif | |
1634 | /* We reach here with PACA in r13, r13 in r9, and HMT_MEDIUM. */ | |
d807ad37 | 1635 | |
1b4d4a79 NP |
1636 | .if ! \virt |
1637 | mfspr r11,SPRN_SRR0 | |
1638 | mfspr r12,SPRN_SRR1 | |
1639 | __LOAD_HANDLER(r10, system_call_common) | |
1640 | mtspr SPRN_SRR0,r10 | |
1641 | ld r10,PACAKMSR(r13) | |
1642 | mtspr SPRN_SRR1,r10 | |
1643 | RFI_TO_KERNEL | |
1644 | b . /* prevent speculative execution */ | |
1645 | .else | |
1646 | #ifdef CONFIG_RELOCATABLE | |
d807ad37 NP |
1647 | /* |
1648 | * We can't branch directly so we do it via the CTR which | |
1649 | * is volatile across system calls. | |
1650 | */ | |
1b4d4a79 NP |
1651 | __LOAD_HANDLER(r10, system_call_common) |
1652 | mtctr r10 | |
1653 | mfspr r11,SPRN_SRR0 | |
1654 | mfspr r12,SPRN_SRR1 | |
1655 | li r10,MSR_RI | |
1656 | mtmsrd r10,1 | |
1657 | bctr | |
d807ad37 NP |
1658 | #else |
1659 | /* We can branch directly */ | |
1b4d4a79 NP |
1660 | mfspr r11,SPRN_SRR0 |
1661 | mfspr r12,SPRN_SRR1 | |
1662 | li r10,MSR_RI | |
1663 | mtmsrd r10,1 /* Set RI (EE=0) */ | |
1664 | b system_call_common | |
1665 | #endif | |
1666 | .endif | |
1667 | ||
1668 | #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH | |
1669 | /* Fast LE/BE switch system call */ | |
1670 | 1: mfspr r12,SPRN_SRR1 | |
1671 | xori r12,r12,MSR_LE | |
1672 | mtspr SPRN_SRR1,r12 | |
1673 | mr r13,r9 | |
1674 | RFI_TO_USER /* return to userspace */ | |
1675 | b . /* prevent speculative execution */ | |
d807ad37 | 1676 | #endif |
1b4d4a79 | 1677 | .endm |
d807ad37 | 1678 | |
1a6822d1 | 1679 | EXC_REAL_BEGIN(system_call, 0xc00, 0x100) |
1b4d4a79 | 1680 | SYSTEM_CALL 0 |
1a6822d1 | 1681 | EXC_REAL_END(system_call, 0xc00, 0x100) |
da2bc464 | 1682 | |
1a6822d1 | 1683 | EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100) |
1b4d4a79 | 1684 | SYSTEM_CALL 1 |
1a6822d1 | 1685 | EXC_VIRT_END(system_call, 0x4c00, 0x100) |
d807ad37 | 1686 | |
acd7d8ce NP |
1687 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
1688 | /* | |
1689 | * This is a hcall, so register convention is as above, with these | |
1690 | * differences: | |
1691 | * r13 = PACA | |
76fc0cfc NP |
1692 | * ctr = orig r13 |
1693 | * orig r10 saved in PACA | |
acd7d8ce NP |
1694 | */ |
1695 | TRAMP_KVM_BEGIN(do_kvm_0xc00) | |
1696 | /* | |
1697 | * Save the PPR (on systems that support it) before changing to | |
1698 | * HMT_MEDIUM. That allows the KVM code to save that value into the | |
1699 | * guest state (it is the guest's PPR value). | |
1700 | */ | |
76fc0cfc | 1701 | OPT_GET_SPR(r10, SPRN_PPR, CPU_FTR_HAS_PPR) |
acd7d8ce | 1702 | HMT_MEDIUM |
76fc0cfc | 1703 | OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r10, CPU_FTR_HAS_PPR) |
acd7d8ce | 1704 | mfctr r10 |
76fc0cfc | 1705 | SET_SCRATCH0(r10) |
acd7d8ce NP |
1706 | std r9,PACA_EXGEN+EX_R9(r13) |
1707 | mfcr r9 | |
17bdc064 | 1708 | KVM_HANDLER PACA_EXGEN, EXC_STD, 0xc00, 0 |
acd7d8ce | 1709 | #endif |
da2bc464 | 1710 | |
d807ad37 | 1711 | |
1a6822d1 NP |
1712 | EXC_REAL(single_step, 0xd00, 0x100) |
1713 | EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00) | |
da2bc464 | 1714 | TRAMP_KVM(PACA_EXGEN, 0xd00) |
bc6675c6 | 1715 | EXC_COMMON(single_step_common, 0xd00, single_step_exception) |
b01c8b54 | 1716 | |
1a6822d1 | 1717 | EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20) |
da0e7e62 | 1718 | EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00) |
f5c32c1d NP |
1719 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) |
1720 | EXC_COMMON_BEGIN(h_data_storage_common) | |
1721 | mfspr r10,SPRN_HDAR | |
1722 | std r10,PACA_EXGEN+EX_DAR(r13) | |
1723 | mfspr r10,SPRN_HDSISR | |
1724 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
d064151f | 1725 | EXCEPTION_COMMON(PACA_EXGEN, 0xe00) |
f5c32c1d NP |
1726 | bl save_nvgprs |
1727 | RECONCILE_IRQ_STATE(r10, r11) | |
1728 | addi r3,r1,STACK_FRAME_OVERHEAD | |
d7b45615 SJS |
1729 | BEGIN_MMU_FTR_SECTION |
1730 | ld r4,PACA_EXGEN+EX_DAR(r13) | |
1731 | lwz r5,PACA_EXGEN+EX_DSISR(r13) | |
1732 | std r4,_DAR(r1) | |
1733 | std r5,_DSISR(r1) | |
1734 | li r5,SIGSEGV | |
1735 | bl bad_page_fault | |
1736 | MMU_FTR_SECTION_ELSE | |
f5c32c1d | 1737 | bl unknown_exception |
d7b45615 | 1738 | ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX) |
f5c32c1d | 1739 | b ret_from_except |
f5c32c1d | 1740 | |
1707dd16 | 1741 | |
1a6822d1 | 1742 | EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20) |
da0e7e62 | 1743 | EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20) |
82517cab NP |
1744 | TRAMP_KVM_HV(PACA_EXGEN, 0xe20) |
1745 | EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) | |
1746 | ||
1707dd16 | 1747 | |
1a6822d1 NP |
1748 | EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20) |
1749 | EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40) | |
031b4026 NP |
1750 | TRAMP_KVM_HV(PACA_EXGEN, 0xe40) |
1751 | EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) | |
1752 | ||
1707dd16 | 1753 | |
e0319829 NP |
1754 | /* |
1755 | * hmi_exception trampoline is a special case. It jumps to hmi_exception_early | |
1756 | * first, and then eventaully from there to the trampoline to get into virtual | |
1757 | * mode. | |
1758 | */ | |
1a6822d1 | 1759 | __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early) |
f14e953b | 1760 | __TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60, IRQS_DISABLED) |
1a6822d1 | 1761 | EXC_VIRT_NONE(0x4e60, 0x20) |
62f9b03b NP |
1762 | TRAMP_KVM_HV(PACA_EXGEN, 0xe60) |
1763 | TRAMP_REAL_BEGIN(hmi_exception_early) | |
fa4cf6b7 | 1764 | EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0xe60, 0 |
a4087a4d NP |
1765 | mr r10,r1 /* Save r1 */ |
1766 | ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */ | |
62f9b03b | 1767 | subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ |
62f9b03b | 1768 | mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ |
a4087a4d NP |
1769 | mfspr r12,SPRN_HSRR1 /* Save HSRR1 */ |
1770 | EXCEPTION_PROLOG_COMMON_1() | |
890274c2 | 1771 | /* We don't touch AMR here, we never go to virtual mode */ |
62f9b03b NP |
1772 | EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) |
1773 | EXCEPTION_PROLOG_COMMON_3(0xe60) | |
1774 | addi r3,r1,STACK_FRAME_OVERHEAD | |
505a314f | 1775 | BRANCH_LINK_TO_FAR(DOTSYM(hmi_exception_realmode)) /* Function call ABI */ |
5080332c MN |
1776 | cmpdi cr0,r3,0 |
1777 | ||
62f9b03b NP |
1778 | /* Windup the stack. */ |
1779 | /* Move original HSRR0 and HSRR1 into the respective regs */ | |
1780 | ld r9,_MSR(r1) | |
1781 | mtspr SPRN_HSRR1,r9 | |
1782 | ld r3,_NIP(r1) | |
1783 | mtspr SPRN_HSRR0,r3 | |
1784 | ld r9,_CTR(r1) | |
1785 | mtctr r9 | |
1786 | ld r9,_XER(r1) | |
1787 | mtxer r9 | |
1788 | ld r9,_LINK(r1) | |
1789 | mtlr r9 | |
1790 | REST_GPR(0, r1) | |
1791 | REST_8GPRS(2, r1) | |
1792 | REST_GPR(10, r1) | |
1793 | ld r11,_CCR(r1) | |
5080332c MN |
1794 | REST_2GPRS(12, r1) |
1795 | bne 1f | |
62f9b03b NP |
1796 | mtcr r11 |
1797 | REST_GPR(11, r1) | |
5080332c | 1798 | ld r1,GPR1(r1) |
222f20f1 | 1799 | HRFI_TO_USER_OR_KERNEL |
5080332c MN |
1800 | |
1801 | 1: mtcr r11 | |
1802 | REST_GPR(11, r1) | |
62f9b03b NP |
1803 | ld r1,GPR1(r1) |
1804 | ||
1805 | /* | |
1806 | * Go to virtual mode and pull the HMI event information from | |
1807 | * firmware. | |
1808 | */ | |
1809 | .globl hmi_exception_after_realmode | |
1810 | hmi_exception_after_realmode: | |
1811 | SET_SCRATCH0(r13) | |
5dba1d50 | 1812 | EXCEPTION_PROLOG_0 PACA_EXGEN |
62f9b03b NP |
1813 | b tramp_real_hmi_exception |
1814 | ||
5080332c | 1815 | EXC_COMMON_BEGIN(hmi_exception_common) |
47169fba NP |
1816 | EXCEPTION_COMMON(PACA_EXGEN, 0xe60) |
1817 | FINISH_NAP | |
1818 | bl save_nvgprs | |
1819 | RECONCILE_IRQ_STATE(r10, r11) | |
1820 | RUNLATCH_ON | |
c06075f3 NP |
1821 | addi r3,r1,STACK_FRAME_OVERHEAD |
1822 | bl handle_hmi_exception | |
1823 | b ret_from_except | |
1707dd16 | 1824 | |
f14e953b MS |
1825 | EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20, IRQS_DISABLED) |
1826 | EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80, IRQS_DISABLED) | |
9bcb81bf NP |
1827 | TRAMP_KVM_HV(PACA_EXGEN, 0xe80) |
1828 | #ifdef CONFIG_PPC_DOORBELL | |
1829 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) | |
1830 | #else | |
1831 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) | |
1832 | #endif | |
1833 | ||
0ebc4cda | 1834 | |
f14e953b MS |
1835 | EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20, IRQS_DISABLED) |
1836 | EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0, IRQS_DISABLED) | |
74408776 NP |
1837 | TRAMP_KVM_HV(PACA_EXGEN, 0xea0) |
1838 | EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) | |
1839 | ||
9baaef0a | 1840 | |
1a6822d1 NP |
1841 | EXC_REAL_NONE(0xec0, 0x20) |
1842 | EXC_VIRT_NONE(0x4ec0, 0x20) | |
1843 | EXC_REAL_NONE(0xee0, 0x20) | |
1844 | EXC_VIRT_NONE(0x4ee0, 0x20) | |
bda7fea2 | 1845 | |
0ebc4cda | 1846 | |
f442d004 MS |
1847 | EXC_REAL_OOL_MASKABLE(performance_monitor, 0xf00, 0x20, IRQS_PMI_DISABLED) |
1848 | EXC_VIRT_OOL_MASKABLE(performance_monitor, 0x4f00, 0x20, 0xf00, IRQS_PMI_DISABLED) | |
b1c7f150 NP |
1849 | TRAMP_KVM(PACA_EXGEN, 0xf00) |
1850 | EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) | |
1851 | ||
0ebc4cda | 1852 | |
1a6822d1 NP |
1853 | EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20) |
1854 | EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20) | |
d1a0ca9c NP |
1855 | TRAMP_KVM(PACA_EXGEN, 0xf20) |
1856 | EXC_COMMON_BEGIN(altivec_unavailable_common) | |
d064151f | 1857 | EXCEPTION_COMMON(PACA_EXGEN, 0xf20) |
d1a0ca9c NP |
1858 | #ifdef CONFIG_ALTIVEC |
1859 | BEGIN_FTR_SECTION | |
1860 | beq 1f | |
1861 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1862 | BEGIN_FTR_SECTION_NESTED(69) | |
1863 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1864 | * transaction), go do TM stuff | |
1865 | */ | |
1866 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1867 | bne- 2f | |
1868 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1869 | #endif | |
1870 | bl load_up_altivec | |
1871 | b fast_exception_return | |
1872 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1873 | 2: /* User process was in a transaction */ | |
1874 | bl save_nvgprs | |
1875 | RECONCILE_IRQ_STATE(r10, r11) | |
1876 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1877 | bl altivec_unavailable_tm | |
1878 | b ret_from_except | |
1879 | #endif | |
1880 | 1: | |
1881 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1882 | #endif | |
1883 | bl save_nvgprs | |
1884 | RECONCILE_IRQ_STATE(r10, r11) | |
1885 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1886 | bl altivec_unavailable_exception | |
1887 | b ret_from_except | |
1888 | ||
0ebc4cda | 1889 | |
1a6822d1 NP |
1890 | EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20) |
1891 | EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40) | |
792cbddd NP |
1892 | TRAMP_KVM(PACA_EXGEN, 0xf40) |
1893 | EXC_COMMON_BEGIN(vsx_unavailable_common) | |
d064151f | 1894 | EXCEPTION_COMMON(PACA_EXGEN, 0xf40) |
792cbddd NP |
1895 | #ifdef CONFIG_VSX |
1896 | BEGIN_FTR_SECTION | |
1897 | beq 1f | |
1898 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1899 | BEGIN_FTR_SECTION_NESTED(69) | |
1900 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1901 | * transaction), go do TM stuff | |
1902 | */ | |
1903 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1904 | bne- 2f | |
1905 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1906 | #endif | |
1907 | b load_up_vsx | |
1908 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1909 | 2: /* User process was in a transaction */ | |
1910 | bl save_nvgprs | |
1911 | RECONCILE_IRQ_STATE(r10, r11) | |
1912 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1913 | bl vsx_unavailable_tm | |
1914 | b ret_from_except | |
1915 | #endif | |
1916 | 1: | |
1917 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
1918 | #endif | |
1919 | bl save_nvgprs | |
1920 | RECONCILE_IRQ_STATE(r10, r11) | |
1921 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1922 | bl vsx_unavailable_exception | |
1923 | b ret_from_except | |
1924 | ||
da2bc464 | 1925 | |
1a6822d1 NP |
1926 | EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20) |
1927 | EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60) | |
1134713c NP |
1928 | TRAMP_KVM(PACA_EXGEN, 0xf60) |
1929 | EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) | |
1930 | ||
da2bc464 | 1931 | |
1a6822d1 NP |
1932 | EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20) |
1933 | EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80) | |
14b0072c NP |
1934 | TRAMP_KVM_HV(PACA_EXGEN, 0xf80) |
1935 | EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) | |
1936 | ||
da2bc464 | 1937 | |
1a6822d1 NP |
1938 | EXC_REAL_NONE(0xfa0, 0x20) |
1939 | EXC_VIRT_NONE(0x4fa0, 0x20) | |
1940 | EXC_REAL_NONE(0xfc0, 0x20) | |
1941 | EXC_VIRT_NONE(0x4fc0, 0x20) | |
1942 | EXC_REAL_NONE(0xfe0, 0x20) | |
1943 | EXC_VIRT_NONE(0x4fe0, 0x20) | |
1944 | ||
1945 | EXC_REAL_NONE(0x1000, 0x100) | |
1946 | EXC_VIRT_NONE(0x5000, 0x100) | |
1947 | EXC_REAL_NONE(0x1100, 0x100) | |
1948 | EXC_VIRT_NONE(0x5100, 0x100) | |
d0c0c9a1 | 1949 | |
0ebc4cda | 1950 | #ifdef CONFIG_CBE_RAS |
1a6822d1 NP |
1951 | EXC_REAL_HV(cbe_system_error, 0x1200, 0x100) |
1952 | EXC_VIRT_NONE(0x5200, 0x100) | |
da2bc464 | 1953 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) |
ff1b3206 | 1954 | EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) |
da2bc464 | 1955 | #else /* CONFIG_CBE_RAS */ |
1a6822d1 NP |
1956 | EXC_REAL_NONE(0x1200, 0x100) |
1957 | EXC_VIRT_NONE(0x5200, 0x100) | |
da2bc464 | 1958 | #endif |
b01c8b54 | 1959 | |
ff1b3206 | 1960 | |
1a6822d1 NP |
1961 | EXC_REAL(instruction_breakpoint, 0x1300, 0x100) |
1962 | EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300) | |
da2bc464 | 1963 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) |
4e96dbbf NP |
1964 | EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) |
1965 | ||
1a6822d1 NP |
1966 | EXC_REAL_NONE(0x1400, 0x100) |
1967 | EXC_VIRT_NONE(0x5400, 0x100) | |
da2bc464 | 1968 | |
1a6822d1 | 1969 | EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100) |
b92a66a6 | 1970 | mtspr SPRN_SPRG_HSCRATCH0,r13 |
5dba1d50 | 1971 | EXCEPTION_PROLOG_0 PACA_EXGEN |
fa4cf6b7 | 1972 | EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 0, 0x1500, 0 |
b92a66a6 MN |
1973 | |
1974 | #ifdef CONFIG_PPC_DENORMALISATION | |
1975 | mfspr r10,SPRN_HSRR1 | |
afcf0095 | 1976 | andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ |
afcf0095 NP |
1977 | bne+ denorm_assist |
1978 | #endif | |
1e9b4507 | 1979 | |
a7c1ca19 | 1980 | KVMTEST EXC_HV 0x1500 |
2d046308 | 1981 | EXCEPTION_PROLOG_2_REAL denorm_common, EXC_HV, 1 |
1a6822d1 | 1982 | EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100) |
a74599a5 | 1983 | |
d7e89849 | 1984 | #ifdef CONFIG_PPC_DENORMALISATION |
1a6822d1 | 1985 | EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100) |
d7e89849 | 1986 | b exc_real_0x1500_denorm_exception_hv |
1a6822d1 | 1987 | EXC_VIRT_END(denorm_exception, 0x5500, 0x100) |
d7e89849 | 1988 | #else |
1a6822d1 | 1989 | EXC_VIRT_NONE(0x5500, 0x100) |
afcf0095 NP |
1990 | #endif |
1991 | ||
4bb3c7a0 | 1992 | TRAMP_KVM_HV(PACA_EXGEN, 0x1500) |
b01c8b54 | 1993 | |
b92a66a6 | 1994 | #ifdef CONFIG_PPC_DENORMALISATION |
da2bc464 | 1995 | TRAMP_REAL_BEGIN(denorm_assist) |
b92a66a6 MN |
1996 | BEGIN_FTR_SECTION |
1997 | /* | |
1998 | * To denormalise we need to move a copy of the register to itself. | |
1999 | * For POWER6 do that here for all FP regs. | |
2000 | */ | |
2001 | mfmsr r10 | |
2002 | ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) | |
2003 | xori r10,r10,(MSR_FE0|MSR_FE1) | |
2004 | mtmsrd r10 | |
2005 | sync | |
d7c67fb1 | 2006 | |
f3c8b6c6 NP |
2007 | .Lreg=0 |
2008 | .rept 32 | |
2009 | fmr .Lreg,.Lreg | |
2010 | .Lreg=.Lreg+1 | |
2011 | .endr | |
d7c67fb1 | 2012 | |
b92a66a6 MN |
2013 | FTR_SECTION_ELSE |
2014 | /* | |
2015 | * To denormalise we need to move a copy of the register to itself. | |
2016 | * For POWER7 do that here for the first 32 VSX registers only. | |
2017 | */ | |
2018 | mfmsr r10 | |
2019 | oris r10,r10,MSR_VSX@h | |
2020 | mtmsrd r10 | |
2021 | sync | |
d7c67fb1 | 2022 | |
f3c8b6c6 NP |
2023 | .Lreg=0 |
2024 | .rept 32 | |
2025 | XVCPSGNDP(.Lreg,.Lreg,.Lreg) | |
2026 | .Lreg=.Lreg+1 | |
2027 | .endr | |
d7c67fb1 | 2028 | |
b92a66a6 | 2029 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) |
fb0fce3e MN |
2030 | |
2031 | BEGIN_FTR_SECTION | |
2032 | b denorm_done | |
2033 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
2034 | /* | |
2035 | * To denormalise we need to move a copy of the register to itself. | |
2036 | * For POWER8 we need to do that for all 64 VSX registers | |
2037 | */ | |
f3c8b6c6 NP |
2038 | .Lreg=32 |
2039 | .rept 32 | |
2040 | XVCPSGNDP(.Lreg,.Lreg,.Lreg) | |
2041 | .Lreg=.Lreg+1 | |
2042 | .endr | |
2043 | ||
fb0fce3e | 2044 | denorm_done: |
f14040bc MN |
2045 | mfspr r11,SPRN_HSRR0 |
2046 | subi r11,r11,4 | |
b92a66a6 MN |
2047 | mtspr SPRN_HSRR0,r11 |
2048 | mtcrf 0x80,r9 | |
2049 | ld r9,PACA_EXGEN+EX_R9(r13) | |
44e9309f | 2050 | RESTORE_PPR_PACA(PACA_EXGEN, r10) |
630573c1 PM |
2051 | BEGIN_FTR_SECTION |
2052 | ld r10,PACA_EXGEN+EX_CFAR(r13) | |
2053 | mtspr SPRN_CFAR,r10 | |
2054 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
b92a66a6 MN |
2055 | ld r10,PACA_EXGEN+EX_R10(r13) |
2056 | ld r11,PACA_EXGEN+EX_R11(r13) | |
2057 | ld r12,PACA_EXGEN+EX_R12(r13) | |
2058 | ld r13,PACA_EXGEN+EX_R13(r13) | |
222f20f1 | 2059 | HRFI_TO_UNKNOWN |
b92a66a6 MN |
2060 | b . |
2061 | #endif | |
2062 | ||
872e2ae4 | 2063 | EXC_COMMON(denorm_common, 0x1500, unknown_exception) |
d7e89849 NP |
2064 | |
2065 | ||
2066 | #ifdef CONFIG_CBE_RAS | |
1a6822d1 NP |
2067 | EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100) |
2068 | EXC_VIRT_NONE(0x5600, 0x100) | |
d7e89849 | 2069 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) |
69a79344 | 2070 | EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) |
d7e89849 | 2071 | #else /* CONFIG_CBE_RAS */ |
1a6822d1 NP |
2072 | EXC_REAL_NONE(0x1600, 0x100) |
2073 | EXC_VIRT_NONE(0x5600, 0x100) | |
d7e89849 NP |
2074 | #endif |
2075 | ||
69a79344 | 2076 | |
1a6822d1 NP |
2077 | EXC_REAL(altivec_assist, 0x1700, 0x100) |
2078 | EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700) | |
d7e89849 | 2079 | TRAMP_KVM(PACA_EXGEN, 0x1700) |
b51c079e NP |
2080 | #ifdef CONFIG_ALTIVEC |
2081 | EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) | |
2082 | #else | |
2083 | EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) | |
2084 | #endif | |
2085 | ||
d7e89849 NP |
2086 | |
2087 | #ifdef CONFIG_CBE_RAS | |
1a6822d1 NP |
2088 | EXC_REAL_HV(cbe_thermal, 0x1800, 0x100) |
2089 | EXC_VIRT_NONE(0x5800, 0x100) | |
d7e89849 | 2090 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) |
3965f8ab | 2091 | EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) |
d7e89849 | 2092 | #else /* CONFIG_CBE_RAS */ |
1a6822d1 NP |
2093 | EXC_REAL_NONE(0x1800, 0x100) |
2094 | EXC_VIRT_NONE(0x5800, 0x100) | |
d7e89849 NP |
2095 | #endif |
2096 | ||
75eb767e | 2097 | #ifdef CONFIG_PPC_WATCHDOG |
2104180a NP |
2098 | |
2099 | #define MASKED_DEC_HANDLER_LABEL 3f | |
2100 | ||
2101 | #define MASKED_DEC_HANDLER(_H) \ | |
2102 | 3: /* soft-nmi */ \ | |
2103 | std r12,PACA_EXGEN+EX_R12(r13); \ | |
2104 | GET_SCRATCH0(r10); \ | |
2105 | std r10,PACA_EXGEN+EX_R13(r13); \ | |
2d046308 | 2106 | EXCEPTION_PROLOG_2_REAL soft_nmi_common, _H, 1 |
2104180a | 2107 | |
cc491f1d NP |
2108 | /* |
2109 | * Branch to soft_nmi_interrupt using the emergency stack. The emergency | |
2110 | * stack is one that is usable by maskable interrupts so long as MSR_EE | |
2111 | * remains off. It is used for recovery when something has corrupted the | |
2112 | * normal kernel stack, for example. The "soft NMI" must not use the process | |
2113 | * stack because we want irq disabled sections to avoid touching the stack | |
2114 | * at all (other than PMU interrupts), so use the emergency stack for this, | |
2115 | * and run it entirely with interrupts hard disabled. | |
2116 | */ | |
2104180a NP |
2117 | EXC_COMMON_BEGIN(soft_nmi_common) |
2118 | mr r10,r1 | |
2119 | ld r1,PACAEMERGSP(r13) | |
2104180a | 2120 | subi r1,r1,INT_FRAME_SIZE |
47169fba NP |
2121 | EXCEPTION_COMMON_STACK(PACA_EXGEN, 0x900) |
2122 | bl save_nvgprs | |
2123 | RECONCILE_IRQ_STATE(r10, r11) | |
c06075f3 NP |
2124 | addi r3,r1,STACK_FRAME_OVERHEAD |
2125 | bl soft_nmi_interrupt | |
2104180a NP |
2126 | b ret_from_except |
2127 | ||
75eb767e | 2128 | #else /* CONFIG_PPC_WATCHDOG */ |
2104180a NP |
2129 | #define MASKED_DEC_HANDLER_LABEL 2f /* normal return */ |
2130 | #define MASKED_DEC_HANDLER(_H) | |
75eb767e | 2131 | #endif /* CONFIG_PPC_WATCHDOG */ |
d7e89849 | 2132 | |
0ebc4cda | 2133 | /* |
fe9e1d54 IM |
2134 | * An interrupt came in while soft-disabled. We set paca->irq_happened, then: |
2135 | * - If it was a decrementer interrupt, we bump the dec to max and and return. | |
2136 | * - If it was a doorbell we return immediately since doorbells are edge | |
2137 | * triggered and won't automatically refire. | |
0869b6fd MS |
2138 | * - If it was a HMI we return immediately since we handled it in realmode |
2139 | * and it won't refire. | |
6cc3f91b | 2140 | * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return. |
fe9e1d54 | 2141 | * This is called with r10 containing the value to OR to the paca field. |
0ebc4cda | 2142 | */ |
4508a74a NP |
2143 | .macro MASKED_INTERRUPT hsrr |
2144 | .if \hsrr | |
2145 | masked_Hinterrupt: | |
2146 | .else | |
2147 | masked_interrupt: | |
2148 | .endif | |
2149 | std r11,PACA_EXGEN+EX_R11(r13) | |
2150 | lbz r11,PACAIRQHAPPENED(r13) | |
2151 | or r11,r11,r10 | |
2152 | stb r11,PACAIRQHAPPENED(r13) | |
2153 | cmpwi r10,PACA_IRQ_DEC | |
2154 | bne 1f | |
2155 | lis r10,0x7fff | |
2156 | ori r10,r10,0xffff | |
2157 | mtspr SPRN_DEC,r10 | |
2158 | b MASKED_DEC_HANDLER_LABEL | |
2159 | 1: andi. r10,r10,PACA_IRQ_MUST_HARD_MASK | |
2160 | beq 2f | |
2161 | .if \hsrr | |
2162 | mfspr r10,SPRN_HSRR1 | |
2163 | xori r10,r10,MSR_EE /* clear MSR_EE */ | |
2164 | mtspr SPRN_HSRR1,r10 | |
2165 | .else | |
2166 | mfspr r10,SPRN_SRR1 | |
2167 | xori r10,r10,MSR_EE /* clear MSR_EE */ | |
2168 | mtspr SPRN_SRR1,r10 | |
2169 | .endif | |
2170 | ori r11,r11,PACA_IRQ_HARD_DIS | |
2171 | stb r11,PACAIRQHAPPENED(r13) | |
2172 | 2: /* done */ | |
2173 | mtcrf 0x80,r9 | |
2174 | std r1,PACAR1(r13) | |
2175 | ld r9,PACA_EXGEN+EX_R9(r13) | |
2176 | ld r10,PACA_EXGEN+EX_R10(r13) | |
2177 | ld r11,PACA_EXGEN+EX_R11(r13) | |
2178 | /* returns to kernel where r13 must be set up, so don't restore it */ | |
2179 | .if \hsrr | |
2180 | HRFI_TO_KERNEL | |
2181 | .else | |
2182 | RFI_TO_KERNEL | |
2183 | .endif | |
2184 | b . | |
2185 | MASKED_DEC_HANDLER(\hsrr\()) | |
2186 | .endm | |
57f26649 | 2187 | |
a048a07d NP |
2188 | TRAMP_REAL_BEGIN(stf_barrier_fallback) |
2189 | std r9,PACA_EXRFI+EX_R9(r13) | |
2190 | std r10,PACA_EXRFI+EX_R10(r13) | |
2191 | sync | |
2192 | ld r9,PACA_EXRFI+EX_R9(r13) | |
2193 | ld r10,PACA_EXRFI+EX_R10(r13) | |
2194 | ori 31,31,0 | |
2195 | .rept 14 | |
2196 | b 1f | |
2197 | 1: | |
2198 | .endr | |
2199 | blr | |
2200 | ||
aa8a5e00 ME |
2201 | TRAMP_REAL_BEGIN(rfi_flush_fallback) |
2202 | SET_SCRATCH0(r13); | |
2203 | GET_PACA(r13); | |
78ee9946 ME |
2204 | std r1,PACA_EXRFI+EX_R12(r13) |
2205 | ld r1,PACAKSAVE(r13) | |
aa8a5e00 ME |
2206 | std r9,PACA_EXRFI+EX_R9(r13) |
2207 | std r10,PACA_EXRFI+EX_R10(r13) | |
2208 | std r11,PACA_EXRFI+EX_R11(r13) | |
aa8a5e00 ME |
2209 | mfctr r9 |
2210 | ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) | |
bdcb1aef NP |
2211 | ld r11,PACA_L1D_FLUSH_SIZE(r13) |
2212 | srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ | |
aa8a5e00 | 2213 | mtctr r11 |
15a3204d | 2214 | DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ |
aa8a5e00 ME |
2215 | |
2216 | /* order ld/st prior to dcbt stop all streams with flushing */ | |
2217 | sync | |
bdcb1aef NP |
2218 | |
2219 | /* | |
2220 | * The load adresses are at staggered offsets within cachelines, | |
2221 | * which suits some pipelines better (on others it should not | |
2222 | * hurt). | |
2223 | */ | |
2224 | 1: | |
2225 | ld r11,(0x80 + 8)*0(r10) | |
2226 | ld r11,(0x80 + 8)*1(r10) | |
2227 | ld r11,(0x80 + 8)*2(r10) | |
2228 | ld r11,(0x80 + 8)*3(r10) | |
2229 | ld r11,(0x80 + 8)*4(r10) | |
2230 | ld r11,(0x80 + 8)*5(r10) | |
2231 | ld r11,(0x80 + 8)*6(r10) | |
2232 | ld r11,(0x80 + 8)*7(r10) | |
2233 | addi r10,r10,0x80*8 | |
aa8a5e00 ME |
2234 | bdnz 1b |
2235 | ||
2236 | mtctr r9 | |
2237 | ld r9,PACA_EXRFI+EX_R9(r13) | |
2238 | ld r10,PACA_EXRFI+EX_R10(r13) | |
2239 | ld r11,PACA_EXRFI+EX_R11(r13) | |
78ee9946 | 2240 | ld r1,PACA_EXRFI+EX_R12(r13) |
aa8a5e00 ME |
2241 | GET_SCRATCH0(r13); |
2242 | rfid | |
2243 | ||
2244 | TRAMP_REAL_BEGIN(hrfi_flush_fallback) | |
2245 | SET_SCRATCH0(r13); | |
2246 | GET_PACA(r13); | |
78ee9946 ME |
2247 | std r1,PACA_EXRFI+EX_R12(r13) |
2248 | ld r1,PACAKSAVE(r13) | |
aa8a5e00 ME |
2249 | std r9,PACA_EXRFI+EX_R9(r13) |
2250 | std r10,PACA_EXRFI+EX_R10(r13) | |
2251 | std r11,PACA_EXRFI+EX_R11(r13) | |
aa8a5e00 ME |
2252 | mfctr r9 |
2253 | ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) | |
bdcb1aef NP |
2254 | ld r11,PACA_L1D_FLUSH_SIZE(r13) |
2255 | srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ | |
aa8a5e00 | 2256 | mtctr r11 |
15a3204d | 2257 | DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ |
aa8a5e00 ME |
2258 | |
2259 | /* order ld/st prior to dcbt stop all streams with flushing */ | |
2260 | sync | |
bdcb1aef NP |
2261 | |
2262 | /* | |
2263 | * The load adresses are at staggered offsets within cachelines, | |
2264 | * which suits some pipelines better (on others it should not | |
2265 | * hurt). | |
2266 | */ | |
2267 | 1: | |
2268 | ld r11,(0x80 + 8)*0(r10) | |
2269 | ld r11,(0x80 + 8)*1(r10) | |
2270 | ld r11,(0x80 + 8)*2(r10) | |
2271 | ld r11,(0x80 + 8)*3(r10) | |
2272 | ld r11,(0x80 + 8)*4(r10) | |
2273 | ld r11,(0x80 + 8)*5(r10) | |
2274 | ld r11,(0x80 + 8)*6(r10) | |
2275 | ld r11,(0x80 + 8)*7(r10) | |
2276 | addi r10,r10,0x80*8 | |
aa8a5e00 ME |
2277 | bdnz 1b |
2278 | ||
2279 | mtctr r9 | |
2280 | ld r9,PACA_EXRFI+EX_R9(r13) | |
2281 | ld r10,PACA_EXRFI+EX_R10(r13) | |
2282 | ld r11,PACA_EXRFI+EX_R11(r13) | |
78ee9946 | 2283 | ld r1,PACA_EXRFI+EX_R12(r13) |
aa8a5e00 ME |
2284 | GET_SCRATCH0(r13); |
2285 | hrfid | |
2286 | ||
57f26649 NP |
2287 | /* |
2288 | * Real mode exceptions actually use this too, but alternate | |
2289 | * instruction code patches (which end up in the common .text area) | |
2290 | * cannot reach these if they are put there. | |
2291 | */ | |
2292 | USE_FIXED_SECTION(virt_trampolines) | |
4508a74a NP |
2293 | MASKED_INTERRUPT EXC_STD |
2294 | MASKED_INTERRUPT EXC_HV | |
0ebc4cda | 2295 | |
4f6c11db | 2296 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
da2bc464 | 2297 | TRAMP_REAL_BEGIN(kvmppc_skip_interrupt) |
4f6c11db PM |
2298 | /* |
2299 | * Here all GPRs are unchanged from when the interrupt happened | |
2300 | * except for r13, which is saved in SPRG_SCRATCH0. | |
2301 | */ | |
2302 | mfspr r13, SPRN_SRR0 | |
2303 | addi r13, r13, 4 | |
2304 | mtspr SPRN_SRR0, r13 | |
2305 | GET_SCRATCH0(r13) | |
222f20f1 | 2306 | RFI_TO_KERNEL |
4f6c11db PM |
2307 | b . |
2308 | ||
da2bc464 | 2309 | TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) |
4f6c11db PM |
2310 | /* |
2311 | * Here all GPRs are unchanged from when the interrupt happened | |
2312 | * except for r13, which is saved in SPRG_SCRATCH0. | |
2313 | */ | |
2314 | mfspr r13, SPRN_HSRR0 | |
2315 | addi r13, r13, 4 | |
2316 | mtspr SPRN_HSRR0, r13 | |
2317 | GET_SCRATCH0(r13) | |
222f20f1 | 2318 | HRFI_TO_KERNEL |
4f6c11db PM |
2319 | b . |
2320 | #endif | |
2321 | ||
0ebc4cda | 2322 | /* |
057b6d7e HB |
2323 | * Ensure that any handlers that get invoked from the exception prologs |
2324 | * above are below the first 64KB (0x10000) of the kernel image because | |
2325 | * the prologs assemble the addresses of these handlers using the | |
2326 | * LOAD_HANDLER macro, which uses an ori instruction. | |
0ebc4cda BH |
2327 | */ |
2328 | ||
2329 | /*** Common interrupt handlers ***/ | |
2330 | ||
0ebc4cda | 2331 | |
c1fb6816 MN |
2332 | /* |
2333 | * Relocation-on interrupts: A subset of the interrupts can be delivered | |
2334 | * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering | |
2335 | * it. Addresses are the same as the original interrupt addresses, but | |
2336 | * offset by 0xc000000000004000. | |
2337 | * It's impossible to receive interrupts below 0x300 via this mechanism. | |
2338 | * KVM: None of these traps are from the guest ; anything that escalated | |
2339 | * to HV=1 from HV=0 is delivered via real mode handlers. | |
2340 | */ | |
2341 | ||
2342 | /* | |
2343 | * This uses the standard macro, since the original 0x300 vector | |
2344 | * only has extra guff for STAB-based processors -- which never | |
2345 | * come here. | |
2346 | */ | |
da2bc464 | 2347 | |
57f26649 | 2348 | EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) |
b1576fec | 2349 | b __ppc64_runlatch_on |
fe1952fc | 2350 | |
57f26649 | 2351 | USE_FIXED_SECTION(virt_trampolines) |
8ed8ab40 HB |
2352 | /* |
2353 | * The __end_interrupts marker must be past the out-of-line (OOL) | |
2354 | * handlers, so that they are copied to real address 0x100 when running | |
2355 | * a relocatable kernel. This ensures they can be reached from the short | |
2356 | * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch | |
2357 | * directly, without using LOAD_HANDLER(). | |
2358 | */ | |
2359 | .align 7 | |
2360 | .globl __end_interrupts | |
2361 | __end_interrupts: | |
57f26649 | 2362 | DEFINE_FIXED_SYMBOL(__end_interrupts) |
61383407 | 2363 | |
087aa036 | 2364 | #ifdef CONFIG_PPC_970_NAP |
7c8cb4b5 | 2365 | EXC_COMMON_BEGIN(power4_fixup_nap) |
087aa036 CG |
2366 | andc r9,r9,r10 |
2367 | std r9,TI_LOCAL_FLAGS(r11) | |
2368 | ld r10,_LINK(r1) /* make idle task do the */ | |
2369 | std r10,_NIP(r1) /* equivalent of a blr */ | |
2370 | blr | |
2371 | #endif | |
2372 | ||
57f26649 NP |
2373 | CLOSE_FIXED_SECTION(real_vectors); |
2374 | CLOSE_FIXED_SECTION(real_trampolines); | |
2375 | CLOSE_FIXED_SECTION(virt_vectors); | |
2376 | CLOSE_FIXED_SECTION(virt_trampolines); | |
2377 | ||
2378 | USE_TEXT_SECTION() | |
2379 | ||
0ebc4cda BH |
2380 | /* |
2381 | * Hash table stuff | |
2382 | */ | |
f4329f2e | 2383 | .balign IFETCH_ALIGN_BYTES |
6a3bab90 | 2384 | do_hash_page: |
4e003747 | 2385 | #ifdef CONFIG_PPC_BOOK3S_64 |
e6c2a479 | 2386 | lis r0,(DSISR_BAD_FAULT_64S | DSISR_DABRMATCH | DSISR_KEYFAULT)@h |
398a719d BH |
2387 | ori r0,r0,DSISR_BAD_FAULT_64S@l |
2388 | and. r0,r4,r0 /* weird error? */ | |
0ebc4cda | 2389 | bne- handle_page_fault /* if not, try to insert a HPTE */ |
c911d2e1 | 2390 | ld r11, PACA_THREAD_INFO(r13) |
9c1e1052 PM |
2391 | lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ |
2392 | andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ | |
2393 | bne 77f /* then don't call hash_page now */ | |
0ebc4cda BH |
2394 | |
2395 | /* | |
2396 | * r3 contains the faulting address | |
106713a1 | 2397 | * r4 msr |
0ebc4cda | 2398 | * r5 contains the trap number |
aefa5688 | 2399 | * r6 contains dsisr |
0ebc4cda | 2400 | * |
7230c564 | 2401 | * at return r3 = 0 for success, 1 for page fault, negative for error |
0ebc4cda | 2402 | */ |
106713a1 | 2403 | mr r4,r12 |
aefa5688 | 2404 | ld r6,_DSISR(r1) |
106713a1 AK |
2405 | bl __hash_page /* build HPTE if possible */ |
2406 | cmpdi r3,0 /* see if __hash_page succeeded */ | |
0ebc4cda | 2407 | |
7230c564 | 2408 | /* Success */ |
0ebc4cda | 2409 | beq fast_exc_return_irq /* Return from exception on success */ |
0ebc4cda | 2410 | |
7230c564 BH |
2411 | /* Error */ |
2412 | blt- 13f | |
d89ba535 NR |
2413 | |
2414 | /* Reload DSISR into r4 for the DABR check below */ | |
2415 | ld r4,_DSISR(r1) | |
4e003747 | 2416 | #endif /* CONFIG_PPC_BOOK3S_64 */ |
9c7cc234 | 2417 | |
0ebc4cda BH |
2418 | /* Here we have a page fault that hash_page can't handle. */ |
2419 | handle_page_fault: | |
d89ba535 NR |
2420 | 11: andis. r0,r4,DSISR_DABRMATCH@h |
2421 | bne- handle_dabr_fault | |
2422 | ld r4,_DAR(r1) | |
0ebc4cda BH |
2423 | ld r5,_DSISR(r1) |
2424 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec | 2425 | bl do_page_fault |
0ebc4cda | 2426 | cmpdi r3,0 |
f474c28f | 2427 | beq+ ret_from_except_lite |
b1576fec | 2428 | bl save_nvgprs |
0ebc4cda BH |
2429 | mr r5,r3 |
2430 | addi r3,r1,STACK_FRAME_OVERHEAD | |
2431 | lwz r4,_DAR(r1) | |
b1576fec AB |
2432 | bl bad_page_fault |
2433 | b ret_from_except | |
0ebc4cda | 2434 | |
a546498f BH |
2435 | /* We have a data breakpoint exception - handle it */ |
2436 | handle_dabr_fault: | |
b1576fec | 2437 | bl save_nvgprs |
a546498f BH |
2438 | ld r4,_DAR(r1) |
2439 | ld r5,_DSISR(r1) | |
2440 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec | 2441 | bl do_break |
f474c28f RB |
2442 | /* |
2443 | * do_break() may have changed the NV GPRS while handling a breakpoint. | |
2444 | * If so, we need to restore them with their updated values. Don't use | |
2445 | * ret_from_except_lite here. | |
2446 | */ | |
2447 | b ret_from_except | |
a546498f | 2448 | |
0ebc4cda | 2449 | |
4e003747 | 2450 | #ifdef CONFIG_PPC_BOOK3S_64 |
0ebc4cda BH |
2451 | /* We have a page fault that hash_page could handle but HV refused |
2452 | * the PTE insertion | |
2453 | */ | |
b1576fec | 2454 | 13: bl save_nvgprs |
0ebc4cda BH |
2455 | mr r5,r3 |
2456 | addi r3,r1,STACK_FRAME_OVERHEAD | |
2457 | ld r4,_DAR(r1) | |
b1576fec AB |
2458 | bl low_hash_fault |
2459 | b ret_from_except | |
caca285e | 2460 | #endif |
0ebc4cda | 2461 | |
9c1e1052 PM |
2462 | /* |
2463 | * We come here as a result of a DSI at a point where we don't want | |
2464 | * to call hash_page, such as when we are accessing memory (possibly | |
2465 | * user memory) inside a PMU interrupt that occurred while interrupts | |
2466 | * were soft-disabled. We want to invoke the exception handler for | |
2467 | * the access, or panic if there isn't a handler. | |
2468 | */ | |
b1576fec | 2469 | 77: bl save_nvgprs |
9c1e1052 PM |
2470 | mr r4,r3 |
2471 | addi r3,r1,STACK_FRAME_OVERHEAD | |
2472 | li r5,SIGSEGV | |
b1576fec AB |
2473 | bl bad_page_fault |
2474 | b ret_from_except | |
4e2bf01b ME |
2475 | |
2476 | /* | |
2477 | * Here we have detected that the kernel stack pointer is bad. | |
2478 | * R9 contains the saved CR, r13 points to the paca, | |
2479 | * r10 contains the (bad) kernel stack pointer, | |
2480 | * r11 and r12 contain the saved SRR0 and SRR1. | |
2481 | * We switch to using an emergency stack, save the registers there, | |
2482 | * and call kernel_bad_stack(), which panics. | |
2483 | */ | |
2484 | bad_stack: | |
2485 | ld r1,PACAEMERGSP(r13) | |
2486 | subi r1,r1,64+INT_FRAME_SIZE | |
2487 | std r9,_CCR(r1) | |
2488 | std r10,GPR1(r1) | |
2489 | std r11,_NIP(r1) | |
2490 | std r12,_MSR(r1) | |
2491 | mfspr r11,SPRN_DAR | |
2492 | mfspr r12,SPRN_DSISR | |
2493 | std r11,_DAR(r1) | |
2494 | std r12,_DSISR(r1) | |
2495 | mflr r10 | |
2496 | mfctr r11 | |
2497 | mfxer r12 | |
2498 | std r10,_LINK(r1) | |
2499 | std r11,_CTR(r1) | |
2500 | std r12,_XER(r1) | |
2501 | SAVE_GPR(0,r1) | |
2502 | SAVE_GPR(2,r1) | |
2503 | ld r10,EX_R3(r3) | |
2504 | std r10,GPR3(r1) | |
2505 | SAVE_GPR(4,r1) | |
2506 | SAVE_4GPRS(5,r1) | |
2507 | ld r9,EX_R9(r3) | |
2508 | ld r10,EX_R10(r3) | |
2509 | SAVE_2GPRS(9,r1) | |
2510 | ld r9,EX_R11(r3) | |
2511 | ld r10,EX_R12(r3) | |
2512 | ld r11,EX_R13(r3) | |
2513 | std r9,GPR11(r1) | |
2514 | std r10,GPR12(r1) | |
2515 | std r11,GPR13(r1) | |
2516 | BEGIN_FTR_SECTION | |
2517 | ld r10,EX_CFAR(r3) | |
2518 | std r10,ORIG_GPR3(r1) | |
2519 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
2520 | SAVE_8GPRS(14,r1) | |
2521 | SAVE_10GPRS(22,r1) | |
2522 | lhz r12,PACA_TRAP_SAVE(r13) | |
2523 | std r12,_TRAP(r1) | |
2524 | addi r11,r1,INT_FRAME_SIZE | |
2525 | std r11,0(r1) | |
2526 | li r12,0 | |
2527 | std r12,0(r11) | |
2528 | ld r2,PACATOC(r13) | |
2529 | ld r11,exception_marker@toc(r2) | |
2530 | std r12,RESULT(r1) | |
2531 | std r11,STACK_FRAME_OVERHEAD-16(r1) | |
2532 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
2533 | bl kernel_bad_stack | |
2534 | b 1b | |
15770a13 | 2535 | _ASM_NOKPROBE_SYMBOL(bad_stack); |
0f0c6ca1 | 2536 | |
a9af97aa NP |
2537 | /* |
2538 | * When doorbell is triggered from system reset wakeup, the message is | |
2539 | * not cleared, so it would fire again when EE is enabled. | |
2540 | * | |
2541 | * When coming from local_irq_enable, there may be the same problem if | |
2542 | * we were hard disabled. | |
2543 | * | |
2544 | * Execute msgclr to clear pending exceptions before handling it. | |
2545 | */ | |
2546 | h_doorbell_common_msgclr: | |
2547 | LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) | |
2548 | PPC_MSGCLR(3) | |
2549 | b h_doorbell_common | |
2550 | ||
2551 | doorbell_super_common_msgclr: | |
2552 | LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) | |
2553 | PPC_MSGCLRP(3) | |
2554 | b doorbell_super_common | |
2555 | ||
0f0c6ca1 NP |
2556 | /* |
2557 | * Called from arch_local_irq_enable when an interrupt needs | |
2558 | * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate | |
2559 | * which kind of interrupt. MSR:EE is already off. We generate a | |
2560 | * stackframe like if a real interrupt had happened. | |
2561 | * | |
2562 | * Note: While MSR:EE is off, we need to make sure that _MSR | |
2563 | * in the generated frame has EE set to 1 or the exception | |
2564 | * handler will not properly re-enable them. | |
b48bbb82 NP |
2565 | * |
2566 | * Note that we don't specify LR as the NIP (return address) for | |
2567 | * the interrupt because that would unbalance the return branch | |
2568 | * predictor. | |
0f0c6ca1 NP |
2569 | */ |
2570 | _GLOBAL(__replay_interrupt) | |
2571 | /* We are going to jump to the exception common code which | |
2572 | * will retrieve various register values from the PACA which | |
2573 | * we don't give a damn about, so we don't bother storing them. | |
2574 | */ | |
2575 | mfmsr r12 | |
3e23a12b | 2576 | LOAD_REG_ADDR(r11, replay_interrupt_return) |
0f0c6ca1 NP |
2577 | mfcr r9 |
2578 | ori r12,r12,MSR_EE | |
2579 | cmpwi r3,0x900 | |
2580 | beq decrementer_common | |
2581 | cmpwi r3,0x500 | |
e6c1203d NP |
2582 | BEGIN_FTR_SECTION |
2583 | beq h_virt_irq_common | |
2584 | FTR_SECTION_ELSE | |
0f0c6ca1 | 2585 | beq hardware_interrupt_common |
e6c1203d | 2586 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_300) |
f442d004 MS |
2587 | cmpwi r3,0xf00 |
2588 | beq performance_monitor_common | |
0f0c6ca1 | 2589 | BEGIN_FTR_SECTION |
d6f73fc6 | 2590 | cmpwi r3,0xa00 |
a9af97aa | 2591 | beq h_doorbell_common_msgclr |
0f0c6ca1 NP |
2592 | cmpwi r3,0xe60 |
2593 | beq hmi_exception_common | |
2594 | FTR_SECTION_ELSE | |
2595 | cmpwi r3,0xa00 | |
a9af97aa | 2596 | beq doorbell_super_common_msgclr |
0f0c6ca1 | 2597 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
3e23a12b | 2598 | replay_interrupt_return: |
0f0c6ca1 | 2599 | blr |
b48bbb82 | 2600 | |
15770a13 | 2601 | _ASM_NOKPROBE_SYMBOL(__replay_interrupt) |