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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
0ebc4cda BH |
2 | /* |
3 | * This file contains the 64-bit "server" PowerPC variant | |
4 | * of the low level exception handling including exception | |
5 | * vectors, exception return, part of the slb and stab | |
6 | * handling and other fixed offset specific things. | |
7 | * | |
8 | * This file is meant to be #included from head_64.S due to | |
25985edc | 9 | * position dependent assembly. |
0ebc4cda BH |
10 | * |
11 | * Most of this originates from head_64.S and thus has the same | |
12 | * copyright history. | |
13 | * | |
14 | */ | |
15 | ||
7230c564 | 16 | #include <asm/hw_irq.h> |
8aa34ab8 | 17 | #include <asm/exception-64s.h> |
46f52210 | 18 | #include <asm/ptrace.h> |
7cba160a | 19 | #include <asm/cpuidle.h> |
da2bc464 | 20 | #include <asm/head-64.h> |
2c86cd18 | 21 | #include <asm/feature-fixups.h> |
890274c2 | 22 | #include <asm/kup.h> |
8aa34ab8 | 23 | |
15820091 NP |
24 | /* PACA save area offsets (exgen, exmc, etc) */ |
25 | #define EX_R9 0 | |
26 | #define EX_R10 8 | |
27 | #define EX_R11 16 | |
28 | #define EX_R12 24 | |
29 | #define EX_R13 32 | |
30 | #define EX_DAR 40 | |
31 | #define EX_DSISR 48 | |
32 | #define EX_CCR 52 | |
33 | #define EX_CFAR 56 | |
34 | #define EX_PPR 64 | |
35 | #if defined(CONFIG_RELOCATABLE) | |
36 | #define EX_CTR 72 | |
37 | .if EX_SIZE != 10 | |
38 | .error "EX_SIZE is wrong" | |
39 | .endif | |
40 | #else | |
41 | .if EX_SIZE != 9 | |
42 | .error "EX_SIZE is wrong" | |
43 | .endif | |
44 | #endif | |
45 | ||
12a04809 NP |
46 | /* |
47 | * We're short on space and time in the exception prolog, so we can't | |
48 | * use the normal LOAD_REG_IMMEDIATE macro to load the address of label. | |
49 | * Instead we get the base of the kernel from paca->kernelbase and or in the low | |
50 | * part of label. This requires that the label be within 64KB of kernelbase, and | |
51 | * that kernelbase be 64K aligned. | |
52 | */ | |
53 | #define LOAD_HANDLER(reg, label) \ | |
54 | ld reg,PACAKBASE(r13); /* get high part of &label */ \ | |
55 | ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label) | |
56 | ||
57 | #define __LOAD_HANDLER(reg, label) \ | |
58 | ld reg,PACAKBASE(r13); \ | |
59 | ori reg,reg,(ABS_ADDR(label))@l | |
60 | ||
61 | /* | |
62 | * Branches from unrelocated code (e.g., interrupts) to labels outside | |
63 | * head-y require >64K offsets. | |
64 | */ | |
65 | #define __LOAD_FAR_HANDLER(reg, label) \ | |
66 | ld reg,PACAKBASE(r13); \ | |
67 | ori reg,reg,(ABS_ADDR(label))@l; \ | |
68 | addis reg,reg,(ABS_ADDR(label))@h | |
69 | ||
70 | /* Exception register prefixes */ | |
71 | #define EXC_HV 1 | |
72 | #define EXC_STD 0 | |
73 | ||
74 | #if defined(CONFIG_RELOCATABLE) | |
75 | /* | |
76 | * If we support interrupts with relocation on AND we're a relocatable kernel, | |
77 | * we need to use CTR to get to the 2nd level handler. So, save/restore it | |
78 | * when required. | |
79 | */ | |
80 | #define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13) | |
81 | #define GET_CTR(reg, area) ld reg,area+EX_CTR(r13) | |
82 | #define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg | |
83 | #else | |
84 | /* ...else CTR is unused and in register. */ | |
85 | #define SAVE_CTR(reg, area) | |
86 | #define GET_CTR(reg, area) mfctr reg | |
87 | #define RESTORE_CTR(reg, area) | |
88 | #endif | |
89 | ||
90 | /* | |
91 | * PPR save/restore macros used in exceptions-64s.S | |
92 | * Used for P7 or later processors | |
93 | */ | |
94 | #define SAVE_PPR(area, ra) \ | |
95 | BEGIN_FTR_SECTION_NESTED(940) \ | |
96 | ld ra,area+EX_PPR(r13); /* Read PPR from paca */ \ | |
97 | std ra,_PPR(r1); \ | |
98 | END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940) | |
99 | ||
100 | #define RESTORE_PPR_PACA(area, ra) \ | |
101 | BEGIN_FTR_SECTION_NESTED(941) \ | |
102 | ld ra,area+EX_PPR(r13); \ | |
103 | mtspr SPRN_PPR,ra; \ | |
104 | END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941) | |
105 | ||
106 | /* | |
107 | * Get an SPR into a register if the CPU has the given feature | |
108 | */ | |
109 | #define OPT_GET_SPR(ra, spr, ftr) \ | |
110 | BEGIN_FTR_SECTION_NESTED(943) \ | |
111 | mfspr ra,spr; \ | |
112 | END_FTR_SECTION_NESTED(ftr,ftr,943) | |
113 | ||
114 | /* | |
115 | * Set an SPR from a register if the CPU has the given feature | |
116 | */ | |
117 | #define OPT_SET_SPR(ra, spr, ftr) \ | |
118 | BEGIN_FTR_SECTION_NESTED(943) \ | |
119 | mtspr spr,ra; \ | |
120 | END_FTR_SECTION_NESTED(ftr,ftr,943) | |
121 | ||
122 | /* | |
123 | * Save a register to the PACA if the CPU has the given feature | |
124 | */ | |
125 | #define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \ | |
126 | BEGIN_FTR_SECTION_NESTED(943) \ | |
127 | std ra,offset(r13); \ | |
128 | END_FTR_SECTION_NESTED(ftr,ftr,943) | |
129 | ||
130 | .macro EXCEPTION_PROLOG_0 area | |
d7fb34c7 | 131 | SET_SCRATCH0(r13) /* save r13 */ |
12a04809 NP |
132 | GET_PACA(r13) |
133 | std r9,\area\()+EX_R9(r13) /* save r9 */ | |
134 | OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR) | |
135 | HMT_MEDIUM | |
136 | std r10,\area\()+EX_R10(r13) /* save r10 - r12 */ | |
137 | OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR) | |
138 | .endm | |
139 | ||
5312c494 | 140 | .macro EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, dar, dsisr, bitmask |
12a04809 NP |
141 | OPT_SAVE_REG_TO_PACA(\area\()+EX_PPR, r9, CPU_FTR_HAS_PPR) |
142 | OPT_SAVE_REG_TO_PACA(\area\()+EX_CFAR, r10, CPU_FTR_CFAR) | |
143 | INTERRUPT_TO_KERNEL | |
144 | SAVE_CTR(r10, \area\()) | |
145 | mfcr r9 | |
146 | .if \kvm | |
147 | KVMTEST \hsrr \vec | |
148 | .endif | |
149 | .if \bitmask | |
150 | lbz r10,PACAIRQSOFTMASK(r13) | |
151 | andi. r10,r10,\bitmask | |
152 | /* Associate vector numbers with bits in paca->irq_happened */ | |
153 | .if \vec == 0x500 || \vec == 0xea0 | |
154 | li r10,PACA_IRQ_EE | |
155 | .elseif \vec == 0x900 | |
156 | li r10,PACA_IRQ_DEC | |
157 | .elseif \vec == 0xa00 || \vec == 0xe80 | |
158 | li r10,PACA_IRQ_DBELL | |
159 | .elseif \vec == 0xe60 | |
160 | li r10,PACA_IRQ_HMI | |
161 | .elseif \vec == 0xf00 | |
162 | li r10,PACA_IRQ_PMI | |
163 | .else | |
164 | .abort "Bad maskable vector" | |
165 | .endif | |
166 | ||
167 | .if \hsrr | |
168 | bne masked_Hinterrupt | |
169 | .else | |
170 | bne masked_interrupt | |
171 | .endif | |
172 | .endif | |
173 | ||
174 | std r11,\area\()+EX_R11(r13) | |
175 | std r12,\area\()+EX_R12(r13) | |
5312c494 NP |
176 | |
177 | /* | |
178 | * DAR/DSISR, SCRATCH0 must be read before setting MSR[RI], | |
179 | * because a d-side MCE will clobber those registers so is | |
180 | * not recoverable if they are live. | |
181 | */ | |
12a04809 NP |
182 | GET_SCRATCH0(r10) |
183 | std r10,\area\()+EX_R13(r13) | |
5312c494 NP |
184 | .if \dar |
185 | mfspr r10,SPRN_DAR | |
186 | std r10,\area\()+EX_DAR(r13) | |
187 | .endif | |
188 | .if \dsisr | |
189 | mfspr r10,SPRN_DSISR | |
190 | stw r10,\area\()+EX_DSISR(r13) | |
191 | .endif | |
12a04809 NP |
192 | .endm |
193 | ||
194 | .macro EXCEPTION_PROLOG_2_REAL label, hsrr, set_ri | |
195 | ld r10,PACAKMSR(r13) /* get MSR value for kernel */ | |
196 | .if ! \set_ri | |
197 | xori r10,r10,MSR_RI /* Clear MSR_RI */ | |
198 | .endif | |
199 | .if \hsrr | |
200 | mfspr r11,SPRN_HSRR0 /* save HSRR0 */ | |
63d60d0c NP |
201 | mfspr r12,SPRN_HSRR1 /* and HSRR1 */ |
202 | mtspr SPRN_HSRR1,r10 | |
12a04809 NP |
203 | .else |
204 | mfspr r11,SPRN_SRR0 /* save SRR0 */ | |
63d60d0c NP |
205 | mfspr r12,SPRN_SRR1 /* and SRR1 */ |
206 | mtspr SPRN_SRR1,r10 | |
12a04809 | 207 | .endif |
63d60d0c | 208 | LOAD_HANDLER(r10, \label\()) |
12a04809 | 209 | .if \hsrr |
63d60d0c | 210 | mtspr SPRN_HSRR0,r10 |
12a04809 NP |
211 | HRFI_TO_KERNEL |
212 | .else | |
63d60d0c | 213 | mtspr SPRN_SRR0,r10 |
12a04809 NP |
214 | RFI_TO_KERNEL |
215 | .endif | |
216 | b . /* prevent speculative execution */ | |
217 | .endm | |
218 | ||
219 | .macro EXCEPTION_PROLOG_2_VIRT label, hsrr | |
220 | #ifdef CONFIG_RELOCATABLE | |
221 | .if \hsrr | |
222 | mfspr r11,SPRN_HSRR0 /* save HSRR0 */ | |
223 | .else | |
224 | mfspr r11,SPRN_SRR0 /* save SRR0 */ | |
225 | .endif | |
226 | LOAD_HANDLER(r12, \label\()) | |
227 | mtctr r12 | |
228 | .if \hsrr | |
229 | mfspr r12,SPRN_HSRR1 /* and HSRR1 */ | |
230 | .else | |
231 | mfspr r12,SPRN_SRR1 /* and HSRR1 */ | |
232 | .endif | |
233 | li r10,MSR_RI | |
234 | mtmsrd r10,1 /* Set RI (EE=0) */ | |
235 | bctr | |
236 | #else | |
237 | .if \hsrr | |
238 | mfspr r11,SPRN_HSRR0 /* save HSRR0 */ | |
239 | mfspr r12,SPRN_HSRR1 /* and HSRR1 */ | |
240 | .else | |
241 | mfspr r11,SPRN_SRR0 /* save SRR0 */ | |
242 | mfspr r12,SPRN_SRR1 /* and SRR1 */ | |
243 | .endif | |
244 | li r10,MSR_RI | |
245 | mtmsrd r10,1 /* Set RI (EE=0) */ | |
246 | b \label | |
247 | #endif | |
248 | .endm | |
249 | ||
250 | /* | |
251 | * Branch to label using its 0xC000 address. This results in instruction | |
252 | * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned | |
253 | * on using mtmsr rather than rfid. | |
254 | * | |
255 | * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than | |
256 | * load KBASE for a slight optimisation. | |
257 | */ | |
258 | #define BRANCH_TO_C000(reg, label) \ | |
0e10be2b | 259 | __LOAD_FAR_HANDLER(reg, label); \ |
12a04809 NP |
260 | mtctr reg; \ |
261 | bctr | |
262 | ||
263 | #ifdef CONFIG_RELOCATABLE | |
12a04809 NP |
264 | #define BRANCH_LINK_TO_FAR(label) \ |
265 | __LOAD_FAR_HANDLER(r12, label); \ | |
266 | mtctr r12; \ | |
267 | bctrl | |
268 | ||
269 | #else | |
12a04809 NP |
270 | #define BRANCH_LINK_TO_FAR(label) \ |
271 | bl label | |
272 | #endif | |
273 | ||
274 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER | |
12a04809 NP |
275 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
276 | /* | |
277 | * If hv is possible, interrupts come into to the hv version | |
278 | * of the kvmppc_interrupt code, which then jumps to the PR handler, | |
279 | * kvmppc_interrupt_pr, if the guest is a PR guest. | |
280 | */ | |
281 | #define kvmppc_interrupt kvmppc_interrupt_hv | |
282 | #else | |
283 | #define kvmppc_interrupt kvmppc_interrupt_pr | |
284 | #endif | |
285 | ||
286 | .macro KVMTEST hsrr, n | |
287 | lbz r10,HSTATE_IN_GUEST(r13) | |
288 | cmpwi r10,0 | |
289 | .if \hsrr | |
290 | bne do_kvm_H\n | |
291 | .else | |
292 | bne do_kvm_\n | |
293 | .endif | |
294 | .endm | |
295 | ||
296 | .macro KVM_HANDLER area, hsrr, n, skip | |
297 | .if \skip | |
298 | cmpwi r10,KVM_GUEST_MODE_SKIP | |
299 | beq 89f | |
300 | .else | |
bf66e3c4 | 301 | BEGIN_FTR_SECTION_NESTED(947) |
12a04809 NP |
302 | ld r10,\area+EX_CFAR(r13) |
303 | std r10,HSTATE_CFAR(r13) | |
bf66e3c4 | 304 | END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947) |
12a04809 NP |
305 | .endif |
306 | ||
bf66e3c4 | 307 | BEGIN_FTR_SECTION_NESTED(948) |
12a04809 NP |
308 | ld r10,\area+EX_PPR(r13) |
309 | std r10,HSTATE_PPR(r13) | |
bf66e3c4 | 310 | END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948) |
12a04809 NP |
311 | ld r10,\area+EX_R10(r13) |
312 | std r12,HSTATE_SCRATCH0(r13) | |
313 | sldi r12,r9,32 | |
314 | /* HSRR variants have the 0x2 bit added to their trap number */ | |
315 | .if \hsrr | |
316 | ori r12,r12,(\n + 0x2) | |
317 | .else | |
318 | ori r12,r12,(\n) | |
319 | .endif | |
64e41351 NP |
320 | |
321 | #ifdef CONFIG_RELOCATABLE | |
322 | /* | |
323 | * KVM requires __LOAD_FAR_HANDLER beause kvmppc_interrupt lives | |
324 | * outside the head section. CONFIG_RELOCATABLE KVM expects CTR | |
325 | * to be saved in HSTATE_SCRATCH1. | |
326 | */ | |
327 | mfctr r9 | |
328 | std r9,HSTATE_SCRATCH1(r13) | |
329 | __LOAD_FAR_HANDLER(r9, kvmppc_interrupt) | |
330 | mtctr r9 | |
331 | ld r9,\area+EX_R9(r13) | |
332 | bctr | |
333 | #else | |
334 | ld r9,\area+EX_R9(r13) | |
335 | b kvmppc_interrupt | |
336 | #endif | |
337 | ||
12a04809 NP |
338 | |
339 | .if \skip | |
340 | 89: mtocrf 0x80,r9 | |
341 | ld r9,\area+EX_R9(r13) | |
342 | ld r10,\area+EX_R10(r13) | |
343 | .if \hsrr | |
344 | b kvmppc_skip_Hinterrupt | |
345 | .else | |
346 | b kvmppc_skip_interrupt | |
347 | .endif | |
348 | .endif | |
349 | .endm | |
350 | ||
351 | #else | |
352 | .macro KVMTEST hsrr, n | |
353 | .endm | |
354 | .macro KVM_HANDLER area, hsrr, n, skip | |
355 | .endm | |
356 | #endif | |
357 | ||
358 | #define EXCEPTION_PROLOG_COMMON_1() \ | |
359 | std r9,_CCR(r1); /* save CR in stackframe */ \ | |
360 | std r11,_NIP(r1); /* save SRR0 in stackframe */ \ | |
361 | std r12,_MSR(r1); /* save SRR1 in stackframe */ \ | |
362 | std r10,0(r1); /* make stack chain pointer */ \ | |
363 | std r0,GPR0(r1); /* save r0 in stackframe */ \ | |
364 | std r10,GPR1(r1); /* save r1 in stackframe */ \ | |
365 | ||
12a04809 NP |
366 | /* Save original regs values from save area to stack frame. */ |
367 | #define EXCEPTION_PROLOG_COMMON_2(area) \ | |
368 | ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ | |
369 | ld r10,area+EX_R10(r13); \ | |
370 | std r9,GPR9(r1); \ | |
371 | std r10,GPR10(r1); \ | |
372 | ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ | |
373 | ld r10,area+EX_R12(r13); \ | |
374 | ld r11,area+EX_R13(r13); \ | |
375 | std r9,GPR11(r1); \ | |
376 | std r10,GPR12(r1); \ | |
377 | std r11,GPR13(r1); \ | |
bf66e3c4 | 378 | BEGIN_FTR_SECTION_NESTED(66); \ |
12a04809 NP |
379 | ld r10,area+EX_CFAR(r13); \ |
380 | std r10,ORIG_GPR3(r1); \ | |
bf66e3c4 | 381 | END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \ |
12a04809 NP |
382 | GET_CTR(r10, area); \ |
383 | std r10,_CTR(r1); | |
384 | ||
d064151f | 385 | #define EXCEPTION_PROLOG_COMMON_3(trap) \ |
12a04809 NP |
386 | std r2,GPR2(r1); /* save r2 in stackframe */ \ |
387 | SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ | |
388 | SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ | |
389 | mflr r9; /* Get LR, later save to stack */ \ | |
390 | ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ | |
391 | std r9,_LINK(r1); \ | |
392 | lbz r10,PACAIRQSOFTMASK(r13); \ | |
393 | mfspr r11,SPRN_XER; /* save XER in stackframe */ \ | |
394 | std r10,SOFTE(r1); \ | |
395 | std r11,_XER(r1); \ | |
d064151f | 396 | li r9,(trap)+1; \ |
12a04809 NP |
397 | std r9,_TRAP(r1); /* set trap number */ \ |
398 | li r10,0; \ | |
399 | ld r11,exception_marker@toc(r2); \ | |
400 | std r10,RESULT(r1); /* clear regs->result */ \ | |
401 | std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ | |
402 | ||
d064151f NP |
403 | /* |
404 | * On entry r13 points to the paca, r9-r13 are saved in the paca, | |
405 | * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and | |
406 | * SRR1, and relocation is on. | |
407 | */ | |
408 | #define EXCEPTION_COMMON(area, trap) \ | |
409 | andi. r10,r12,MSR_PR; /* See if coming from user */ \ | |
410 | mr r10,r1; /* Save r1 */ \ | |
411 | subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ | |
412 | beq- 1f; \ | |
413 | ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ | |
0a882e28 NP |
414 | 1: tdgei r1,-INT_FRAME_SIZE; /* trap if r1 is in userspace */ \ |
415 | EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0; \ | |
d064151f NP |
416 | 3: EXCEPTION_PROLOG_COMMON_1(); \ |
417 | kuap_save_amr_and_lock r9, r10, cr1, cr0; \ | |
418 | beq 4f; /* if from kernel mode */ \ | |
419 | ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \ | |
420 | SAVE_PPR(area, r9); \ | |
421 | 4: EXCEPTION_PROLOG_COMMON_2(area); \ | |
422 | EXCEPTION_PROLOG_COMMON_3(trap); \ | |
423 | ACCOUNT_STOLEN_TIME | |
12a04809 | 424 | |
12a04809 | 425 | /* |
d064151f NP |
426 | * Exception where stack is already set in r1, r1 is saved in r10. |
427 | * PPR save and CPU accounting is not done (for some reason). | |
12a04809 NP |
428 | */ |
429 | #define EXCEPTION_COMMON_STACK(area, trap) \ | |
430 | EXCEPTION_PROLOG_COMMON_1(); \ | |
431 | kuap_save_amr_and_lock r9, r10, cr1; \ | |
432 | EXCEPTION_PROLOG_COMMON_2(area); \ | |
433 | EXCEPTION_PROLOG_COMMON_3(trap) | |
434 | ||
391e941b NP |
435 | /* |
436 | * Restore all registers including H/SRR0/1 saved in a stack frame of a | |
437 | * standard exception. | |
438 | */ | |
439 | .macro EXCEPTION_RESTORE_REGS hsrr | |
440 | /* Move original SRR0 and SRR1 into the respective regs */ | |
441 | ld r9,_MSR(r1) | |
442 | .if \hsrr | |
443 | mtspr SPRN_HSRR1,r9 | |
444 | .else | |
445 | mtspr SPRN_SRR1,r9 | |
446 | .endif | |
447 | ld r9,_NIP(r1) | |
448 | .if \hsrr | |
449 | mtspr SPRN_HSRR0,r9 | |
450 | .else | |
451 | mtspr SPRN_SRR0,r9 | |
452 | .endif | |
453 | ld r9,_CTR(r1) | |
454 | mtctr r9 | |
455 | ld r9,_XER(r1) | |
456 | mtxer r9 | |
457 | ld r9,_LINK(r1) | |
458 | mtlr r9 | |
459 | ld r9,_CCR(r1) | |
460 | mtcr r9 | |
461 | REST_8GPRS(2, r1) | |
462 | REST_4GPRS(10, r1) | |
463 | REST_GPR(0, r1) | |
464 | /* restore original r1. */ | |
465 | ld r1,GPR1(r1) | |
466 | .endm | |
d064151f NP |
467 | |
468 | #define RUNLATCH_ON \ | |
469 | BEGIN_FTR_SECTION \ | |
470 | ld r3, PACA_THREAD_INFO(r13); \ | |
471 | ld r4,TI_LOCAL_FLAGS(r3); \ | |
472 | andi. r0,r4,_TLF_RUNLATCH; \ | |
473 | beql ppc64_runlatch_on_trampoline; \ | |
474 | END_FTR_SECTION_IFSET(CPU_FTR_CTRL) | |
475 | ||
12a04809 NP |
476 | /* |
477 | * When the idle code in power4_idle puts the CPU into NAP mode, | |
478 | * it has to do so in a loop, and relies on the external interrupt | |
479 | * and decrementer interrupt entry code to get it out of the loop. | |
480 | * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags | |
481 | * to signal that it is in the loop and needs help to get out. | |
482 | */ | |
483 | #ifdef CONFIG_PPC_970_NAP | |
484 | #define FINISH_NAP \ | |
485 | BEGIN_FTR_SECTION \ | |
486 | ld r11, PACA_THREAD_INFO(r13); \ | |
487 | ld r9,TI_LOCAL_FLAGS(r11); \ | |
488 | andi. r10,r9,_TLF_NAPPING; \ | |
489 | bnel power4_fixup_nap; \ | |
490 | END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) | |
491 | #else | |
492 | #define FINISH_NAP | |
493 | #endif | |
494 | ||
a0502434 NP |
495 | /* |
496 | * Following are the BOOK3S exception handler helper macros. | |
497 | * Handlers come in a number of types, and each type has a number of varieties. | |
498 | * | |
499 | * EXC_REAL_* - real, unrelocated exception vectors | |
500 | * EXC_VIRT_* - virt (AIL), unrelocated exception vectors | |
501 | * TRAMP_REAL_* - real, unrelocated helpers (virt can call these) | |
502 | * TRAMP_VIRT_* - virt, unreloc helpers (in practice, real can use) | |
503 | * TRAMP_KVM - KVM handlers that get put into real, unrelocated | |
504 | * EXC_COMMON - virt, relocated common handlers | |
505 | * | |
506 | * The EXC handlers are given a name, and branch to name_common, or the | |
507 | * appropriate KVM or masking function. Vector handler verieties are as | |
508 | * follows: | |
509 | * | |
510 | * EXC_{REAL|VIRT}_BEGIN/END - used to open-code the exception | |
511 | * | |
512 | * EXC_{REAL|VIRT} - standard exception | |
513 | * | |
514 | * EXC_{REAL|VIRT}_suffix | |
515 | * where _suffix is: | |
516 | * - _MASKABLE - maskable exception | |
517 | * - _OOL - out of line with trampoline to common handler | |
518 | * - _HV - HV exception | |
519 | * | |
520 | * There can be combinations, e.g., EXC_VIRT_OOL_MASKABLE_HV | |
521 | * | |
522 | * The one unusual case is __EXC_REAL_OOL_HV_DIRECT, which is | |
523 | * an OOL vector that branches to a specified handler rather than the usual | |
524 | * trampoline that goes to common. It, and other underscore macros, should | |
525 | * be used with care. | |
526 | * | |
527 | * KVM handlers come in the following verieties: | |
528 | * TRAMP_KVM | |
529 | * TRAMP_KVM_SKIP | |
530 | * TRAMP_KVM_HV | |
531 | * TRAMP_KVM_HV_SKIP | |
532 | * | |
533 | * COMMON handlers come in the following verieties: | |
534 | * EXC_COMMON_BEGIN/END - used to open-code the handler | |
535 | * EXC_COMMON | |
536 | * EXC_COMMON_ASYNC | |
537 | * | |
538 | * TRAMP_REAL and TRAMP_VIRT can be used with BEGIN/END. KVM | |
539 | * and OOL handlers are implemented as types of TRAMP and TRAMP_VIRT handlers. | |
540 | */ | |
541 | ||
542 | #define __EXC_REAL(name, start, size, area) \ | |
543 | EXC_REAL_BEGIN(name, start, size); \ | |
a0502434 | 544 | EXCEPTION_PROLOG_0 area ; \ |
5312c494 | 545 | EXCEPTION_PROLOG_1 EXC_STD, area, 1, start, 0, 0, 0 ; \ |
a0502434 NP |
546 | EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 ; \ |
547 | EXC_REAL_END(name, start, size) | |
548 | ||
549 | #define EXC_REAL(name, start, size) \ | |
550 | __EXC_REAL(name, start, size, PACA_EXGEN) | |
551 | ||
552 | #define __EXC_VIRT(name, start, size, realvec, area) \ | |
553 | EXC_VIRT_BEGIN(name, start, size); \ | |
a0502434 | 554 | EXCEPTION_PROLOG_0 area ; \ |
5312c494 | 555 | EXCEPTION_PROLOG_1 EXC_STD, area, 0, realvec, 0, 0, 0; \ |
a0502434 NP |
556 | EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD ; \ |
557 | EXC_VIRT_END(name, start, size) | |
558 | ||
559 | #define EXC_VIRT(name, start, size, realvec) \ | |
560 | __EXC_VIRT(name, start, size, realvec, PACA_EXGEN) | |
561 | ||
562 | #define EXC_REAL_MASKABLE(name, start, size, bitmask) \ | |
563 | EXC_REAL_BEGIN(name, start, size); \ | |
a0502434 | 564 | EXCEPTION_PROLOG_0 PACA_EXGEN ; \ |
5312c494 | 565 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, start, 0, 0, bitmask ; \ |
a0502434 NP |
566 | EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 ; \ |
567 | EXC_REAL_END(name, start, size) | |
568 | ||
569 | #define EXC_VIRT_MASKABLE(name, start, size, realvec, bitmask) \ | |
570 | EXC_VIRT_BEGIN(name, start, size); \ | |
a0502434 | 571 | EXCEPTION_PROLOG_0 PACA_EXGEN ; \ |
5312c494 | 572 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, realvec, 0, 0, bitmask ; \ |
a0502434 NP |
573 | EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD ; \ |
574 | EXC_VIRT_END(name, start, size) | |
575 | ||
576 | #define EXC_REAL_HV(name, start, size) \ | |
577 | EXC_REAL_BEGIN(name, start, size); \ | |
a0502434 | 578 | EXCEPTION_PROLOG_0 PACA_EXGEN; \ |
5312c494 | 579 | EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, start, 0, 0, 0 ; \ |
a0502434 NP |
580 | EXCEPTION_PROLOG_2_REAL name##_common, EXC_HV, 1 ; \ |
581 | EXC_REAL_END(name, start, size) | |
582 | ||
583 | #define EXC_VIRT_HV(name, start, size, realvec) \ | |
584 | EXC_VIRT_BEGIN(name, start, size); \ | |
a0502434 | 585 | EXCEPTION_PROLOG_0 PACA_EXGEN; \ |
5312c494 | 586 | EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, 0, 0, 0 ; \ |
a0502434 NP |
587 | EXCEPTION_PROLOG_2_VIRT name##_common, EXC_HV ; \ |
588 | EXC_VIRT_END(name, start, size) | |
589 | ||
590 | #define __EXC_REAL_OOL(name, start, size) \ | |
591 | EXC_REAL_BEGIN(name, start, size); \ | |
a0502434 NP |
592 | EXCEPTION_PROLOG_0 PACA_EXGEN ; \ |
593 | b tramp_real_##name ; \ | |
594 | EXC_REAL_END(name, start, size) | |
595 | ||
596 | #define __TRAMP_REAL_OOL(name, vec) \ | |
597 | TRAMP_REAL_BEGIN(tramp_real_##name); \ | |
5312c494 | 598 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec, 0, 0, 0 ; \ |
a0502434 NP |
599 | EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 |
600 | ||
601 | #define EXC_REAL_OOL(name, start, size) \ | |
602 | __EXC_REAL_OOL(name, start, size); \ | |
603 | __TRAMP_REAL_OOL(name, start) | |
604 | ||
605 | #define __EXC_REAL_OOL_MASKABLE(name, start, size) \ | |
606 | __EXC_REAL_OOL(name, start, size) | |
607 | ||
608 | #define __TRAMP_REAL_OOL_MASKABLE(name, vec, bitmask) \ | |
609 | TRAMP_REAL_BEGIN(tramp_real_##name); \ | |
5312c494 | 610 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec, 0, 0, bitmask ; \ |
a0502434 NP |
611 | EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 |
612 | ||
613 | #define EXC_REAL_OOL_MASKABLE(name, start, size, bitmask) \ | |
614 | __EXC_REAL_OOL_MASKABLE(name, start, size); \ | |
615 | __TRAMP_REAL_OOL_MASKABLE(name, start, bitmask) | |
616 | ||
617 | #define __EXC_REAL_OOL_HV_DIRECT(name, start, size, handler) \ | |
618 | EXC_REAL_BEGIN(name, start, size); \ | |
a0502434 NP |
619 | EXCEPTION_PROLOG_0 PACA_EXGEN ; \ |
620 | b handler; \ | |
621 | EXC_REAL_END(name, start, size) | |
622 | ||
623 | #define __EXC_REAL_OOL_HV(name, start, size) \ | |
624 | __EXC_REAL_OOL(name, start, size) | |
625 | ||
626 | #define __TRAMP_REAL_OOL_HV(name, vec) \ | |
627 | TRAMP_REAL_BEGIN(tramp_real_##name); \ | |
5312c494 | 628 | EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, 0, 0, 0 ; \ |
a0502434 NP |
629 | EXCEPTION_PROLOG_2_REAL name##_common, EXC_HV, 1 |
630 | ||
631 | #define EXC_REAL_OOL_HV(name, start, size) \ | |
632 | __EXC_REAL_OOL_HV(name, start, size); \ | |
633 | __TRAMP_REAL_OOL_HV(name, start) | |
634 | ||
635 | #define __EXC_REAL_OOL_MASKABLE_HV(name, start, size) \ | |
636 | __EXC_REAL_OOL(name, start, size) | |
637 | ||
638 | #define __TRAMP_REAL_OOL_MASKABLE_HV(name, vec, bitmask) \ | |
639 | TRAMP_REAL_BEGIN(tramp_real_##name); \ | |
5312c494 | 640 | EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, 0, 0, bitmask ; \ |
a0502434 NP |
641 | EXCEPTION_PROLOG_2_REAL name##_common, EXC_HV, 1 |
642 | ||
643 | #define EXC_REAL_OOL_MASKABLE_HV(name, start, size, bitmask) \ | |
644 | __EXC_REAL_OOL_MASKABLE_HV(name, start, size); \ | |
645 | __TRAMP_REAL_OOL_MASKABLE_HV(name, start, bitmask) | |
646 | ||
647 | #define __EXC_VIRT_OOL(name, start, size) \ | |
648 | EXC_VIRT_BEGIN(name, start, size); \ | |
a0502434 NP |
649 | EXCEPTION_PROLOG_0 PACA_EXGEN ; \ |
650 | b tramp_virt_##name; \ | |
651 | EXC_VIRT_END(name, start, size) | |
652 | ||
653 | #define __TRAMP_VIRT_OOL(name, realvec) \ | |
654 | TRAMP_VIRT_BEGIN(tramp_virt_##name); \ | |
5312c494 | 655 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, vec, 0, 0, 0 ; \ |
a0502434 NP |
656 | EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD |
657 | ||
658 | #define EXC_VIRT_OOL(name, start, size, realvec) \ | |
659 | __EXC_VIRT_OOL(name, start, size); \ | |
660 | __TRAMP_VIRT_OOL(name, realvec) | |
661 | ||
662 | #define __EXC_VIRT_OOL_MASKABLE(name, start, size) \ | |
663 | __EXC_VIRT_OOL(name, start, size) | |
664 | ||
665 | #define __TRAMP_VIRT_OOL_MASKABLE(name, realvec, bitmask) \ | |
666 | TRAMP_VIRT_BEGIN(tramp_virt_##name); \ | |
5312c494 | 667 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, realvec, 0, 0, bitmask ; \ |
a0502434 NP |
668 | EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 |
669 | ||
670 | #define EXC_VIRT_OOL_MASKABLE(name, start, size, realvec, bitmask) \ | |
671 | __EXC_VIRT_OOL_MASKABLE(name, start, size); \ | |
672 | __TRAMP_VIRT_OOL_MASKABLE(name, realvec, bitmask) | |
673 | ||
674 | #define __EXC_VIRT_OOL_HV(name, start, size) \ | |
675 | __EXC_VIRT_OOL(name, start, size) | |
676 | ||
677 | #define __TRAMP_VIRT_OOL_HV(name, realvec) \ | |
678 | TRAMP_VIRT_BEGIN(tramp_virt_##name); \ | |
5312c494 | 679 | EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, 0, 0, 0 ; \ |
a0502434 NP |
680 | EXCEPTION_PROLOG_2_VIRT name##_common, EXC_HV |
681 | ||
682 | #define EXC_VIRT_OOL_HV(name, start, size, realvec) \ | |
683 | __EXC_VIRT_OOL_HV(name, start, size); \ | |
684 | __TRAMP_VIRT_OOL_HV(name, realvec) | |
685 | ||
686 | #define __EXC_VIRT_OOL_MASKABLE_HV(name, start, size) \ | |
687 | __EXC_VIRT_OOL(name, start, size) | |
688 | ||
689 | #define __TRAMP_VIRT_OOL_MASKABLE_HV(name, realvec, bitmask) \ | |
690 | TRAMP_VIRT_BEGIN(tramp_virt_##name); \ | |
5312c494 | 691 | EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, 0, 0, bitmask ; \ |
a0502434 NP |
692 | EXCEPTION_PROLOG_2_VIRT name##_common, EXC_HV |
693 | ||
694 | #define EXC_VIRT_OOL_MASKABLE_HV(name, start, size, realvec, bitmask) \ | |
695 | __EXC_VIRT_OOL_MASKABLE_HV(name, start, size); \ | |
696 | __TRAMP_VIRT_OOL_MASKABLE_HV(name, realvec, bitmask) | |
697 | ||
698 | #define TRAMP_KVM(area, n) \ | |
699 | TRAMP_KVM_BEGIN(do_kvm_##n); \ | |
700 | KVM_HANDLER area, EXC_STD, n, 0 | |
701 | ||
702 | #define TRAMP_KVM_SKIP(area, n) \ | |
703 | TRAMP_KVM_BEGIN(do_kvm_##n); \ | |
704 | KVM_HANDLER area, EXC_STD, n, 1 | |
705 | ||
706 | #define TRAMP_KVM_HV(area, n) \ | |
707 | TRAMP_KVM_BEGIN(do_kvm_H##n); \ | |
708 | KVM_HANDLER area, EXC_HV, n, 0 | |
709 | ||
710 | #define TRAMP_KVM_HV_SKIP(area, n) \ | |
711 | TRAMP_KVM_BEGIN(do_kvm_H##n); \ | |
712 | KVM_HANDLER area, EXC_HV, n, 1 | |
713 | ||
714 | #define EXC_COMMON(name, realvec, hdlr) \ | |
715 | EXC_COMMON_BEGIN(name); \ | |
716 | EXCEPTION_COMMON(PACA_EXGEN, realvec); \ | |
717 | bl save_nvgprs; \ | |
718 | RECONCILE_IRQ_STATE(r10, r11); \ | |
719 | addi r3,r1,STACK_FRAME_OVERHEAD; \ | |
720 | bl hdlr; \ | |
721 | b ret_from_except | |
722 | ||
723 | /* | |
724 | * Like EXC_COMMON, but for exceptions that can occur in the idle task and | |
725 | * therefore need the special idle handling (finish nap and runlatch) | |
726 | */ | |
727 | #define EXC_COMMON_ASYNC(name, realvec, hdlr) \ | |
728 | EXC_COMMON_BEGIN(name); \ | |
729 | EXCEPTION_COMMON(PACA_EXGEN, realvec); \ | |
730 | FINISH_NAP; \ | |
731 | RECONCILE_IRQ_STATE(r10, r11); \ | |
732 | RUNLATCH_ON; \ | |
733 | addi r3,r1,STACK_FRAME_OVERHEAD; \ | |
734 | bl hdlr; \ | |
735 | b ret_from_except_lite | |
736 | ||
12a04809 | 737 | |
0ebc4cda | 738 | /* |
57f26649 NP |
739 | * There are a few constraints to be concerned with. |
740 | * - Real mode exceptions code/data must be located at their physical location. | |
741 | * - Virtual mode exceptions must be mapped at their 0xc000... location. | |
742 | * - Fixed location code must not call directly beyond the __end_interrupts | |
743 | * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence | |
744 | * must be used. | |
745 | * - LOAD_HANDLER targets must be within first 64K of physical 0 / | |
746 | * virtual 0xc00... | |
747 | * - Conditional branch targets must be within +/-32K of caller. | |
748 | * | |
749 | * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and | |
750 | * therefore don't have to run in physically located code or rfid to | |
751 | * virtual mode kernel code. However on relocatable kernels they do have | |
752 | * to branch to KERNELBASE offset because the rest of the kernel (outside | |
753 | * the exception vectors) may be located elsewhere. | |
754 | * | |
755 | * Virtual exceptions correspond with physical, except their entry points | |
756 | * are offset by 0xc000000000000000 and also tend to get an added 0x4000 | |
757 | * offset applied. Virtual exceptions are enabled with the Alternate | |
758 | * Interrupt Location (AIL) bit set in the LPCR. However this does not | |
759 | * guarantee they will be delivered virtually. Some conditions (see the ISA) | |
760 | * cause exceptions to be delivered in real mode. | |
761 | * | |
762 | * It's impossible to receive interrupts below 0x300 via AIL. | |
763 | * | |
764 | * KVM: None of the virtual exceptions are from the guest. Anything that | |
765 | * escalated to HV=1 from HV=0 is delivered via real mode handlers. | |
766 | * | |
767 | * | |
0ebc4cda BH |
768 | * We layout physical memory as follows: |
769 | * 0x0000 - 0x00ff : Secondary processor spin code | |
57f26649 NP |
770 | * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors |
771 | * 0x1900 - 0x3fff : Real mode trampolines | |
772 | * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors | |
773 | * 0x5900 - 0x6fff : Relon mode trampolines | |
0ebc4cda | 774 | * 0x7000 - 0x7fff : FWNMI data area |
57f26649 NP |
775 | * 0x8000 - .... : Common interrupt handlers, remaining early |
776 | * setup code, rest of kernel. | |
e0319829 NP |
777 | * |
778 | * We could reclaim 0x4000-0x42ff for real mode trampolines if the space | |
779 | * is necessary. Until then it's more consistent to explicitly put VIRT_NONE | |
780 | * vectors there. | |
57f26649 NP |
781 | */ |
782 | OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) | |
783 | OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000) | |
784 | OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900) | |
785 | OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) | |
ccd47702 NP |
786 | |
787 | #ifdef CONFIG_PPC_POWERNV | |
bd3524fe NP |
788 | .globl start_real_trampolines |
789 | .globl end_real_trampolines | |
790 | .globl start_virt_trampolines | |
791 | .globl end_virt_trampolines | |
ccd47702 NP |
792 | #endif |
793 | ||
57f26649 NP |
794 | #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) |
795 | /* | |
796 | * Data area reserved for FWNMI option. | |
797 | * This address (0x7000) is fixed by the RPA. | |
798 | * pseries and powernv need to keep the whole page from | |
799 | * 0x7000 to 0x8000 free for use by the firmware | |
0ebc4cda | 800 | */ |
57f26649 NP |
801 | ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) |
802 | OPEN_TEXT_SECTION(0x8000) | |
803 | #else | |
804 | OPEN_TEXT_SECTION(0x7000) | |
805 | #endif | |
806 | ||
807 | USE_FIXED_SECTION(real_vectors) | |
808 | ||
0ebc4cda BH |
809 | /* |
810 | * This is the start of the interrupt handlers for pSeries | |
811 | * This code runs with relocation off. | |
812 | * Code from here to __end_interrupts gets copied down to real | |
813 | * address 0x100 when we are running a relocatable kernel. | |
814 | * Therefore any relative branches in this section must only | |
815 | * branch to labels in this section. | |
816 | */ | |
0ebc4cda BH |
817 | .globl __start_interrupts |
818 | __start_interrupts: | |
819 | ||
e0319829 | 820 | /* No virt vectors corresponding with 0x0..0x100 */ |
1a6822d1 | 821 | EXC_VIRT_NONE(0x4000, 0x100) |
e0319829 | 822 | |
fb479e44 | 823 | |
a7c1ca19 | 824 | EXC_REAL_BEGIN(system_reset, 0x100, 0x100) |
948cf67c | 825 | #ifdef CONFIG_PPC_P7_NAP |
fb479e44 NP |
826 | /* |
827 | * If running native on arch 2.06 or later, check if we are waking up | |
ba6d334a BH |
828 | * from nap/sleep/winkle, and branch to idle handler. This tests SRR1 |
829 | * bits 46:47. A non-0 value indicates that we are coming from a power | |
830 | * saving state. The idle wakeup handler initially runs in real mode, | |
831 | * but we branch to the 0xc000... address so we can turn on relocation | |
0e10be2b NP |
832 | * with mtmsrd later, after SPRs are restored. |
833 | * | |
834 | * Careful to minimise cost for the fast path (idle wakeup) while | |
835 | * also avoiding clobbering CFAR for the debug path (non-idle). | |
836 | * | |
837 | * For the idle wake case volatile registers can be clobbered, which | |
838 | * is why we use those initially. If it turns out to not be an idle | |
839 | * wake, carefully put everything back the way it was, so we can use | |
840 | * common exception macros to handle it. | |
948cf67c | 841 | */ |
bf66e3c4 | 842 | BEGIN_FTR_SECTION |
0e10be2b NP |
843 | SET_SCRATCH0(r13) |
844 | GET_PACA(r13) | |
845 | std r3,PACA_EXNMI+0*8(r13) | |
846 | std r4,PACA_EXNMI+1*8(r13) | |
847 | std r5,PACA_EXNMI+2*8(r13) | |
a7c1ca19 | 848 | mfspr r3,SPRN_SRR1 |
0e10be2b NP |
849 | mfocrf r4,0x80 |
850 | rlwinm. r5,r3,47-31,30,31 | |
851 | bne+ system_reset_idle_wake | |
852 | /* Not powersave wakeup. Restore regs for regular interrupt handler. */ | |
853 | mtocrf 0x80,r4 | |
854 | ld r3,PACA_EXNMI+0*8(r13) | |
855 | ld r4,PACA_EXNMI+1*8(r13) | |
856 | ld r5,PACA_EXNMI+2*8(r13) | |
857 | GET_SCRATCH0(r13) | |
bf66e3c4 | 858 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
fb479e44 | 859 | #endif |
371fefd6 | 860 | |
0e10be2b NP |
861 | EXCEPTION_PROLOG_0 PACA_EXNMI |
862 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXNMI, 1, 0x100, 0, 0, 0 | |
a7c1ca19 | 863 | EXCEPTION_PROLOG_2_REAL system_reset_common, EXC_STD, 0 |
c4f3b52c NP |
864 | /* |
865 | * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is | |
866 | * being used, so a nested NMI exception would corrupt it. | |
0e10be2b NP |
867 | * |
868 | * In theory, we should not enable relocation here if it was disabled | |
869 | * in SRR1, because the MMU may not be configured to support it (e.g., | |
870 | * SLB may have been cleared). In practice, there should only be a few | |
871 | * small windows where that's the case, and sreset is considered to | |
872 | * be dangerous anyway. | |
c4f3b52c | 873 | */ |
1a6822d1 | 874 | EXC_REAL_END(system_reset, 0x100, 0x100) |
0e10be2b | 875 | |
1a6822d1 | 876 | EXC_VIRT_NONE(0x4100, 0x100) |
6de6638b | 877 | TRAMP_KVM(PACA_EXNMI, 0x100) |
fb479e44 NP |
878 | |
879 | #ifdef CONFIG_PPC_P7_NAP | |
0e10be2b NP |
880 | TRAMP_REAL_BEGIN(system_reset_idle_wake) |
881 | /* We are waking up from idle, so may clobber any volatile register */ | |
882 | cmpwi cr1,r5,2 | |
883 | bltlr cr1 /* no state loss, return to idle caller with r3=SRR1 */ | |
884 | BRANCH_TO_C000(r12, DOTSYM(idle_return_gpr_loss)) | |
371fefd6 PM |
885 | #endif |
886 | ||
acc8da44 NP |
887 | #ifdef CONFIG_PPC_PSERIES |
888 | /* | |
889 | * Vectors for the FWNMI option. Share common code. | |
890 | */ | |
891 | TRAMP_REAL_BEGIN(system_reset_fwnmi) | |
892 | /* See comment at system_reset exception, don't turn on RI */ | |
893 | EXCEPTION_PROLOG_0 PACA_EXNMI | |
894 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXNMI, 0, 0x100, 0, 0, 0 | |
895 | EXCEPTION_PROLOG_2_REAL system_reset_common, EXC_STD, 0 | |
896 | ||
897 | #endif /* CONFIG_PPC_PSERIES */ | |
898 | ||
a3d96f70 | 899 | EXC_COMMON_BEGIN(system_reset_common) |
c4f3b52c NP |
900 | /* |
901 | * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able | |
902 | * to recover, but nested NMI will notice in_nmi and not recover | |
903 | * because of the use of the NMI stack. in_nmi reentrancy is tested in | |
904 | * system_reset_exception. | |
905 | */ | |
906 | lhz r10,PACA_IN_NMI(r13) | |
907 | addi r10,r10,1 | |
908 | sth r10,PACA_IN_NMI(r13) | |
909 | li r10,MSR_RI | |
910 | mtmsrd r10,1 | |
aca79d2b | 911 | |
b1ee8a3d NP |
912 | mr r10,r1 |
913 | ld r1,PACA_NMI_EMERG_SP(r13) | |
914 | subi r1,r1,INT_FRAME_SIZE | |
47169fba NP |
915 | EXCEPTION_COMMON_STACK(PACA_EXNMI, 0x100) |
916 | bl save_nvgprs | |
917 | /* | |
918 | * Set IRQS_ALL_DISABLED unconditionally so arch_irqs_disabled does | |
919 | * the right thing. We do not want to reconcile because that goes | |
920 | * through irq tracing which we don't want in NMI. | |
921 | * | |
922 | * Save PACAIRQHAPPENED because some code will do a hard disable | |
923 | * (e.g., xmon). So we want to restore this back to where it was | |
924 | * when we return. DAR is unused in the stack, so save it there. | |
925 | */ | |
926 | li r10,IRQS_ALL_DISABLED | |
927 | stb r10,PACAIRQSOFTMASK(r13) | |
928 | lbz r10,PACAIRQHAPPENED(r13) | |
929 | std r10,_DAR(r1) | |
930 | ||
c06075f3 NP |
931 | addi r3,r1,STACK_FRAME_OVERHEAD |
932 | bl system_reset_exception | |
15b4dd79 | 933 | |
15b4dd79 | 934 | /* Clear MSR_RI before setting SRR0 and SRR1. */ |
fbc50063 | 935 | li r9,0 |
15b4dd79 | 936 | mtmsrd r9,1 |
c4f3b52c NP |
937 | |
938 | /* | |
15b4dd79 | 939 | * MSR_RI is clear, now we can decrement paca->in_nmi. |
c4f3b52c NP |
940 | */ |
941 | lhz r10,PACA_IN_NMI(r13) | |
942 | subi r10,r10,1 | |
943 | sth r10,PACA_IN_NMI(r13) | |
944 | ||
15b4dd79 NP |
945 | /* |
946 | * Restore soft mask settings. | |
947 | */ | |
948 | ld r10,_DAR(r1) | |
949 | stb r10,PACAIRQHAPPENED(r13) | |
950 | ld r10,SOFTE(r1) | |
951 | stb r10,PACAIRQSOFTMASK(r13) | |
952 | ||
391e941b | 953 | EXCEPTION_RESTORE_REGS EXC_STD |
15b4dd79 | 954 | RFI_TO_USER_OR_KERNEL |
582baf44 | 955 | |
0ebc4cda | 956 | |
1a6822d1 | 957 | EXC_REAL_BEGIN(machine_check, 0x200, 0x100) |
b01c8b54 PM |
958 | /* This is moved out of line as it can be patched by FW, but |
959 | * some code path might still want to branch into the original | |
960 | * vector | |
961 | */ | |
5dba1d50 | 962 | EXCEPTION_PROLOG_0 PACA_EXMC |
1e9b4507 | 963 | BEGIN_FTR_SECTION |
db7d31ac | 964 | b machine_check_common_early |
1e9b4507 | 965 | FTR_SECTION_ELSE |
1707dd16 | 966 | b machine_check_pSeries_0 |
1e9b4507 | 967 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
1a6822d1 NP |
968 | EXC_REAL_END(machine_check, 0x200, 0x100) |
969 | EXC_VIRT_NONE(0x4200, 0x100) | |
db7d31ac | 970 | TRAMP_REAL_BEGIN(machine_check_common_early) |
5312c494 | 971 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 0, 0x200, 0, 0, 0 |
afcf0095 NP |
972 | /* |
973 | * Register contents: | |
974 | * R13 = PACA | |
975 | * R9 = CR | |
976 | * Original R9 to R13 is saved on PACA_EXMC | |
977 | * | |
978 | * Switch to mc_emergency stack and handle re-entrancy (we limit | |
979 | * the nested MCE upto level 4 to avoid stack overflow). | |
980 | * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 | |
981 | * | |
982 | * We use paca->in_mce to check whether this is the first entry or | |
983 | * nested machine check. We increment paca->in_mce to track nested | |
984 | * machine checks. | |
985 | * | |
986 | * If this is the first entry then set stack pointer to | |
987 | * paca->mc_emergency_sp, otherwise r1 is already pointing to | |
988 | * stack frame on mc_emergency stack. | |
989 | * | |
990 | * NOTE: We are here with MSR_ME=0 (off), which means we risk a | |
991 | * checkstop if we get another machine check exception before we do | |
992 | * rfid with MSR_ME=1. | |
1945bc45 NP |
993 | * |
994 | * This interrupt can wake directly from idle. If that is the case, | |
995 | * the machine check is handled then the idle wakeup code is called | |
2bf1071a | 996 | * to restore state. |
afcf0095 NP |
997 | */ |
998 | mr r11,r1 /* Save r1 */ | |
999 | lhz r10,PACA_IN_MCE(r13) | |
1000 | cmpwi r10,0 /* Are we in nested machine check */ | |
1001 | bne 0f /* Yes, we are. */ | |
1002 | /* First machine check entry */ | |
1003 | ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ | |
1004 | 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
1005 | addi r10,r10,1 /* increment paca->in_mce */ | |
1006 | sth r10,PACA_IN_MCE(r13) | |
1007 | /* Limit nested MCE to level 4 to avoid stack overflow */ | |
ba41e1e1 | 1008 | cmpwi r10,MAX_MCE_DEPTH |
afcf0095 NP |
1009 | bgt 2f /* Check if we hit limit of 4 */ |
1010 | std r11,GPR1(r1) /* Save r1 on the stack. */ | |
1011 | std r11,0(r1) /* make stack chain pointer */ | |
1012 | mfspr r11,SPRN_SRR0 /* Save SRR0 */ | |
1013 | std r11,_NIP(r1) | |
1014 | mfspr r11,SPRN_SRR1 /* Save SRR1 */ | |
1015 | std r11,_MSR(r1) | |
1016 | mfspr r11,SPRN_DAR /* Save DAR */ | |
1017 | std r11,_DAR(r1) | |
1018 | mfspr r11,SPRN_DSISR /* Save DSISR */ | |
1019 | std r11,_DSISR(r1) | |
1020 | std r9,_CCR(r1) /* Save CR in stackframe */ | |
e13e7cd4 | 1021 | /* We don't touch AMR here, we never go to virtual mode */ |
afcf0095 NP |
1022 | /* Save r9 through r13 from EXMC save area to stack frame. */ |
1023 | EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) | |
1024 | mfmsr r11 /* get MSR value */ | |
db7d31ac | 1025 | BEGIN_FTR_SECTION |
afcf0095 | 1026 | ori r11,r11,MSR_ME /* turn on ME bit */ |
db7d31ac | 1027 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) |
afcf0095 NP |
1028 | ori r11,r11,MSR_RI /* turn on RI bit */ |
1029 | LOAD_HANDLER(r12, machine_check_handle_early) | |
1030 | 1: mtspr SPRN_SRR0,r12 | |
1031 | mtspr SPRN_SRR1,r11 | |
222f20f1 | 1032 | RFI_TO_KERNEL |
afcf0095 NP |
1033 | b . /* prevent speculative execution */ |
1034 | 2: | |
1035 | /* Stack overflow. Stay on emergency stack and panic. | |
1036 | * Keep the ME bit off while panic-ing, so that if we hit | |
1037 | * another machine check we checkstop. | |
1038 | */ | |
1039 | addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ | |
1040 | ld r11,PACAKMSR(r13) | |
1041 | LOAD_HANDLER(r12, unrecover_mce) | |
1042 | li r10,MSR_ME | |
1043 | andc r11,r11,r10 /* Turn off MSR_ME */ | |
1044 | b 1b | |
1045 | b . /* prevent speculative execution */ | |
afcf0095 NP |
1046 | |
1047 | TRAMP_REAL_BEGIN(machine_check_pSeries) | |
1048 | .globl machine_check_fwnmi | |
1049 | machine_check_fwnmi: | |
5dba1d50 | 1050 | EXCEPTION_PROLOG_0 PACA_EXMC |
a43c1590 | 1051 | BEGIN_FTR_SECTION |
db7d31ac | 1052 | b machine_check_common_early |
a43c1590 | 1053 | END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE) |
afcf0095 | 1054 | machine_check_pSeries_0: |
02a12581 | 1055 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 1, 0x200, 1, 1, 0 |
afcf0095 | 1056 | /* |
83a980f7 NP |
1057 | * MSR_RI is not enabled, because PACA_EXMC is being used, so a |
1058 | * nested machine check corrupts it. machine_check_common enables | |
1059 | * MSR_RI. | |
afcf0095 | 1060 | */ |
2d046308 | 1061 | EXCEPTION_PROLOG_2_REAL machine_check_common, EXC_STD, 0 |
afcf0095 NP |
1062 | |
1063 | TRAMP_KVM_SKIP(PACA_EXMC, 0x200) | |
1064 | ||
1065 | EXC_COMMON_BEGIN(machine_check_common) | |
1066 | /* | |
1067 | * Machine check is different because we use a different | |
1068 | * save area: PACA_EXMC instead of PACA_EXGEN. | |
1069 | */ | |
d064151f | 1070 | EXCEPTION_COMMON(PACA_EXMC, 0x200) |
afcf0095 NP |
1071 | FINISH_NAP |
1072 | RECONCILE_IRQ_STATE(r10, r11) | |
1073 | ld r3,PACA_EXMC+EX_DAR(r13) | |
1074 | lwz r4,PACA_EXMC+EX_DSISR(r13) | |
1075 | /* Enable MSR_RI when finished with PACA_EXMC */ | |
1076 | li r10,MSR_RI | |
1077 | mtmsrd r10,1 | |
1078 | std r3,_DAR(r1) | |
1079 | std r4,_DSISR(r1) | |
1080 | bl save_nvgprs | |
1081 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1082 | bl machine_check_exception | |
1083 | b ret_from_except | |
1084 | ||
1085 | #define MACHINE_CHECK_HANDLER_WINDUP \ | |
1086 | /* Clear MSR_RI before setting SRR0 and SRR1. */\ | |
fbc50063 | 1087 | li r9,0; \ |
afcf0095 | 1088 | mtmsrd r9,1; /* Clear MSR_RI */ \ |
ad73d8d4 NP |
1089 | /* Decrement paca->in_mce now RI is clear. */ \ |
1090 | lhz r12,PACA_IN_MCE(r13); \ | |
1091 | subi r12,r12,1; \ | |
1092 | sth r12,PACA_IN_MCE(r13); \ | |
391e941b | 1093 | EXCEPTION_RESTORE_REGS EXC_STD |
afcf0095 | 1094 | |
1945bc45 NP |
1095 | #ifdef CONFIG_PPC_P7_NAP |
1096 | /* | |
1097 | * This is an idle wakeup. Low level machine check has already been | |
1098 | * done. Queue the event then call the idle code to do the wake up. | |
1099 | */ | |
1100 | EXC_COMMON_BEGIN(machine_check_idle_common) | |
1101 | bl machine_check_queue_event | |
1102 | ||
1103 | /* | |
1104 | * We have not used any non-volatile GPRs here, and as a rule | |
1105 | * most exception code including machine check does not. | |
1106 | * Therefore PACA_NAPSTATELOST does not need to be set. Idle | |
1107 | * wakeup will restore volatile registers. | |
1108 | * | |
1109 | * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce. | |
1110 | * | |
1111 | * Then decrement MCE nesting after finishing with the stack. | |
1112 | */ | |
1113 | ld r3,_MSR(r1) | |
10d91611 | 1114 | ld r4,_LINK(r1) |
1945bc45 NP |
1115 | |
1116 | lhz r11,PACA_IN_MCE(r13) | |
1117 | subi r11,r11,1 | |
1118 | sth r11,PACA_IN_MCE(r13) | |
1119 | ||
10d91611 NP |
1120 | mtlr r4 |
1121 | rlwinm r10,r3,47-31,30,31 | |
1122 | cmpwi cr1,r10,2 | |
1123 | bltlr cr1 /* no state loss, return to idle caller */ | |
1124 | b idle_return_gpr_loss | |
1945bc45 | 1125 | #endif |
afcf0095 NP |
1126 | /* |
1127 | * Handle machine check early in real mode. We come here with | |
1128 | * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. | |
1129 | */ | |
1130 | EXC_COMMON_BEGIN(machine_check_handle_early) | |
1131 | std r0,GPR0(r1) /* Save r0 */ | |
1132 | EXCEPTION_PROLOG_COMMON_3(0x200) | |
1133 | bl save_nvgprs | |
1134 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1135 | bl machine_check_early | |
1136 | std r3,RESULT(r1) /* Save result */ | |
1137 | ld r12,_MSR(r1) | |
db7d31ac MS |
1138 | BEGIN_FTR_SECTION |
1139 | b 4f | |
1140 | END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE) | |
1945bc45 | 1141 | |
afcf0095 NP |
1142 | #ifdef CONFIG_PPC_P7_NAP |
1143 | /* | |
1144 | * Check if thread was in power saving mode. We come here when any | |
1145 | * of the following is true: | |
1146 | * a. thread wasn't in power saving mode | |
1147 | * b. thread was in power saving mode with no state loss, | |
1148 | * supervisor state loss or hypervisor state loss. | |
1149 | * | |
1150 | * Go back to nap/sleep/winkle mode again if (b) is true. | |
1151 | */ | |
bf66e3c4 | 1152 | BEGIN_FTR_SECTION |
1945bc45 | 1153 | rlwinm. r11,r12,47-31,30,31 |
6102c005 | 1154 | bne machine_check_idle_common |
bf66e3c4 | 1155 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
afcf0095 | 1156 | #endif |
1945bc45 | 1157 | |
afcf0095 NP |
1158 | /* |
1159 | * Check if we are coming from hypervisor userspace. If yes then we | |
1160 | * continue in host kernel in V mode to deliver the MC event. | |
1161 | */ | |
1162 | rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ | |
1163 | beq 5f | |
db7d31ac | 1164 | 4: andi. r11,r12,MSR_PR /* See if coming from user. */ |
afcf0095 NP |
1165 | bne 9f /* continue in V mode if we are. */ |
1166 | ||
1167 | 5: | |
1168 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER | |
db7d31ac | 1169 | BEGIN_FTR_SECTION |
afcf0095 NP |
1170 | /* |
1171 | * We are coming from kernel context. Check if we are coming from | |
1172 | * guest. if yes, then we can continue. We will fall through | |
1173 | * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. | |
1174 | */ | |
1175 | lbz r11,HSTATE_IN_GUEST(r13) | |
1176 | cmpwi r11,0 /* Check if coming from guest */ | |
1177 | bne 9f /* continue if we are. */ | |
db7d31ac | 1178 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) |
afcf0095 NP |
1179 | #endif |
1180 | /* | |
1181 | * At this point we are not sure about what context we come from. | |
1182 | * Queue up the MCE event and return from the interrupt. | |
1183 | * But before that, check if this is an un-recoverable exception. | |
1184 | * If yes, then stay on emergency stack and panic. | |
1185 | */ | |
1186 | andi. r11,r12,MSR_RI | |
1187 | bne 2f | |
1188 | 1: mfspr r11,SPRN_SRR0 | |
1189 | LOAD_HANDLER(r10,unrecover_mce) | |
1190 | mtspr SPRN_SRR0,r10 | |
1191 | ld r10,PACAKMSR(r13) | |
1192 | /* | |
1193 | * We are going down. But there are chances that we might get hit by | |
1194 | * another MCE during panic path and we may run into unstable state | |
1195 | * with no way out. Hence, turn ME bit off while going down, so that | |
1196 | * when another MCE is hit during panic path, system will checkstop | |
1197 | * and hypervisor will get restarted cleanly by SP. | |
1198 | */ | |
1199 | li r3,MSR_ME | |
1200 | andc r10,r10,r3 /* Turn off MSR_ME */ | |
1201 | mtspr SPRN_SRR1,r10 | |
222f20f1 | 1202 | RFI_TO_KERNEL |
afcf0095 NP |
1203 | b . |
1204 | 2: | |
1205 | /* | |
1206 | * Check if we have successfully handled/recovered from error, if not | |
1207 | * then stay on emergency stack and panic. | |
1208 | */ | |
1209 | ld r3,RESULT(r1) /* Load result */ | |
1210 | cmpdi r3,0 /* see if we handled MCE successfully */ | |
1211 | ||
1212 | beq 1b /* if !handled then panic */ | |
db7d31ac | 1213 | BEGIN_FTR_SECTION |
afcf0095 NP |
1214 | /* |
1215 | * Return from MC interrupt. | |
1216 | * Queue up the MCE event so that we can log it later, while | |
1217 | * returning from kernel or opal call. | |
1218 | */ | |
1219 | bl machine_check_queue_event | |
1220 | MACHINE_CHECK_HANDLER_WINDUP | |
222f20f1 | 1221 | RFI_TO_USER_OR_KERNEL |
db7d31ac MS |
1222 | FTR_SECTION_ELSE |
1223 | /* | |
1224 | * pSeries: Return from MC interrupt. Before that stay on emergency | |
1225 | * stack and call machine_check_exception to log the MCE event. | |
1226 | */ | |
1227 | LOAD_HANDLER(r10,mce_return) | |
1228 | mtspr SPRN_SRR0,r10 | |
1229 | ld r10,PACAKMSR(r13) | |
1230 | mtspr SPRN_SRR1,r10 | |
1231 | RFI_TO_KERNEL | |
1232 | b . | |
1233 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) | |
afcf0095 NP |
1234 | 9: |
1235 | /* Deliver the machine check to host kernel in V mode. */ | |
1236 | MACHINE_CHECK_HANDLER_WINDUP | |
5dba1d50 | 1237 | EXCEPTION_PROLOG_0 PACA_EXMC |
db7d31ac | 1238 | b machine_check_pSeries_0 |
afcf0095 NP |
1239 | |
1240 | EXC_COMMON_BEGIN(unrecover_mce) | |
1241 | /* Invoke machine_check_exception to print MCE event and panic. */ | |
1242 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1243 | bl machine_check_exception | |
1244 | /* | |
1245 | * We will not reach here. Even if we did, there is no way out. Call | |
1246 | * unrecoverable_exception and die. | |
1247 | */ | |
1248 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
1249 | bl unrecoverable_exception | |
1250 | b 1b | |
1251 | ||
a43c1590 MS |
1252 | EXC_COMMON_BEGIN(mce_return) |
1253 | /* Invoke machine_check_exception to print MCE event and return. */ | |
1254 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1255 | bl machine_check_exception | |
db7d31ac | 1256 | MACHINE_CHECK_HANDLER_WINDUP |
a43c1590 MS |
1257 | RFI_TO_KERNEL |
1258 | b . | |
0ebc4cda | 1259 | |
e779fc93 | 1260 | EXC_REAL_BEGIN(data_access, 0x300, 0x80) |
bf66e3c4 | 1261 | EXCEPTION_PROLOG_0 PACA_EXGEN |
e779fc93 NP |
1262 | b tramp_real_data_access |
1263 | EXC_REAL_END(data_access, 0x300, 0x80) | |
1264 | ||
1265 | TRAMP_REAL_BEGIN(tramp_real_data_access) | |
5312c494 NP |
1266 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x300, 1, 1, 0 |
1267 | EXCEPTION_PROLOG_2_REAL data_access_common, EXC_STD, 1 | |
e779fc93 NP |
1268 | |
1269 | EXC_VIRT_BEGIN(data_access, 0x4300, 0x80) | |
bf66e3c4 | 1270 | EXCEPTION_PROLOG_0 PACA_EXGEN |
5312c494 | 1271 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x300, 1, 1, 0 |
2d046308 | 1272 | EXCEPTION_PROLOG_2_VIRT data_access_common, EXC_STD |
e779fc93 NP |
1273 | EXC_VIRT_END(data_access, 0x4300, 0x80) |
1274 | ||
80795e6c NP |
1275 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x300) |
1276 | ||
1277 | EXC_COMMON_BEGIN(data_access_common) | |
1278 | /* | |
1279 | * Here r13 points to the paca, r9 contains the saved CR, | |
1280 | * SRR0 and SRR1 are saved in r11 and r12, | |
1281 | * r9 - r13 are saved in paca->exgen. | |
38555434 | 1282 | * EX_DAR and EX_DSISR have saved DAR/DSISR |
80795e6c | 1283 | */ |
d064151f | 1284 | EXCEPTION_COMMON(PACA_EXGEN, 0x300) |
80795e6c NP |
1285 | RECONCILE_IRQ_STATE(r10, r11) |
1286 | ld r12,_MSR(r1) | |
1287 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
1288 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
1289 | li r5,0x300 | |
1290 | std r3,_DAR(r1) | |
1291 | std r4,_DSISR(r1) | |
1292 | BEGIN_MMU_FTR_SECTION | |
1293 | b do_hash_page /* Try to handle as hpte fault */ | |
1294 | MMU_FTR_SECTION_ELSE | |
1295 | b handle_page_fault | |
1296 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
1297 | ||
0ebc4cda | 1298 | |
1a6822d1 | 1299 | EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80) |
bf66e3c4 | 1300 | EXCEPTION_PROLOG_0 PACA_EXSLB |
e779fc93 | 1301 | b tramp_real_data_access_slb |
1a6822d1 | 1302 | EXC_REAL_END(data_access_slb, 0x380, 0x80) |
0ebc4cda | 1303 | |
e779fc93 | 1304 | TRAMP_REAL_BEGIN(tramp_real_data_access_slb) |
5312c494 | 1305 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 1, 0x380, 1, 0, 0 |
bf66e3c4 | 1306 | EXCEPTION_PROLOG_2_REAL data_access_slb_common, EXC_STD, 1 |
e779fc93 | 1307 | |
1a6822d1 | 1308 | EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80) |
bf66e3c4 | 1309 | EXCEPTION_PROLOG_0 PACA_EXSLB |
5312c494 | 1310 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 0, 0x380, 1, 0, 0 |
bf66e3c4 | 1311 | EXCEPTION_PROLOG_2_VIRT data_access_slb_common, EXC_STD |
1a6822d1 | 1312 | EXC_VIRT_END(data_access_slb, 0x4380, 0x80) |
48e7b769 | 1313 | |
2b9af6e4 NP |
1314 | TRAMP_KVM_SKIP(PACA_EXSLB, 0x380) |
1315 | ||
48e7b769 | 1316 | EXC_COMMON_BEGIN(data_access_slb_common) |
d064151f | 1317 | EXCEPTION_COMMON(PACA_EXSLB, 0x380) |
48e7b769 NP |
1318 | ld r4,PACA_EXSLB+EX_DAR(r13) |
1319 | std r4,_DAR(r1) | |
1320 | addi r3,r1,STACK_FRAME_OVERHEAD | |
7100e870 NP |
1321 | BEGIN_MMU_FTR_SECTION |
1322 | /* HPT case, do SLB fault */ | |
48e7b769 NP |
1323 | bl do_slb_fault |
1324 | cmpdi r3,0 | |
1325 | bne- 1f | |
1326 | b fast_exception_return | |
1327 | 1: /* Error case */ | |
7100e870 NP |
1328 | MMU_FTR_SECTION_ELSE |
1329 | /* Radix case, access is outside page table range */ | |
1330 | li r3,-EFAULT | |
1331 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
48e7b769 NP |
1332 | std r3,RESULT(r1) |
1333 | bl save_nvgprs | |
1334 | RECONCILE_IRQ_STATE(r10, r11) | |
1335 | ld r4,_DAR(r1) | |
1336 | ld r5,RESULT(r1) | |
1337 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1338 | bl do_bad_slb_fault | |
1339 | b ret_from_except | |
1340 | ||
2b9af6e4 | 1341 | |
1a6822d1 NP |
1342 | EXC_REAL(instruction_access, 0x400, 0x80) |
1343 | EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400) | |
27ce77df NP |
1344 | TRAMP_KVM(PACA_EXGEN, 0x400) |
1345 | ||
1346 | EXC_COMMON_BEGIN(instruction_access_common) | |
d064151f | 1347 | EXCEPTION_COMMON(PACA_EXGEN, 0x400) |
27ce77df NP |
1348 | RECONCILE_IRQ_STATE(r10, r11) |
1349 | ld r12,_MSR(r1) | |
1350 | ld r3,_NIP(r1) | |
475b581f | 1351 | andis. r4,r12,DSISR_SRR1_MATCH_64S@h |
27ce77df NP |
1352 | li r5,0x400 |
1353 | std r3,_DAR(r1) | |
1354 | std r4,_DSISR(r1) | |
1355 | BEGIN_MMU_FTR_SECTION | |
1356 | b do_hash_page /* Try to handle as hpte fault */ | |
1357 | MMU_FTR_SECTION_ELSE | |
1358 | b handle_page_fault | |
1359 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
1360 | ||
0ebc4cda | 1361 | |
fc557537 NP |
1362 | __EXC_REAL(instruction_access_slb, 0x480, 0x80, PACA_EXSLB) |
1363 | __EXC_VIRT(instruction_access_slb, 0x4480, 0x80, 0x480, PACA_EXSLB) | |
48e7b769 | 1364 | TRAMP_KVM(PACA_EXSLB, 0x480) |
54be0b9c | 1365 | |
48e7b769 | 1366 | EXC_COMMON_BEGIN(instruction_access_slb_common) |
d064151f | 1367 | EXCEPTION_COMMON(PACA_EXSLB, 0x480) |
48e7b769 NP |
1368 | ld r4,_NIP(r1) |
1369 | addi r3,r1,STACK_FRAME_OVERHEAD | |
7100e870 NP |
1370 | BEGIN_MMU_FTR_SECTION |
1371 | /* HPT case, do SLB fault */ | |
48e7b769 NP |
1372 | bl do_slb_fault |
1373 | cmpdi r3,0 | |
1374 | bne- 1f | |
1375 | b fast_exception_return | |
1376 | 1: /* Error case */ | |
7100e870 NP |
1377 | MMU_FTR_SECTION_ELSE |
1378 | /* Radix case, access is outside page table range */ | |
1379 | li r3,-EFAULT | |
1380 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
48e7b769 | 1381 | std r3,RESULT(r1) |
8d04631a | 1382 | bl save_nvgprs |
8d04631a | 1383 | RECONCILE_IRQ_STATE(r10, r11) |
48e7b769 NP |
1384 | ld r4,_NIP(r1) |
1385 | ld r5,RESULT(r1) | |
1386 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1387 | bl do_bad_slb_fault | |
8d04631a NP |
1388 | b ret_from_except |
1389 | ||
48e7b769 | 1390 | |
1a6822d1 | 1391 | EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100) |
80bd9177 | 1392 | EXCEPTION_PROLOG_0 PACA_EXGEN |
bf66e3c4 | 1393 | BEGIN_FTR_SECTION |
5312c494 | 1394 | EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0x500, 0, 0, IRQS_DISABLED |
bf66e3c4 NP |
1395 | EXCEPTION_PROLOG_2_REAL hardware_interrupt_common, EXC_HV, 1 |
1396 | FTR_SECTION_ELSE | |
5312c494 | 1397 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x500, 0, 0, IRQS_DISABLED |
bf66e3c4 NP |
1398 | EXCEPTION_PROLOG_2_REAL hardware_interrupt_common, EXC_STD, 1 |
1399 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) | |
1a6822d1 | 1400 | EXC_REAL_END(hardware_interrupt, 0x500, 0x100) |
da2bc464 | 1401 | |
1a6822d1 | 1402 | EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100) |
80bd9177 | 1403 | EXCEPTION_PROLOG_0 PACA_EXGEN |
bf66e3c4 | 1404 | BEGIN_FTR_SECTION |
5312c494 | 1405 | EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0x500, 0, 0, IRQS_DISABLED |
bf66e3c4 NP |
1406 | EXCEPTION_PROLOG_2_VIRT hardware_interrupt_common, EXC_HV |
1407 | FTR_SECTION_ELSE | |
5312c494 | 1408 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x500, 0, 0, IRQS_DISABLED |
bf66e3c4 NP |
1409 | EXCEPTION_PROLOG_2_VIRT hardware_interrupt_common, EXC_STD |
1410 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) | |
1a6822d1 | 1411 | EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100) |
c138e588 | 1412 | |
7ede5317 NP |
1413 | TRAMP_KVM(PACA_EXGEN, 0x500) |
1414 | TRAMP_KVM_HV(PACA_EXGEN, 0x500) | |
c138e588 NP |
1415 | EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) |
1416 | ||
1417 | ||
e779fc93 | 1418 | EXC_REAL_BEGIN(alignment, 0x600, 0x100) |
bf66e3c4 | 1419 | EXCEPTION_PROLOG_0 PACA_EXGEN |
5312c494 | 1420 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x600, 1, 1, 0 |
bf66e3c4 | 1421 | EXCEPTION_PROLOG_2_REAL alignment_common, EXC_STD, 1 |
e779fc93 NP |
1422 | EXC_REAL_END(alignment, 0x600, 0x100) |
1423 | ||
1424 | EXC_VIRT_BEGIN(alignment, 0x4600, 0x100) | |
bf66e3c4 | 1425 | EXCEPTION_PROLOG_0 PACA_EXGEN |
5312c494 | 1426 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x600, 1, 1, 0 |
bf66e3c4 | 1427 | EXCEPTION_PROLOG_2_VIRT alignment_common, EXC_STD |
e779fc93 NP |
1428 | EXC_VIRT_END(alignment, 0x4600, 0x100) |
1429 | ||
da2bc464 | 1430 | TRAMP_KVM(PACA_EXGEN, 0x600) |
f9aa6714 | 1431 | EXC_COMMON_BEGIN(alignment_common) |
d064151f | 1432 | EXCEPTION_COMMON(PACA_EXGEN, 0x600) |
f9aa6714 NP |
1433 | ld r3,PACA_EXGEN+EX_DAR(r13) |
1434 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
1435 | std r3,_DAR(r1) | |
1436 | std r4,_DSISR(r1) | |
1437 | bl save_nvgprs | |
1438 | RECONCILE_IRQ_STATE(r10, r11) | |
1439 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1440 | bl alignment_exception | |
1441 | b ret_from_except | |
1442 | ||
da2bc464 | 1443 | |
1a6822d1 NP |
1444 | EXC_REAL(program_check, 0x700, 0x100) |
1445 | EXC_VIRT(program_check, 0x4700, 0x100, 0x700) | |
da2bc464 | 1446 | TRAMP_KVM(PACA_EXGEN, 0x700) |
11e87346 | 1447 | EXC_COMMON_BEGIN(program_check_common) |
265e60a1 CB |
1448 | /* |
1449 | * It's possible to receive a TM Bad Thing type program check with | |
1450 | * userspace register values (in particular r1), but with SRR1 reporting | |
1451 | * that we came from the kernel. Normally that would confuse the bad | |
1452 | * stack logic, and we would report a bad kernel stack pointer. Instead | |
1453 | * we switch to the emergency stack if we're taking a TM Bad Thing from | |
1454 | * the kernel. | |
1455 | */ | |
0a882e28 NP |
1456 | |
1457 | andi. r10,r12,MSR_PR | |
1458 | bne 2f /* If userspace, go normal path */ | |
1459 | ||
1460 | andis. r10,r12,(SRR1_PROGTM)@h | |
1461 | bne 1f /* If TM, emergency */ | |
1462 | ||
1463 | cmpdi r1,-INT_FRAME_SIZE /* check if r1 is in userspace */ | |
1464 | blt 2f /* normal path if not */ | |
1465 | ||
1466 | /* Use the emergency stack */ | |
1467 | 1: andi. r10,r12,MSR_PR /* Set CR0 correctly for label */ | |
265e60a1 CB |
1468 | /* 3 in EXCEPTION_PROLOG_COMMON */ |
1469 | mr r10,r1 /* Save r1 */ | |
1470 | ld r1,PACAEMERGSP(r13) /* Use emergency stack */ | |
1471 | subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
1472 | b 3f /* Jump into the macro !! */ | |
0a882e28 NP |
1473 | 2: |
1474 | EXCEPTION_COMMON(PACA_EXGEN, 0x700) | |
11e87346 NP |
1475 | bl save_nvgprs |
1476 | RECONCILE_IRQ_STATE(r10, r11) | |
1477 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1478 | bl program_check_exception | |
1479 | b ret_from_except | |
1480 | ||
b01c8b54 | 1481 | |
1a6822d1 NP |
1482 | EXC_REAL(fp_unavailable, 0x800, 0x100) |
1483 | EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800) | |
da2bc464 | 1484 | TRAMP_KVM(PACA_EXGEN, 0x800) |
c78d9b97 | 1485 | EXC_COMMON_BEGIN(fp_unavailable_common) |
d064151f | 1486 | EXCEPTION_COMMON(PACA_EXGEN, 0x800) |
c78d9b97 NP |
1487 | bne 1f /* if from user, just load it up */ |
1488 | bl save_nvgprs | |
1489 | RECONCILE_IRQ_STATE(r10, r11) | |
1490 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1491 | bl kernel_fp_unavailable_exception | |
1492 | BUG_OPCODE | |
1493 | 1: | |
1494 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1495 | BEGIN_FTR_SECTION | |
1496 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1497 | * transaction), go do TM stuff | |
1498 | */ | |
1499 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1500 | bne- 2f | |
1501 | END_FTR_SECTION_IFSET(CPU_FTR_TM) | |
1502 | #endif | |
1503 | bl load_up_fpu | |
1504 | b fast_exception_return | |
1505 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1506 | 2: /* User process was in a transaction */ | |
1507 | bl save_nvgprs | |
1508 | RECONCILE_IRQ_STATE(r10, r11) | |
1509 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1510 | bl fp_unavailable_tm | |
1511 | b ret_from_except | |
1512 | #endif | |
1513 | ||
a5d4f3ad | 1514 | |
a048a07d | 1515 | EXC_REAL_OOL_MASKABLE(decrementer, 0x900, 0x80, IRQS_DISABLED) |
f14e953b | 1516 | EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900, IRQS_DISABLED) |
39c0da57 NP |
1517 | TRAMP_KVM(PACA_EXGEN, 0x900) |
1518 | EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) | |
1519 | ||
a485c709 | 1520 | |
1a6822d1 NP |
1521 | EXC_REAL_HV(hdecrementer, 0x980, 0x80) |
1522 | EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980) | |
facc6d74 NP |
1523 | TRAMP_KVM_HV(PACA_EXGEN, 0x980) |
1524 | EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) | |
1525 | ||
a5d4f3ad | 1526 | |
f14e953b MS |
1527 | EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100, IRQS_DISABLED) |
1528 | EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00, IRQS_DISABLED) | |
da2bc464 | 1529 | TRAMP_KVM(PACA_EXGEN, 0xa00) |
ca243163 NP |
1530 | #ifdef CONFIG_PPC_DOORBELL |
1531 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) | |
1532 | #else | |
1533 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) | |
1534 | #endif | |
1535 | ||
0ebc4cda | 1536 | |
1a6822d1 NP |
1537 | EXC_REAL(trap_0b, 0xb00, 0x100) |
1538 | EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00) | |
da2bc464 | 1539 | TRAMP_KVM(PACA_EXGEN, 0xb00) |
341215dc NP |
1540 | EXC_COMMON(trap_0b_common, 0xb00, unknown_exception) |
1541 | ||
acd7d8ce NP |
1542 | /* |
1543 | * system call / hypercall (0xc00, 0x4c00) | |
1544 | * | |
1545 | * The system call exception is invoked with "sc 0" and does not alter HV bit. | |
1546 | * There is support for kernel code to invoke system calls but there are no | |
1547 | * in-tree users. | |
1548 | * | |
1549 | * The hypercall is invoked with "sc 1" and sets HV=1. | |
1550 | * | |
1551 | * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to | |
1552 | * 0x4c00 virtual mode. | |
1553 | * | |
1554 | * Call convention: | |
1555 | * | |
1556 | * syscall register convention is in Documentation/powerpc/syscall64-abi.txt | |
1557 | * | |
1558 | * For hypercalls, the register convention is as follows: | |
1559 | * r0 volatile | |
1560 | * r1-2 nonvolatile | |
1561 | * r3 volatile parameter and return value for status | |
1562 | * r4-r10 volatile input and output value | |
1563 | * r11 volatile hypercall number and output value | |
76fc0cfc | 1564 | * r12 volatile input and output value |
acd7d8ce NP |
1565 | * r13-r31 nonvolatile |
1566 | * LR nonvolatile | |
1567 | * CTR volatile | |
1568 | * XER volatile | |
1569 | * CR0-1 CR5-7 volatile | |
1570 | * CR2-4 nonvolatile | |
1571 | * Other registers nonvolatile | |
1572 | * | |
1573 | * The intersection of volatile registers that don't contain possible | |
76fc0cfc NP |
1574 | * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry |
1575 | * without saving, though xer is not a good idea to use, as hardware may | |
1576 | * interpret some bits so it may be costly to change them. | |
acd7d8ce | 1577 | */ |
1b4d4a79 | 1578 | .macro SYSTEM_CALL virt |
bc355125 | 1579 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
acd7d8ce NP |
1580 | /* |
1581 | * There is a little bit of juggling to get syscall and hcall | |
76fc0cfc NP |
1582 | * working well. Save r13 in ctr to avoid using SPRG scratch |
1583 | * register. | |
acd7d8ce NP |
1584 | * |
1585 | * Userspace syscalls have already saved the PPR, hcalls must save | |
1586 | * it before setting HMT_MEDIUM. | |
1587 | */ | |
1b4d4a79 NP |
1588 | mtctr r13 |
1589 | GET_PACA(r13) | |
1590 | std r10,PACA_EXGEN+EX_R10(r13) | |
1591 | INTERRUPT_TO_KERNEL | |
1592 | KVMTEST EXC_STD 0xc00 /* uses r10, branch to do_kvm_0xc00_system_call */ | |
1b4d4a79 | 1593 | mfctr r9 |
bc355125 | 1594 | #else |
1b4d4a79 NP |
1595 | mr r9,r13 |
1596 | GET_PACA(r13) | |
1597 | INTERRUPT_TO_KERNEL | |
bc355125 | 1598 | #endif |
d807ad37 | 1599 | |
727f1361 | 1600 | #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH |
1b4d4a79 NP |
1601 | BEGIN_FTR_SECTION |
1602 | cmpdi r0,0x1ebe | |
1603 | beq- 1f | |
1604 | END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) | |
1605 | #endif | |
d807ad37 | 1606 | |
b0b2a93d | 1607 | /* We reach here with PACA in r13, r13 in r9. */ |
1b4d4a79 NP |
1608 | mfspr r11,SPRN_SRR0 |
1609 | mfspr r12,SPRN_SRR1 | |
b0b2a93d NP |
1610 | |
1611 | HMT_MEDIUM | |
1612 | ||
1613 | .if ! \virt | |
1b4d4a79 NP |
1614 | __LOAD_HANDLER(r10, system_call_common) |
1615 | mtspr SPRN_SRR0,r10 | |
1616 | ld r10,PACAKMSR(r13) | |
1617 | mtspr SPRN_SRR1,r10 | |
1618 | RFI_TO_KERNEL | |
1619 | b . /* prevent speculative execution */ | |
1620 | .else | |
b0b2a93d NP |
1621 | li r10,MSR_RI |
1622 | mtmsrd r10,1 /* Set RI (EE=0) */ | |
1b4d4a79 | 1623 | #ifdef CONFIG_RELOCATABLE |
1b4d4a79 NP |
1624 | __LOAD_HANDLER(r10, system_call_common) |
1625 | mtctr r10 | |
1b4d4a79 | 1626 | bctr |
d807ad37 | 1627 | #else |
1b4d4a79 NP |
1628 | b system_call_common |
1629 | #endif | |
1630 | .endif | |
1631 | ||
1632 | #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH | |
1633 | /* Fast LE/BE switch system call */ | |
1634 | 1: mfspr r12,SPRN_SRR1 | |
1635 | xori r12,r12,MSR_LE | |
1636 | mtspr SPRN_SRR1,r12 | |
1637 | mr r13,r9 | |
1638 | RFI_TO_USER /* return to userspace */ | |
1639 | b . /* prevent speculative execution */ | |
d807ad37 | 1640 | #endif |
1b4d4a79 | 1641 | .endm |
d807ad37 | 1642 | |
1a6822d1 | 1643 | EXC_REAL_BEGIN(system_call, 0xc00, 0x100) |
1b4d4a79 | 1644 | SYSTEM_CALL 0 |
1a6822d1 | 1645 | EXC_REAL_END(system_call, 0xc00, 0x100) |
da2bc464 | 1646 | |
1a6822d1 | 1647 | EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100) |
1b4d4a79 | 1648 | SYSTEM_CALL 1 |
1a6822d1 | 1649 | EXC_VIRT_END(system_call, 0x4c00, 0x100) |
d807ad37 | 1650 | |
acd7d8ce NP |
1651 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
1652 | /* | |
1653 | * This is a hcall, so register convention is as above, with these | |
1654 | * differences: | |
1655 | * r13 = PACA | |
76fc0cfc NP |
1656 | * ctr = orig r13 |
1657 | * orig r10 saved in PACA | |
acd7d8ce NP |
1658 | */ |
1659 | TRAMP_KVM_BEGIN(do_kvm_0xc00) | |
1660 | /* | |
1661 | * Save the PPR (on systems that support it) before changing to | |
1662 | * HMT_MEDIUM. That allows the KVM code to save that value into the | |
1663 | * guest state (it is the guest's PPR value). | |
1664 | */ | |
76fc0cfc | 1665 | OPT_GET_SPR(r10, SPRN_PPR, CPU_FTR_HAS_PPR) |
acd7d8ce | 1666 | HMT_MEDIUM |
76fc0cfc | 1667 | OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r10, CPU_FTR_HAS_PPR) |
acd7d8ce | 1668 | mfctr r10 |
76fc0cfc | 1669 | SET_SCRATCH0(r10) |
acd7d8ce NP |
1670 | std r9,PACA_EXGEN+EX_R9(r13) |
1671 | mfcr r9 | |
17bdc064 | 1672 | KVM_HANDLER PACA_EXGEN, EXC_STD, 0xc00, 0 |
acd7d8ce | 1673 | #endif |
da2bc464 | 1674 | |
d807ad37 | 1675 | |
1a6822d1 NP |
1676 | EXC_REAL(single_step, 0xd00, 0x100) |
1677 | EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00) | |
da2bc464 | 1678 | TRAMP_KVM(PACA_EXGEN, 0xd00) |
bc6675c6 | 1679 | EXC_COMMON(single_step_common, 0xd00, single_step_exception) |
b01c8b54 | 1680 | |
1a6822d1 | 1681 | EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20) |
da0e7e62 | 1682 | EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00) |
f5c32c1d NP |
1683 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) |
1684 | EXC_COMMON_BEGIN(h_data_storage_common) | |
1685 | mfspr r10,SPRN_HDAR | |
1686 | std r10,PACA_EXGEN+EX_DAR(r13) | |
1687 | mfspr r10,SPRN_HDSISR | |
1688 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
d064151f | 1689 | EXCEPTION_COMMON(PACA_EXGEN, 0xe00) |
f5c32c1d NP |
1690 | bl save_nvgprs |
1691 | RECONCILE_IRQ_STATE(r10, r11) | |
1692 | addi r3,r1,STACK_FRAME_OVERHEAD | |
d7b45615 SJS |
1693 | BEGIN_MMU_FTR_SECTION |
1694 | ld r4,PACA_EXGEN+EX_DAR(r13) | |
1695 | lwz r5,PACA_EXGEN+EX_DSISR(r13) | |
1696 | std r4,_DAR(r1) | |
1697 | std r5,_DSISR(r1) | |
1698 | li r5,SIGSEGV | |
1699 | bl bad_page_fault | |
1700 | MMU_FTR_SECTION_ELSE | |
f5c32c1d | 1701 | bl unknown_exception |
d7b45615 | 1702 | ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX) |
f5c32c1d | 1703 | b ret_from_except |
f5c32c1d | 1704 | |
1707dd16 | 1705 | |
1a6822d1 | 1706 | EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20) |
da0e7e62 | 1707 | EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20) |
82517cab NP |
1708 | TRAMP_KVM_HV(PACA_EXGEN, 0xe20) |
1709 | EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) | |
1710 | ||
1707dd16 | 1711 | |
1a6822d1 NP |
1712 | EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20) |
1713 | EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40) | |
031b4026 NP |
1714 | TRAMP_KVM_HV(PACA_EXGEN, 0xe40) |
1715 | EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) | |
1716 | ||
1707dd16 | 1717 | |
e0319829 NP |
1718 | /* |
1719 | * hmi_exception trampoline is a special case. It jumps to hmi_exception_early | |
1720 | * first, and then eventaully from there to the trampoline to get into virtual | |
1721 | * mode. | |
1722 | */ | |
1a6822d1 | 1723 | __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early) |
f14e953b | 1724 | __TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60, IRQS_DISABLED) |
1a6822d1 | 1725 | EXC_VIRT_NONE(0x4e60, 0x20) |
62f9b03b NP |
1726 | TRAMP_KVM_HV(PACA_EXGEN, 0xe60) |
1727 | TRAMP_REAL_BEGIN(hmi_exception_early) | |
5312c494 | 1728 | EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0xe60, 0, 0, 0 |
a4087a4d NP |
1729 | mr r10,r1 /* Save r1 */ |
1730 | ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */ | |
62f9b03b | 1731 | subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ |
62f9b03b | 1732 | mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ |
a4087a4d NP |
1733 | mfspr r12,SPRN_HSRR1 /* Save HSRR1 */ |
1734 | EXCEPTION_PROLOG_COMMON_1() | |
890274c2 | 1735 | /* We don't touch AMR here, we never go to virtual mode */ |
62f9b03b NP |
1736 | EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) |
1737 | EXCEPTION_PROLOG_COMMON_3(0xe60) | |
1738 | addi r3,r1,STACK_FRAME_OVERHEAD | |
505a314f | 1739 | BRANCH_LINK_TO_FAR(DOTSYM(hmi_exception_realmode)) /* Function call ABI */ |
5080332c | 1740 | cmpdi cr0,r3,0 |
67d4160a | 1741 | bne 1f |
5080332c | 1742 | |
391e941b | 1743 | EXCEPTION_RESTORE_REGS EXC_HV |
222f20f1 | 1744 | HRFI_TO_USER_OR_KERNEL |
5080332c | 1745 | |
67d4160a | 1746 | 1: |
62f9b03b NP |
1747 | /* |
1748 | * Go to virtual mode and pull the HMI event information from | |
1749 | * firmware. | |
1750 | */ | |
391e941b | 1751 | EXCEPTION_RESTORE_REGS EXC_HV |
5dba1d50 | 1752 | EXCEPTION_PROLOG_0 PACA_EXGEN |
62f9b03b NP |
1753 | b tramp_real_hmi_exception |
1754 | ||
5080332c | 1755 | EXC_COMMON_BEGIN(hmi_exception_common) |
47169fba NP |
1756 | EXCEPTION_COMMON(PACA_EXGEN, 0xe60) |
1757 | FINISH_NAP | |
1758 | bl save_nvgprs | |
1759 | RECONCILE_IRQ_STATE(r10, r11) | |
1760 | RUNLATCH_ON | |
c06075f3 NP |
1761 | addi r3,r1,STACK_FRAME_OVERHEAD |
1762 | bl handle_hmi_exception | |
1763 | b ret_from_except | |
1707dd16 | 1764 | |
f14e953b MS |
1765 | EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20, IRQS_DISABLED) |
1766 | EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80, IRQS_DISABLED) | |
9bcb81bf NP |
1767 | TRAMP_KVM_HV(PACA_EXGEN, 0xe80) |
1768 | #ifdef CONFIG_PPC_DOORBELL | |
1769 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) | |
1770 | #else | |
1771 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) | |
1772 | #endif | |
1773 | ||
0ebc4cda | 1774 | |
f14e953b MS |
1775 | EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20, IRQS_DISABLED) |
1776 | EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0, IRQS_DISABLED) | |
74408776 NP |
1777 | TRAMP_KVM_HV(PACA_EXGEN, 0xea0) |
1778 | EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) | |
1779 | ||
9baaef0a | 1780 | |
1a6822d1 NP |
1781 | EXC_REAL_NONE(0xec0, 0x20) |
1782 | EXC_VIRT_NONE(0x4ec0, 0x20) | |
1783 | EXC_REAL_NONE(0xee0, 0x20) | |
1784 | EXC_VIRT_NONE(0x4ee0, 0x20) | |
bda7fea2 | 1785 | |
0ebc4cda | 1786 | |
f442d004 MS |
1787 | EXC_REAL_OOL_MASKABLE(performance_monitor, 0xf00, 0x20, IRQS_PMI_DISABLED) |
1788 | EXC_VIRT_OOL_MASKABLE(performance_monitor, 0x4f00, 0x20, 0xf00, IRQS_PMI_DISABLED) | |
b1c7f150 NP |
1789 | TRAMP_KVM(PACA_EXGEN, 0xf00) |
1790 | EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) | |
1791 | ||
0ebc4cda | 1792 | |
1a6822d1 NP |
1793 | EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20) |
1794 | EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20) | |
d1a0ca9c NP |
1795 | TRAMP_KVM(PACA_EXGEN, 0xf20) |
1796 | EXC_COMMON_BEGIN(altivec_unavailable_common) | |
d064151f | 1797 | EXCEPTION_COMMON(PACA_EXGEN, 0xf20) |
d1a0ca9c NP |
1798 | #ifdef CONFIG_ALTIVEC |
1799 | BEGIN_FTR_SECTION | |
1800 | beq 1f | |
1801 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1802 | BEGIN_FTR_SECTION_NESTED(69) | |
1803 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1804 | * transaction), go do TM stuff | |
1805 | */ | |
1806 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1807 | bne- 2f | |
1808 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1809 | #endif | |
1810 | bl load_up_altivec | |
1811 | b fast_exception_return | |
1812 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1813 | 2: /* User process was in a transaction */ | |
1814 | bl save_nvgprs | |
1815 | RECONCILE_IRQ_STATE(r10, r11) | |
1816 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1817 | bl altivec_unavailable_tm | |
1818 | b ret_from_except | |
1819 | #endif | |
1820 | 1: | |
1821 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1822 | #endif | |
1823 | bl save_nvgprs | |
1824 | RECONCILE_IRQ_STATE(r10, r11) | |
1825 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1826 | bl altivec_unavailable_exception | |
1827 | b ret_from_except | |
1828 | ||
0ebc4cda | 1829 | |
1a6822d1 NP |
1830 | EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20) |
1831 | EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40) | |
792cbddd NP |
1832 | TRAMP_KVM(PACA_EXGEN, 0xf40) |
1833 | EXC_COMMON_BEGIN(vsx_unavailable_common) | |
d064151f | 1834 | EXCEPTION_COMMON(PACA_EXGEN, 0xf40) |
792cbddd NP |
1835 | #ifdef CONFIG_VSX |
1836 | BEGIN_FTR_SECTION | |
1837 | beq 1f | |
1838 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1839 | BEGIN_FTR_SECTION_NESTED(69) | |
1840 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1841 | * transaction), go do TM stuff | |
1842 | */ | |
1843 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1844 | bne- 2f | |
1845 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1846 | #endif | |
1847 | b load_up_vsx | |
1848 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1849 | 2: /* User process was in a transaction */ | |
1850 | bl save_nvgprs | |
1851 | RECONCILE_IRQ_STATE(r10, r11) | |
1852 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1853 | bl vsx_unavailable_tm | |
1854 | b ret_from_except | |
1855 | #endif | |
1856 | 1: | |
1857 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
1858 | #endif | |
1859 | bl save_nvgprs | |
1860 | RECONCILE_IRQ_STATE(r10, r11) | |
1861 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1862 | bl vsx_unavailable_exception | |
1863 | b ret_from_except | |
1864 | ||
da2bc464 | 1865 | |
1a6822d1 NP |
1866 | EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20) |
1867 | EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60) | |
1134713c NP |
1868 | TRAMP_KVM(PACA_EXGEN, 0xf60) |
1869 | EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) | |
1870 | ||
da2bc464 | 1871 | |
1a6822d1 NP |
1872 | EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20) |
1873 | EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80) | |
14b0072c NP |
1874 | TRAMP_KVM_HV(PACA_EXGEN, 0xf80) |
1875 | EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) | |
1876 | ||
da2bc464 | 1877 | |
1a6822d1 NP |
1878 | EXC_REAL_NONE(0xfa0, 0x20) |
1879 | EXC_VIRT_NONE(0x4fa0, 0x20) | |
1880 | EXC_REAL_NONE(0xfc0, 0x20) | |
1881 | EXC_VIRT_NONE(0x4fc0, 0x20) | |
1882 | EXC_REAL_NONE(0xfe0, 0x20) | |
1883 | EXC_VIRT_NONE(0x4fe0, 0x20) | |
1884 | ||
1885 | EXC_REAL_NONE(0x1000, 0x100) | |
1886 | EXC_VIRT_NONE(0x5000, 0x100) | |
1887 | EXC_REAL_NONE(0x1100, 0x100) | |
1888 | EXC_VIRT_NONE(0x5100, 0x100) | |
d0c0c9a1 | 1889 | |
0ebc4cda | 1890 | #ifdef CONFIG_CBE_RAS |
1a6822d1 NP |
1891 | EXC_REAL_HV(cbe_system_error, 0x1200, 0x100) |
1892 | EXC_VIRT_NONE(0x5200, 0x100) | |
da2bc464 | 1893 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) |
ff1b3206 | 1894 | EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) |
da2bc464 | 1895 | #else /* CONFIG_CBE_RAS */ |
1a6822d1 NP |
1896 | EXC_REAL_NONE(0x1200, 0x100) |
1897 | EXC_VIRT_NONE(0x5200, 0x100) | |
da2bc464 | 1898 | #endif |
b01c8b54 | 1899 | |
ff1b3206 | 1900 | |
1a6822d1 NP |
1901 | EXC_REAL(instruction_breakpoint, 0x1300, 0x100) |
1902 | EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300) | |
da2bc464 | 1903 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) |
4e96dbbf NP |
1904 | EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) |
1905 | ||
1a6822d1 NP |
1906 | EXC_REAL_NONE(0x1400, 0x100) |
1907 | EXC_VIRT_NONE(0x5400, 0x100) | |
da2bc464 | 1908 | |
1a6822d1 | 1909 | EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100) |
5dba1d50 | 1910 | EXCEPTION_PROLOG_0 PACA_EXGEN |
5312c494 | 1911 | EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 0, 0x1500, 0, 0, 0 |
b92a66a6 MN |
1912 | |
1913 | #ifdef CONFIG_PPC_DENORMALISATION | |
1914 | mfspr r10,SPRN_HSRR1 | |
afcf0095 | 1915 | andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ |
afcf0095 NP |
1916 | bne+ denorm_assist |
1917 | #endif | |
1e9b4507 | 1918 | |
a7c1ca19 | 1919 | KVMTEST EXC_HV 0x1500 |
2d046308 | 1920 | EXCEPTION_PROLOG_2_REAL denorm_common, EXC_HV, 1 |
1a6822d1 | 1921 | EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100) |
a74599a5 | 1922 | |
d7e89849 | 1923 | #ifdef CONFIG_PPC_DENORMALISATION |
1a6822d1 | 1924 | EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100) |
d7e89849 | 1925 | b exc_real_0x1500_denorm_exception_hv |
1a6822d1 | 1926 | EXC_VIRT_END(denorm_exception, 0x5500, 0x100) |
d7e89849 | 1927 | #else |
1a6822d1 | 1928 | EXC_VIRT_NONE(0x5500, 0x100) |
afcf0095 NP |
1929 | #endif |
1930 | ||
4bb3c7a0 | 1931 | TRAMP_KVM_HV(PACA_EXGEN, 0x1500) |
b01c8b54 | 1932 | |
b92a66a6 | 1933 | #ifdef CONFIG_PPC_DENORMALISATION |
da2bc464 | 1934 | TRAMP_REAL_BEGIN(denorm_assist) |
b92a66a6 MN |
1935 | BEGIN_FTR_SECTION |
1936 | /* | |
1937 | * To denormalise we need to move a copy of the register to itself. | |
1938 | * For POWER6 do that here for all FP regs. | |
1939 | */ | |
1940 | mfmsr r10 | |
1941 | ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) | |
1942 | xori r10,r10,(MSR_FE0|MSR_FE1) | |
1943 | mtmsrd r10 | |
1944 | sync | |
d7c67fb1 | 1945 | |
f3c8b6c6 NP |
1946 | .Lreg=0 |
1947 | .rept 32 | |
1948 | fmr .Lreg,.Lreg | |
1949 | .Lreg=.Lreg+1 | |
1950 | .endr | |
d7c67fb1 | 1951 | |
b92a66a6 MN |
1952 | FTR_SECTION_ELSE |
1953 | /* | |
1954 | * To denormalise we need to move a copy of the register to itself. | |
1955 | * For POWER7 do that here for the first 32 VSX registers only. | |
1956 | */ | |
1957 | mfmsr r10 | |
1958 | oris r10,r10,MSR_VSX@h | |
1959 | mtmsrd r10 | |
1960 | sync | |
d7c67fb1 | 1961 | |
f3c8b6c6 NP |
1962 | .Lreg=0 |
1963 | .rept 32 | |
1964 | XVCPSGNDP(.Lreg,.Lreg,.Lreg) | |
1965 | .Lreg=.Lreg+1 | |
1966 | .endr | |
d7c67fb1 | 1967 | |
b92a66a6 | 1968 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) |
fb0fce3e MN |
1969 | |
1970 | BEGIN_FTR_SECTION | |
1971 | b denorm_done | |
1972 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
1973 | /* | |
1974 | * To denormalise we need to move a copy of the register to itself. | |
1975 | * For POWER8 we need to do that for all 64 VSX registers | |
1976 | */ | |
f3c8b6c6 NP |
1977 | .Lreg=32 |
1978 | .rept 32 | |
1979 | XVCPSGNDP(.Lreg,.Lreg,.Lreg) | |
1980 | .Lreg=.Lreg+1 | |
1981 | .endr | |
1982 | ||
fb0fce3e | 1983 | denorm_done: |
f14040bc MN |
1984 | mfspr r11,SPRN_HSRR0 |
1985 | subi r11,r11,4 | |
b92a66a6 MN |
1986 | mtspr SPRN_HSRR0,r11 |
1987 | mtcrf 0x80,r9 | |
1988 | ld r9,PACA_EXGEN+EX_R9(r13) | |
44e9309f | 1989 | RESTORE_PPR_PACA(PACA_EXGEN, r10) |
630573c1 PM |
1990 | BEGIN_FTR_SECTION |
1991 | ld r10,PACA_EXGEN+EX_CFAR(r13) | |
1992 | mtspr SPRN_CFAR,r10 | |
1993 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
b92a66a6 MN |
1994 | ld r10,PACA_EXGEN+EX_R10(r13) |
1995 | ld r11,PACA_EXGEN+EX_R11(r13) | |
1996 | ld r12,PACA_EXGEN+EX_R12(r13) | |
1997 | ld r13,PACA_EXGEN+EX_R13(r13) | |
222f20f1 | 1998 | HRFI_TO_UNKNOWN |
b92a66a6 MN |
1999 | b . |
2000 | #endif | |
2001 | ||
872e2ae4 | 2002 | EXC_COMMON(denorm_common, 0x1500, unknown_exception) |
d7e89849 NP |
2003 | |
2004 | ||
2005 | #ifdef CONFIG_CBE_RAS | |
1a6822d1 NP |
2006 | EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100) |
2007 | EXC_VIRT_NONE(0x5600, 0x100) | |
d7e89849 | 2008 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) |
69a79344 | 2009 | EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) |
d7e89849 | 2010 | #else /* CONFIG_CBE_RAS */ |
1a6822d1 NP |
2011 | EXC_REAL_NONE(0x1600, 0x100) |
2012 | EXC_VIRT_NONE(0x5600, 0x100) | |
d7e89849 NP |
2013 | #endif |
2014 | ||
69a79344 | 2015 | |
1a6822d1 NP |
2016 | EXC_REAL(altivec_assist, 0x1700, 0x100) |
2017 | EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700) | |
d7e89849 | 2018 | TRAMP_KVM(PACA_EXGEN, 0x1700) |
b51c079e NP |
2019 | #ifdef CONFIG_ALTIVEC |
2020 | EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) | |
2021 | #else | |
2022 | EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) | |
2023 | #endif | |
2024 | ||
d7e89849 NP |
2025 | |
2026 | #ifdef CONFIG_CBE_RAS | |
1a6822d1 NP |
2027 | EXC_REAL_HV(cbe_thermal, 0x1800, 0x100) |
2028 | EXC_VIRT_NONE(0x5800, 0x100) | |
d7e89849 | 2029 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) |
3965f8ab | 2030 | EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) |
d7e89849 | 2031 | #else /* CONFIG_CBE_RAS */ |
1a6822d1 NP |
2032 | EXC_REAL_NONE(0x1800, 0x100) |
2033 | EXC_VIRT_NONE(0x5800, 0x100) | |
d7e89849 NP |
2034 | #endif |
2035 | ||
75eb767e | 2036 | #ifdef CONFIG_PPC_WATCHDOG |
2104180a NP |
2037 | |
2038 | #define MASKED_DEC_HANDLER_LABEL 3f | |
2039 | ||
2040 | #define MASKED_DEC_HANDLER(_H) \ | |
2041 | 3: /* soft-nmi */ \ | |
2042 | std r12,PACA_EXGEN+EX_R12(r13); \ | |
2043 | GET_SCRATCH0(r10); \ | |
2044 | std r10,PACA_EXGEN+EX_R13(r13); \ | |
2d046308 | 2045 | EXCEPTION_PROLOG_2_REAL soft_nmi_common, _H, 1 |
2104180a | 2046 | |
cc491f1d NP |
2047 | /* |
2048 | * Branch to soft_nmi_interrupt using the emergency stack. The emergency | |
2049 | * stack is one that is usable by maskable interrupts so long as MSR_EE | |
2050 | * remains off. It is used for recovery when something has corrupted the | |
2051 | * normal kernel stack, for example. The "soft NMI" must not use the process | |
2052 | * stack because we want irq disabled sections to avoid touching the stack | |
2053 | * at all (other than PMU interrupts), so use the emergency stack for this, | |
2054 | * and run it entirely with interrupts hard disabled. | |
2055 | */ | |
2104180a NP |
2056 | EXC_COMMON_BEGIN(soft_nmi_common) |
2057 | mr r10,r1 | |
2058 | ld r1,PACAEMERGSP(r13) | |
2104180a | 2059 | subi r1,r1,INT_FRAME_SIZE |
47169fba NP |
2060 | EXCEPTION_COMMON_STACK(PACA_EXGEN, 0x900) |
2061 | bl save_nvgprs | |
2062 | RECONCILE_IRQ_STATE(r10, r11) | |
c06075f3 NP |
2063 | addi r3,r1,STACK_FRAME_OVERHEAD |
2064 | bl soft_nmi_interrupt | |
2104180a NP |
2065 | b ret_from_except |
2066 | ||
75eb767e | 2067 | #else /* CONFIG_PPC_WATCHDOG */ |
2104180a NP |
2068 | #define MASKED_DEC_HANDLER_LABEL 2f /* normal return */ |
2069 | #define MASKED_DEC_HANDLER(_H) | |
75eb767e | 2070 | #endif /* CONFIG_PPC_WATCHDOG */ |
d7e89849 | 2071 | |
0ebc4cda | 2072 | /* |
fe9e1d54 IM |
2073 | * An interrupt came in while soft-disabled. We set paca->irq_happened, then: |
2074 | * - If it was a decrementer interrupt, we bump the dec to max and and return. | |
2075 | * - If it was a doorbell we return immediately since doorbells are edge | |
2076 | * triggered and won't automatically refire. | |
0869b6fd MS |
2077 | * - If it was a HMI we return immediately since we handled it in realmode |
2078 | * and it won't refire. | |
6cc3f91b | 2079 | * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return. |
fe9e1d54 | 2080 | * This is called with r10 containing the value to OR to the paca field. |
0ebc4cda | 2081 | */ |
4508a74a NP |
2082 | .macro MASKED_INTERRUPT hsrr |
2083 | .if \hsrr | |
2084 | masked_Hinterrupt: | |
2085 | .else | |
2086 | masked_interrupt: | |
2087 | .endif | |
2088 | std r11,PACA_EXGEN+EX_R11(r13) | |
2089 | lbz r11,PACAIRQHAPPENED(r13) | |
2090 | or r11,r11,r10 | |
2091 | stb r11,PACAIRQHAPPENED(r13) | |
2092 | cmpwi r10,PACA_IRQ_DEC | |
2093 | bne 1f | |
2094 | lis r10,0x7fff | |
2095 | ori r10,r10,0xffff | |
2096 | mtspr SPRN_DEC,r10 | |
2097 | b MASKED_DEC_HANDLER_LABEL | |
2098 | 1: andi. r10,r10,PACA_IRQ_MUST_HARD_MASK | |
2099 | beq 2f | |
2100 | .if \hsrr | |
2101 | mfspr r10,SPRN_HSRR1 | |
2102 | xori r10,r10,MSR_EE /* clear MSR_EE */ | |
2103 | mtspr SPRN_HSRR1,r10 | |
2104 | .else | |
2105 | mfspr r10,SPRN_SRR1 | |
2106 | xori r10,r10,MSR_EE /* clear MSR_EE */ | |
2107 | mtspr SPRN_SRR1,r10 | |
2108 | .endif | |
2109 | ori r11,r11,PACA_IRQ_HARD_DIS | |
2110 | stb r11,PACAIRQHAPPENED(r13) | |
2111 | 2: /* done */ | |
2112 | mtcrf 0x80,r9 | |
2113 | std r1,PACAR1(r13) | |
2114 | ld r9,PACA_EXGEN+EX_R9(r13) | |
2115 | ld r10,PACA_EXGEN+EX_R10(r13) | |
2116 | ld r11,PACA_EXGEN+EX_R11(r13) | |
2117 | /* returns to kernel where r13 must be set up, so don't restore it */ | |
2118 | .if \hsrr | |
2119 | HRFI_TO_KERNEL | |
2120 | .else | |
2121 | RFI_TO_KERNEL | |
2122 | .endif | |
2123 | b . | |
2124 | MASKED_DEC_HANDLER(\hsrr\()) | |
2125 | .endm | |
57f26649 | 2126 | |
a048a07d NP |
2127 | TRAMP_REAL_BEGIN(stf_barrier_fallback) |
2128 | std r9,PACA_EXRFI+EX_R9(r13) | |
2129 | std r10,PACA_EXRFI+EX_R10(r13) | |
2130 | sync | |
2131 | ld r9,PACA_EXRFI+EX_R9(r13) | |
2132 | ld r10,PACA_EXRFI+EX_R10(r13) | |
2133 | ori 31,31,0 | |
2134 | .rept 14 | |
2135 | b 1f | |
2136 | 1: | |
2137 | .endr | |
2138 | blr | |
2139 | ||
aa8a5e00 ME |
2140 | TRAMP_REAL_BEGIN(rfi_flush_fallback) |
2141 | SET_SCRATCH0(r13); | |
2142 | GET_PACA(r13); | |
78ee9946 ME |
2143 | std r1,PACA_EXRFI+EX_R12(r13) |
2144 | ld r1,PACAKSAVE(r13) | |
aa8a5e00 ME |
2145 | std r9,PACA_EXRFI+EX_R9(r13) |
2146 | std r10,PACA_EXRFI+EX_R10(r13) | |
2147 | std r11,PACA_EXRFI+EX_R11(r13) | |
aa8a5e00 ME |
2148 | mfctr r9 |
2149 | ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) | |
bdcb1aef NP |
2150 | ld r11,PACA_L1D_FLUSH_SIZE(r13) |
2151 | srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ | |
aa8a5e00 | 2152 | mtctr r11 |
15a3204d | 2153 | DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ |
aa8a5e00 ME |
2154 | |
2155 | /* order ld/st prior to dcbt stop all streams with flushing */ | |
2156 | sync | |
bdcb1aef NP |
2157 | |
2158 | /* | |
2159 | * The load adresses are at staggered offsets within cachelines, | |
2160 | * which suits some pipelines better (on others it should not | |
2161 | * hurt). | |
2162 | */ | |
2163 | 1: | |
2164 | ld r11,(0x80 + 8)*0(r10) | |
2165 | ld r11,(0x80 + 8)*1(r10) | |
2166 | ld r11,(0x80 + 8)*2(r10) | |
2167 | ld r11,(0x80 + 8)*3(r10) | |
2168 | ld r11,(0x80 + 8)*4(r10) | |
2169 | ld r11,(0x80 + 8)*5(r10) | |
2170 | ld r11,(0x80 + 8)*6(r10) | |
2171 | ld r11,(0x80 + 8)*7(r10) | |
2172 | addi r10,r10,0x80*8 | |
aa8a5e00 ME |
2173 | bdnz 1b |
2174 | ||
2175 | mtctr r9 | |
2176 | ld r9,PACA_EXRFI+EX_R9(r13) | |
2177 | ld r10,PACA_EXRFI+EX_R10(r13) | |
2178 | ld r11,PACA_EXRFI+EX_R11(r13) | |
78ee9946 | 2179 | ld r1,PACA_EXRFI+EX_R12(r13) |
aa8a5e00 ME |
2180 | GET_SCRATCH0(r13); |
2181 | rfid | |
2182 | ||
2183 | TRAMP_REAL_BEGIN(hrfi_flush_fallback) | |
2184 | SET_SCRATCH0(r13); | |
2185 | GET_PACA(r13); | |
78ee9946 ME |
2186 | std r1,PACA_EXRFI+EX_R12(r13) |
2187 | ld r1,PACAKSAVE(r13) | |
aa8a5e00 ME |
2188 | std r9,PACA_EXRFI+EX_R9(r13) |
2189 | std r10,PACA_EXRFI+EX_R10(r13) | |
2190 | std r11,PACA_EXRFI+EX_R11(r13) | |
aa8a5e00 ME |
2191 | mfctr r9 |
2192 | ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) | |
bdcb1aef NP |
2193 | ld r11,PACA_L1D_FLUSH_SIZE(r13) |
2194 | srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ | |
aa8a5e00 | 2195 | mtctr r11 |
15a3204d | 2196 | DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ |
aa8a5e00 ME |
2197 | |
2198 | /* order ld/st prior to dcbt stop all streams with flushing */ | |
2199 | sync | |
bdcb1aef NP |
2200 | |
2201 | /* | |
2202 | * The load adresses are at staggered offsets within cachelines, | |
2203 | * which suits some pipelines better (on others it should not | |
2204 | * hurt). | |
2205 | */ | |
2206 | 1: | |
2207 | ld r11,(0x80 + 8)*0(r10) | |
2208 | ld r11,(0x80 + 8)*1(r10) | |
2209 | ld r11,(0x80 + 8)*2(r10) | |
2210 | ld r11,(0x80 + 8)*3(r10) | |
2211 | ld r11,(0x80 + 8)*4(r10) | |
2212 | ld r11,(0x80 + 8)*5(r10) | |
2213 | ld r11,(0x80 + 8)*6(r10) | |
2214 | ld r11,(0x80 + 8)*7(r10) | |
2215 | addi r10,r10,0x80*8 | |
aa8a5e00 ME |
2216 | bdnz 1b |
2217 | ||
2218 | mtctr r9 | |
2219 | ld r9,PACA_EXRFI+EX_R9(r13) | |
2220 | ld r10,PACA_EXRFI+EX_R10(r13) | |
2221 | ld r11,PACA_EXRFI+EX_R11(r13) | |
78ee9946 | 2222 | ld r1,PACA_EXRFI+EX_R12(r13) |
aa8a5e00 ME |
2223 | GET_SCRATCH0(r13); |
2224 | hrfid | |
2225 | ||
57f26649 NP |
2226 | /* |
2227 | * Real mode exceptions actually use this too, but alternate | |
2228 | * instruction code patches (which end up in the common .text area) | |
2229 | * cannot reach these if they are put there. | |
2230 | */ | |
2231 | USE_FIXED_SECTION(virt_trampolines) | |
4508a74a NP |
2232 | MASKED_INTERRUPT EXC_STD |
2233 | MASKED_INTERRUPT EXC_HV | |
0ebc4cda | 2234 | |
4f6c11db | 2235 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
da2bc464 | 2236 | TRAMP_REAL_BEGIN(kvmppc_skip_interrupt) |
4f6c11db PM |
2237 | /* |
2238 | * Here all GPRs are unchanged from when the interrupt happened | |
2239 | * except for r13, which is saved in SPRG_SCRATCH0. | |
2240 | */ | |
2241 | mfspr r13, SPRN_SRR0 | |
2242 | addi r13, r13, 4 | |
2243 | mtspr SPRN_SRR0, r13 | |
2244 | GET_SCRATCH0(r13) | |
222f20f1 | 2245 | RFI_TO_KERNEL |
4f6c11db PM |
2246 | b . |
2247 | ||
da2bc464 | 2248 | TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) |
4f6c11db PM |
2249 | /* |
2250 | * Here all GPRs are unchanged from when the interrupt happened | |
2251 | * except for r13, which is saved in SPRG_SCRATCH0. | |
2252 | */ | |
2253 | mfspr r13, SPRN_HSRR0 | |
2254 | addi r13, r13, 4 | |
2255 | mtspr SPRN_HSRR0, r13 | |
2256 | GET_SCRATCH0(r13) | |
222f20f1 | 2257 | HRFI_TO_KERNEL |
4f6c11db PM |
2258 | b . |
2259 | #endif | |
2260 | ||
0ebc4cda | 2261 | /* |
057b6d7e HB |
2262 | * Ensure that any handlers that get invoked from the exception prologs |
2263 | * above are below the first 64KB (0x10000) of the kernel image because | |
2264 | * the prologs assemble the addresses of these handlers using the | |
2265 | * LOAD_HANDLER macro, which uses an ori instruction. | |
0ebc4cda BH |
2266 | */ |
2267 | ||
2268 | /*** Common interrupt handlers ***/ | |
2269 | ||
0ebc4cda | 2270 | |
c1fb6816 MN |
2271 | /* |
2272 | * Relocation-on interrupts: A subset of the interrupts can be delivered | |
2273 | * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering | |
2274 | * it. Addresses are the same as the original interrupt addresses, but | |
2275 | * offset by 0xc000000000004000. | |
2276 | * It's impossible to receive interrupts below 0x300 via this mechanism. | |
2277 | * KVM: None of these traps are from the guest ; anything that escalated | |
2278 | * to HV=1 from HV=0 is delivered via real mode handlers. | |
2279 | */ | |
2280 | ||
2281 | /* | |
2282 | * This uses the standard macro, since the original 0x300 vector | |
2283 | * only has extra guff for STAB-based processors -- which never | |
2284 | * come here. | |
2285 | */ | |
da2bc464 | 2286 | |
57f26649 | 2287 | EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) |
b1576fec | 2288 | b __ppc64_runlatch_on |
fe1952fc | 2289 | |
57f26649 | 2290 | USE_FIXED_SECTION(virt_trampolines) |
8ed8ab40 HB |
2291 | /* |
2292 | * The __end_interrupts marker must be past the out-of-line (OOL) | |
2293 | * handlers, so that they are copied to real address 0x100 when running | |
2294 | * a relocatable kernel. This ensures they can be reached from the short | |
2295 | * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch | |
2296 | * directly, without using LOAD_HANDLER(). | |
2297 | */ | |
2298 | .align 7 | |
2299 | .globl __end_interrupts | |
2300 | __end_interrupts: | |
57f26649 | 2301 | DEFINE_FIXED_SYMBOL(__end_interrupts) |
61383407 | 2302 | |
087aa036 | 2303 | #ifdef CONFIG_PPC_970_NAP |
7c8cb4b5 | 2304 | EXC_COMMON_BEGIN(power4_fixup_nap) |
087aa036 CG |
2305 | andc r9,r9,r10 |
2306 | std r9,TI_LOCAL_FLAGS(r11) | |
2307 | ld r10,_LINK(r1) /* make idle task do the */ | |
2308 | std r10,_NIP(r1) /* equivalent of a blr */ | |
2309 | blr | |
2310 | #endif | |
2311 | ||
57f26649 NP |
2312 | CLOSE_FIXED_SECTION(real_vectors); |
2313 | CLOSE_FIXED_SECTION(real_trampolines); | |
2314 | CLOSE_FIXED_SECTION(virt_vectors); | |
2315 | CLOSE_FIXED_SECTION(virt_trampolines); | |
2316 | ||
2317 | USE_TEXT_SECTION() | |
2318 | ||
0ebc4cda BH |
2319 | /* |
2320 | * Hash table stuff | |
2321 | */ | |
f4329f2e | 2322 | .balign IFETCH_ALIGN_BYTES |
6a3bab90 | 2323 | do_hash_page: |
4e003747 | 2324 | #ifdef CONFIG_PPC_BOOK3S_64 |
e6c2a479 | 2325 | lis r0,(DSISR_BAD_FAULT_64S | DSISR_DABRMATCH | DSISR_KEYFAULT)@h |
398a719d BH |
2326 | ori r0,r0,DSISR_BAD_FAULT_64S@l |
2327 | and. r0,r4,r0 /* weird error? */ | |
0ebc4cda | 2328 | bne- handle_page_fault /* if not, try to insert a HPTE */ |
c911d2e1 | 2329 | ld r11, PACA_THREAD_INFO(r13) |
9c1e1052 PM |
2330 | lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ |
2331 | andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ | |
2332 | bne 77f /* then don't call hash_page now */ | |
0ebc4cda BH |
2333 | |
2334 | /* | |
2335 | * r3 contains the faulting address | |
106713a1 | 2336 | * r4 msr |
0ebc4cda | 2337 | * r5 contains the trap number |
aefa5688 | 2338 | * r6 contains dsisr |
0ebc4cda | 2339 | * |
7230c564 | 2340 | * at return r3 = 0 for success, 1 for page fault, negative for error |
0ebc4cda | 2341 | */ |
106713a1 | 2342 | mr r4,r12 |
aefa5688 | 2343 | ld r6,_DSISR(r1) |
106713a1 AK |
2344 | bl __hash_page /* build HPTE if possible */ |
2345 | cmpdi r3,0 /* see if __hash_page succeeded */ | |
0ebc4cda | 2346 | |
7230c564 | 2347 | /* Success */ |
0ebc4cda | 2348 | beq fast_exc_return_irq /* Return from exception on success */ |
0ebc4cda | 2349 | |
7230c564 BH |
2350 | /* Error */ |
2351 | blt- 13f | |
d89ba535 NR |
2352 | |
2353 | /* Reload DSISR into r4 for the DABR check below */ | |
2354 | ld r4,_DSISR(r1) | |
4e003747 | 2355 | #endif /* CONFIG_PPC_BOOK3S_64 */ |
9c7cc234 | 2356 | |
0ebc4cda BH |
2357 | /* Here we have a page fault that hash_page can't handle. */ |
2358 | handle_page_fault: | |
d89ba535 NR |
2359 | 11: andis. r0,r4,DSISR_DABRMATCH@h |
2360 | bne- handle_dabr_fault | |
2361 | ld r4,_DAR(r1) | |
0ebc4cda BH |
2362 | ld r5,_DSISR(r1) |
2363 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec | 2364 | bl do_page_fault |
0ebc4cda | 2365 | cmpdi r3,0 |
f474c28f | 2366 | beq+ ret_from_except_lite |
b1576fec | 2367 | bl save_nvgprs |
0ebc4cda BH |
2368 | mr r5,r3 |
2369 | addi r3,r1,STACK_FRAME_OVERHEAD | |
2370 | lwz r4,_DAR(r1) | |
b1576fec AB |
2371 | bl bad_page_fault |
2372 | b ret_from_except | |
0ebc4cda | 2373 | |
a546498f BH |
2374 | /* We have a data breakpoint exception - handle it */ |
2375 | handle_dabr_fault: | |
b1576fec | 2376 | bl save_nvgprs |
a546498f BH |
2377 | ld r4,_DAR(r1) |
2378 | ld r5,_DSISR(r1) | |
2379 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec | 2380 | bl do_break |
f474c28f RB |
2381 | /* |
2382 | * do_break() may have changed the NV GPRS while handling a breakpoint. | |
2383 | * If so, we need to restore them with their updated values. Don't use | |
2384 | * ret_from_except_lite here. | |
2385 | */ | |
2386 | b ret_from_except | |
a546498f | 2387 | |
0ebc4cda | 2388 | |
4e003747 | 2389 | #ifdef CONFIG_PPC_BOOK3S_64 |
0ebc4cda BH |
2390 | /* We have a page fault that hash_page could handle but HV refused |
2391 | * the PTE insertion | |
2392 | */ | |
b1576fec | 2393 | 13: bl save_nvgprs |
0ebc4cda BH |
2394 | mr r5,r3 |
2395 | addi r3,r1,STACK_FRAME_OVERHEAD | |
2396 | ld r4,_DAR(r1) | |
b1576fec AB |
2397 | bl low_hash_fault |
2398 | b ret_from_except | |
caca285e | 2399 | #endif |
0ebc4cda | 2400 | |
9c1e1052 PM |
2401 | /* |
2402 | * We come here as a result of a DSI at a point where we don't want | |
2403 | * to call hash_page, such as when we are accessing memory (possibly | |
2404 | * user memory) inside a PMU interrupt that occurred while interrupts | |
2405 | * were soft-disabled. We want to invoke the exception handler for | |
2406 | * the access, or panic if there isn't a handler. | |
2407 | */ | |
b1576fec | 2408 | 77: bl save_nvgprs |
9c1e1052 PM |
2409 | mr r4,r3 |
2410 | addi r3,r1,STACK_FRAME_OVERHEAD | |
2411 | li r5,SIGSEGV | |
b1576fec AB |
2412 | bl bad_page_fault |
2413 | b ret_from_except | |
4e2bf01b | 2414 | |
a9af97aa NP |
2415 | /* |
2416 | * When doorbell is triggered from system reset wakeup, the message is | |
2417 | * not cleared, so it would fire again when EE is enabled. | |
2418 | * | |
2419 | * When coming from local_irq_enable, there may be the same problem if | |
2420 | * we were hard disabled. | |
2421 | * | |
2422 | * Execute msgclr to clear pending exceptions before handling it. | |
2423 | */ | |
2424 | h_doorbell_common_msgclr: | |
2425 | LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) | |
2426 | PPC_MSGCLR(3) | |
2427 | b h_doorbell_common | |
2428 | ||
2429 | doorbell_super_common_msgclr: | |
2430 | LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) | |
2431 | PPC_MSGCLRP(3) | |
2432 | b doorbell_super_common | |
2433 | ||
0f0c6ca1 NP |
2434 | /* |
2435 | * Called from arch_local_irq_enable when an interrupt needs | |
2436 | * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate | |
2437 | * which kind of interrupt. MSR:EE is already off. We generate a | |
2438 | * stackframe like if a real interrupt had happened. | |
2439 | * | |
2440 | * Note: While MSR:EE is off, we need to make sure that _MSR | |
2441 | * in the generated frame has EE set to 1 or the exception | |
2442 | * handler will not properly re-enable them. | |
b48bbb82 NP |
2443 | * |
2444 | * Note that we don't specify LR as the NIP (return address) for | |
2445 | * the interrupt because that would unbalance the return branch | |
2446 | * predictor. | |
0f0c6ca1 NP |
2447 | */ |
2448 | _GLOBAL(__replay_interrupt) | |
2449 | /* We are going to jump to the exception common code which | |
2450 | * will retrieve various register values from the PACA which | |
2451 | * we don't give a damn about, so we don't bother storing them. | |
2452 | */ | |
2453 | mfmsr r12 | |
3e23a12b | 2454 | LOAD_REG_ADDR(r11, replay_interrupt_return) |
0f0c6ca1 NP |
2455 | mfcr r9 |
2456 | ori r12,r12,MSR_EE | |
2457 | cmpwi r3,0x900 | |
2458 | beq decrementer_common | |
2459 | cmpwi r3,0x500 | |
e6c1203d NP |
2460 | BEGIN_FTR_SECTION |
2461 | beq h_virt_irq_common | |
2462 | FTR_SECTION_ELSE | |
0f0c6ca1 | 2463 | beq hardware_interrupt_common |
e6c1203d | 2464 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_300) |
f442d004 MS |
2465 | cmpwi r3,0xf00 |
2466 | beq performance_monitor_common | |
0f0c6ca1 | 2467 | BEGIN_FTR_SECTION |
d6f73fc6 | 2468 | cmpwi r3,0xa00 |
a9af97aa | 2469 | beq h_doorbell_common_msgclr |
0f0c6ca1 NP |
2470 | cmpwi r3,0xe60 |
2471 | beq hmi_exception_common | |
2472 | FTR_SECTION_ELSE | |
2473 | cmpwi r3,0xa00 | |
a9af97aa | 2474 | beq doorbell_super_common_msgclr |
0f0c6ca1 | 2475 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
3e23a12b | 2476 | replay_interrupt_return: |
0f0c6ca1 | 2477 | blr |
b48bbb82 | 2478 | |
15770a13 | 2479 | _ASM_NOKPROBE_SYMBOL(__replay_interrupt) |