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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
0ebc4cda BH |
2 | /* |
3 | * This file contains the 64-bit "server" PowerPC variant | |
4 | * of the low level exception handling including exception | |
5 | * vectors, exception return, part of the slb and stab | |
6 | * handling and other fixed offset specific things. | |
7 | * | |
8 | * This file is meant to be #included from head_64.S due to | |
25985edc | 9 | * position dependent assembly. |
0ebc4cda BH |
10 | * |
11 | * Most of this originates from head_64.S and thus has the same | |
12 | * copyright history. | |
13 | * | |
14 | */ | |
15 | ||
7230c564 | 16 | #include <asm/hw_irq.h> |
8aa34ab8 | 17 | #include <asm/exception-64s.h> |
46f52210 | 18 | #include <asm/ptrace.h> |
7cba160a | 19 | #include <asm/cpuidle.h> |
da2bc464 | 20 | #include <asm/head-64.h> |
2c86cd18 | 21 | #include <asm/feature-fixups.h> |
890274c2 | 22 | #include <asm/kup.h> |
8aa34ab8 | 23 | |
0ebc4cda | 24 | /* |
57f26649 NP |
25 | * There are a few constraints to be concerned with. |
26 | * - Real mode exceptions code/data must be located at their physical location. | |
27 | * - Virtual mode exceptions must be mapped at their 0xc000... location. | |
28 | * - Fixed location code must not call directly beyond the __end_interrupts | |
29 | * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence | |
30 | * must be used. | |
31 | * - LOAD_HANDLER targets must be within first 64K of physical 0 / | |
32 | * virtual 0xc00... | |
33 | * - Conditional branch targets must be within +/-32K of caller. | |
34 | * | |
35 | * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and | |
36 | * therefore don't have to run in physically located code or rfid to | |
37 | * virtual mode kernel code. However on relocatable kernels they do have | |
38 | * to branch to KERNELBASE offset because the rest of the kernel (outside | |
39 | * the exception vectors) may be located elsewhere. | |
40 | * | |
41 | * Virtual exceptions correspond with physical, except their entry points | |
42 | * are offset by 0xc000000000000000 and also tend to get an added 0x4000 | |
43 | * offset applied. Virtual exceptions are enabled with the Alternate | |
44 | * Interrupt Location (AIL) bit set in the LPCR. However this does not | |
45 | * guarantee they will be delivered virtually. Some conditions (see the ISA) | |
46 | * cause exceptions to be delivered in real mode. | |
47 | * | |
48 | * It's impossible to receive interrupts below 0x300 via AIL. | |
49 | * | |
50 | * KVM: None of the virtual exceptions are from the guest. Anything that | |
51 | * escalated to HV=1 from HV=0 is delivered via real mode handlers. | |
52 | * | |
53 | * | |
0ebc4cda BH |
54 | * We layout physical memory as follows: |
55 | * 0x0000 - 0x00ff : Secondary processor spin code | |
57f26649 NP |
56 | * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors |
57 | * 0x1900 - 0x3fff : Real mode trampolines | |
58 | * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors | |
59 | * 0x5900 - 0x6fff : Relon mode trampolines | |
0ebc4cda | 60 | * 0x7000 - 0x7fff : FWNMI data area |
57f26649 NP |
61 | * 0x8000 - .... : Common interrupt handlers, remaining early |
62 | * setup code, rest of kernel. | |
e0319829 NP |
63 | * |
64 | * We could reclaim 0x4000-0x42ff for real mode trampolines if the space | |
65 | * is necessary. Until then it's more consistent to explicitly put VIRT_NONE | |
66 | * vectors there. | |
57f26649 NP |
67 | */ |
68 | OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) | |
69 | OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000) | |
70 | OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900) | |
71 | OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) | |
ccd47702 NP |
72 | |
73 | #ifdef CONFIG_PPC_POWERNV | |
bd3524fe NP |
74 | .globl start_real_trampolines |
75 | .globl end_real_trampolines | |
76 | .globl start_virt_trampolines | |
77 | .globl end_virt_trampolines | |
ccd47702 NP |
78 | #endif |
79 | ||
57f26649 NP |
80 | #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) |
81 | /* | |
82 | * Data area reserved for FWNMI option. | |
83 | * This address (0x7000) is fixed by the RPA. | |
84 | * pseries and powernv need to keep the whole page from | |
85 | * 0x7000 to 0x8000 free for use by the firmware | |
0ebc4cda | 86 | */ |
57f26649 NP |
87 | ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) |
88 | OPEN_TEXT_SECTION(0x8000) | |
89 | #else | |
90 | OPEN_TEXT_SECTION(0x7000) | |
91 | #endif | |
92 | ||
93 | USE_FIXED_SECTION(real_vectors) | |
94 | ||
0ebc4cda BH |
95 | /* |
96 | * This is the start of the interrupt handlers for pSeries | |
97 | * This code runs with relocation off. | |
98 | * Code from here to __end_interrupts gets copied down to real | |
99 | * address 0x100 when we are running a relocatable kernel. | |
100 | * Therefore any relative branches in this section must only | |
101 | * branch to labels in this section. | |
102 | */ | |
0ebc4cda BH |
103 | .globl __start_interrupts |
104 | __start_interrupts: | |
105 | ||
e0319829 | 106 | /* No virt vectors corresponding with 0x0..0x100 */ |
1a6822d1 | 107 | EXC_VIRT_NONE(0x4000, 0x100) |
e0319829 | 108 | |
fb479e44 | 109 | |
a7c1ca19 NP |
110 | EXC_REAL_BEGIN(system_reset, 0x100, 0x100) |
111 | SET_SCRATCH0(r13) | |
5dba1d50 | 112 | EXCEPTION_PROLOG_0 PACA_EXNMI |
a7c1ca19 NP |
113 | |
114 | /* This is EXCEPTION_PROLOG_1 with the idle feature section added */ | |
115 | OPT_SAVE_REG_TO_PACA(PACA_EXNMI+EX_PPR, r9, CPU_FTR_HAS_PPR) | |
116 | OPT_SAVE_REG_TO_PACA(PACA_EXNMI+EX_CFAR, r10, CPU_FTR_CFAR) | |
117 | INTERRUPT_TO_KERNEL | |
118 | SAVE_CTR(r10, PACA_EXNMI) | |
119 | mfcr r9 | |
120 | ||
948cf67c | 121 | #ifdef CONFIG_PPC_P7_NAP |
fb479e44 NP |
122 | /* |
123 | * If running native on arch 2.06 or later, check if we are waking up | |
ba6d334a BH |
124 | * from nap/sleep/winkle, and branch to idle handler. This tests SRR1 |
125 | * bits 46:47. A non-0 value indicates that we are coming from a power | |
126 | * saving state. The idle wakeup handler initially runs in real mode, | |
127 | * but we branch to the 0xc000... address so we can turn on relocation | |
128 | * with mtmsr. | |
948cf67c | 129 | */ |
a7c1ca19 NP |
130 | BEGIN_FTR_SECTION |
131 | mfspr r10,SPRN_SRR1 | |
132 | rlwinm. r10,r10,47-31,30,31 | |
133 | beq- 1f | |
134 | cmpwi cr1,r10,2 | |
135 | mfspr r3,SPRN_SRR1 | |
136 | bltlr cr1 /* no state loss, return to idle caller */ | |
137 | BRANCH_TO_C000(r10, system_reset_idle_common) | |
138 | 1: | |
139 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) | |
fb479e44 | 140 | #endif |
371fefd6 | 141 | |
a7c1ca19 NP |
142 | KVMTEST EXC_STD 0x100 |
143 | std r11,PACA_EXNMI+EX_R11(r13) | |
144 | std r12,PACA_EXNMI+EX_R12(r13) | |
145 | GET_SCRATCH0(r10) | |
146 | std r10,PACA_EXNMI+EX_R13(r13) | |
147 | ||
148 | EXCEPTION_PROLOG_2_REAL system_reset_common, EXC_STD, 0 | |
c4f3b52c NP |
149 | /* |
150 | * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is | |
151 | * being used, so a nested NMI exception would corrupt it. | |
152 | */ | |
fb479e44 | 153 | |
1a6822d1 NP |
154 | EXC_REAL_END(system_reset, 0x100, 0x100) |
155 | EXC_VIRT_NONE(0x4100, 0x100) | |
6de6638b | 156 | TRAMP_KVM(PACA_EXNMI, 0x100) |
fb479e44 NP |
157 | |
158 | #ifdef CONFIG_PPC_P7_NAP | |
159 | EXC_COMMON_BEGIN(system_reset_idle_common) | |
10d91611 NP |
160 | /* |
161 | * This must be a direct branch (without linker branch stub) because | |
162 | * we can not use TOC at this point as r2 may not be restored yet. | |
163 | */ | |
164 | b idle_return_gpr_loss | |
371fefd6 PM |
165 | #endif |
166 | ||
15b4dd79 NP |
167 | /* |
168 | * Set IRQS_ALL_DISABLED unconditionally so arch_irqs_disabled does | |
169 | * the right thing. We do not want to reconcile because that goes | |
170 | * through irq tracing which we don't want in NMI. | |
171 | * | |
172 | * Save PACAIRQHAPPENED because some code will do a hard disable | |
173 | * (e.g., xmon). So we want to restore this back to where it was | |
174 | * when we return. DAR is unused in the stack, so save it there. | |
175 | */ | |
176 | #define ADD_RECONCILE_NMI \ | |
177 | li r10,IRQS_ALL_DISABLED; \ | |
178 | stb r10,PACAIRQSOFTMASK(r13); \ | |
179 | lbz r10,PACAIRQHAPPENED(r13); \ | |
180 | std r10,_DAR(r1) | |
181 | ||
a3d96f70 | 182 | EXC_COMMON_BEGIN(system_reset_common) |
c4f3b52c NP |
183 | /* |
184 | * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able | |
185 | * to recover, but nested NMI will notice in_nmi and not recover | |
186 | * because of the use of the NMI stack. in_nmi reentrancy is tested in | |
187 | * system_reset_exception. | |
188 | */ | |
189 | lhz r10,PACA_IN_NMI(r13) | |
190 | addi r10,r10,1 | |
191 | sth r10,PACA_IN_NMI(r13) | |
192 | li r10,MSR_RI | |
193 | mtmsrd r10,1 | |
aca79d2b | 194 | |
b1ee8a3d NP |
195 | mr r10,r1 |
196 | ld r1,PACA_NMI_EMERG_SP(r13) | |
197 | subi r1,r1,INT_FRAME_SIZE | |
198 | EXCEPTION_COMMON_NORET_STACK(PACA_EXNMI, 0x100, | |
199 | system_reset, system_reset_exception, | |
15b4dd79 NP |
200 | ADD_NVGPRS;ADD_RECONCILE_NMI) |
201 | ||
202 | /* This (and MCE) can be simplified with mtmsrd L=1 */ | |
203 | /* Clear MSR_RI before setting SRR0 and SRR1. */ | |
204 | li r0,MSR_RI | |
205 | mfmsr r9 | |
206 | andc r9,r9,r0 | |
207 | mtmsrd r9,1 | |
c4f3b52c NP |
208 | |
209 | /* | |
15b4dd79 | 210 | * MSR_RI is clear, now we can decrement paca->in_nmi. |
c4f3b52c NP |
211 | */ |
212 | lhz r10,PACA_IN_NMI(r13) | |
213 | subi r10,r10,1 | |
214 | sth r10,PACA_IN_NMI(r13) | |
215 | ||
15b4dd79 NP |
216 | /* |
217 | * Restore soft mask settings. | |
218 | */ | |
219 | ld r10,_DAR(r1) | |
220 | stb r10,PACAIRQHAPPENED(r13) | |
221 | ld r10,SOFTE(r1) | |
222 | stb r10,PACAIRQSOFTMASK(r13) | |
223 | ||
224 | /* | |
225 | * Keep below code in synch with MACHINE_CHECK_HANDLER_WINDUP. | |
226 | * Should share common bits... | |
227 | */ | |
228 | ||
229 | /* Move original SRR0 and SRR1 into the respective regs */ | |
230 | ld r9,_MSR(r1) | |
231 | mtspr SPRN_SRR1,r9 | |
232 | ld r3,_NIP(r1) | |
233 | mtspr SPRN_SRR0,r3 | |
234 | ld r9,_CTR(r1) | |
235 | mtctr r9 | |
236 | ld r9,_XER(r1) | |
237 | mtxer r9 | |
238 | ld r9,_LINK(r1) | |
239 | mtlr r9 | |
240 | REST_GPR(0, r1) | |
241 | REST_8GPRS(2, r1) | |
242 | REST_GPR(10, r1) | |
243 | ld r11,_CCR(r1) | |
244 | mtcr r11 | |
245 | REST_GPR(11, r1) | |
246 | REST_2GPRS(12, r1) | |
247 | /* restore original r1. */ | |
248 | ld r1,GPR1(r1) | |
249 | RFI_TO_USER_OR_KERNEL | |
582baf44 NP |
250 | |
251 | #ifdef CONFIG_PPC_PSERIES | |
252 | /* | |
253 | * Vectors for the FWNMI option. Share common code. | |
254 | */ | |
255 | TRAMP_REAL_BEGIN(system_reset_fwnmi) | |
256 | SET_SCRATCH0(r13) /* save r13 */ | |
c4f3b52c | 257 | /* See comment at system_reset exception */ |
94f3cc8e | 258 | EXCEPTION_PROLOG_NORI(PACA_EXNMI, system_reset_common, EXC_STD, |
a7c1ca19 | 259 | 0, 0x100) |
582baf44 NP |
260 | #endif /* CONFIG_PPC_PSERIES */ |
261 | ||
0ebc4cda | 262 | |
1a6822d1 | 263 | EXC_REAL_BEGIN(machine_check, 0x200, 0x100) |
b01c8b54 PM |
264 | /* This is moved out of line as it can be patched by FW, but |
265 | * some code path might still want to branch into the original | |
266 | * vector | |
267 | */ | |
1707dd16 | 268 | SET_SCRATCH0(r13) /* save r13 */ |
5dba1d50 | 269 | EXCEPTION_PROLOG_0 PACA_EXMC |
1e9b4507 | 270 | BEGIN_FTR_SECTION |
db7d31ac | 271 | b machine_check_common_early |
1e9b4507 | 272 | FTR_SECTION_ELSE |
1707dd16 | 273 | b machine_check_pSeries_0 |
1e9b4507 | 274 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
1a6822d1 NP |
275 | EXC_REAL_END(machine_check, 0x200, 0x100) |
276 | EXC_VIRT_NONE(0x4200, 0x100) | |
db7d31ac | 277 | TRAMP_REAL_BEGIN(machine_check_common_early) |
fa4cf6b7 | 278 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 0, 0x200, 0 |
afcf0095 NP |
279 | /* |
280 | * Register contents: | |
281 | * R13 = PACA | |
282 | * R9 = CR | |
283 | * Original R9 to R13 is saved on PACA_EXMC | |
284 | * | |
285 | * Switch to mc_emergency stack and handle re-entrancy (we limit | |
286 | * the nested MCE upto level 4 to avoid stack overflow). | |
287 | * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 | |
288 | * | |
289 | * We use paca->in_mce to check whether this is the first entry or | |
290 | * nested machine check. We increment paca->in_mce to track nested | |
291 | * machine checks. | |
292 | * | |
293 | * If this is the first entry then set stack pointer to | |
294 | * paca->mc_emergency_sp, otherwise r1 is already pointing to | |
295 | * stack frame on mc_emergency stack. | |
296 | * | |
297 | * NOTE: We are here with MSR_ME=0 (off), which means we risk a | |
298 | * checkstop if we get another machine check exception before we do | |
299 | * rfid with MSR_ME=1. | |
1945bc45 NP |
300 | * |
301 | * This interrupt can wake directly from idle. If that is the case, | |
302 | * the machine check is handled then the idle wakeup code is called | |
2bf1071a | 303 | * to restore state. |
afcf0095 NP |
304 | */ |
305 | mr r11,r1 /* Save r1 */ | |
306 | lhz r10,PACA_IN_MCE(r13) | |
307 | cmpwi r10,0 /* Are we in nested machine check */ | |
308 | bne 0f /* Yes, we are. */ | |
309 | /* First machine check entry */ | |
310 | ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ | |
311 | 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
312 | addi r10,r10,1 /* increment paca->in_mce */ | |
313 | sth r10,PACA_IN_MCE(r13) | |
314 | /* Limit nested MCE to level 4 to avoid stack overflow */ | |
ba41e1e1 | 315 | cmpwi r10,MAX_MCE_DEPTH |
afcf0095 NP |
316 | bgt 2f /* Check if we hit limit of 4 */ |
317 | std r11,GPR1(r1) /* Save r1 on the stack. */ | |
318 | std r11,0(r1) /* make stack chain pointer */ | |
319 | mfspr r11,SPRN_SRR0 /* Save SRR0 */ | |
320 | std r11,_NIP(r1) | |
321 | mfspr r11,SPRN_SRR1 /* Save SRR1 */ | |
322 | std r11,_MSR(r1) | |
323 | mfspr r11,SPRN_DAR /* Save DAR */ | |
324 | std r11,_DAR(r1) | |
325 | mfspr r11,SPRN_DSISR /* Save DSISR */ | |
326 | std r11,_DSISR(r1) | |
327 | std r9,_CCR(r1) /* Save CR in stackframe */ | |
e13e7cd4 | 328 | /* We don't touch AMR here, we never go to virtual mode */ |
afcf0095 NP |
329 | /* Save r9 through r13 from EXMC save area to stack frame. */ |
330 | EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) | |
331 | mfmsr r11 /* get MSR value */ | |
db7d31ac | 332 | BEGIN_FTR_SECTION |
afcf0095 | 333 | ori r11,r11,MSR_ME /* turn on ME bit */ |
db7d31ac | 334 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) |
afcf0095 NP |
335 | ori r11,r11,MSR_RI /* turn on RI bit */ |
336 | LOAD_HANDLER(r12, machine_check_handle_early) | |
337 | 1: mtspr SPRN_SRR0,r12 | |
338 | mtspr SPRN_SRR1,r11 | |
222f20f1 | 339 | RFI_TO_KERNEL |
afcf0095 NP |
340 | b . /* prevent speculative execution */ |
341 | 2: | |
342 | /* Stack overflow. Stay on emergency stack and panic. | |
343 | * Keep the ME bit off while panic-ing, so that if we hit | |
344 | * another machine check we checkstop. | |
345 | */ | |
346 | addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ | |
347 | ld r11,PACAKMSR(r13) | |
348 | LOAD_HANDLER(r12, unrecover_mce) | |
349 | li r10,MSR_ME | |
350 | andc r11,r11,r10 /* Turn off MSR_ME */ | |
351 | b 1b | |
352 | b . /* prevent speculative execution */ | |
afcf0095 NP |
353 | |
354 | TRAMP_REAL_BEGIN(machine_check_pSeries) | |
355 | .globl machine_check_fwnmi | |
356 | machine_check_fwnmi: | |
357 | SET_SCRATCH0(r13) /* save r13 */ | |
5dba1d50 | 358 | EXCEPTION_PROLOG_0 PACA_EXMC |
a43c1590 | 359 | BEGIN_FTR_SECTION |
db7d31ac | 360 | b machine_check_common_early |
a43c1590 | 361 | END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE) |
afcf0095 | 362 | machine_check_pSeries_0: |
fa4cf6b7 | 363 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 1, 0x200, 0 |
afcf0095 | 364 | /* |
83a980f7 NP |
365 | * MSR_RI is not enabled, because PACA_EXMC is being used, so a |
366 | * nested machine check corrupts it. machine_check_common enables | |
367 | * MSR_RI. | |
afcf0095 | 368 | */ |
2d046308 | 369 | EXCEPTION_PROLOG_2_REAL machine_check_common, EXC_STD, 0 |
afcf0095 NP |
370 | |
371 | TRAMP_KVM_SKIP(PACA_EXMC, 0x200) | |
372 | ||
373 | EXC_COMMON_BEGIN(machine_check_common) | |
374 | /* | |
375 | * Machine check is different because we use a different | |
376 | * save area: PACA_EXMC instead of PACA_EXGEN. | |
377 | */ | |
378 | mfspr r10,SPRN_DAR | |
379 | std r10,PACA_EXMC+EX_DAR(r13) | |
380 | mfspr r10,SPRN_DSISR | |
381 | stw r10,PACA_EXMC+EX_DSISR(r13) | |
382 | EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) | |
383 | FINISH_NAP | |
384 | RECONCILE_IRQ_STATE(r10, r11) | |
385 | ld r3,PACA_EXMC+EX_DAR(r13) | |
386 | lwz r4,PACA_EXMC+EX_DSISR(r13) | |
387 | /* Enable MSR_RI when finished with PACA_EXMC */ | |
388 | li r10,MSR_RI | |
389 | mtmsrd r10,1 | |
390 | std r3,_DAR(r1) | |
391 | std r4,_DSISR(r1) | |
392 | bl save_nvgprs | |
393 | addi r3,r1,STACK_FRAME_OVERHEAD | |
394 | bl machine_check_exception | |
395 | b ret_from_except | |
396 | ||
397 | #define MACHINE_CHECK_HANDLER_WINDUP \ | |
398 | /* Clear MSR_RI before setting SRR0 and SRR1. */\ | |
399 | li r0,MSR_RI; \ | |
400 | mfmsr r9; /* get MSR value */ \ | |
401 | andc r9,r9,r0; \ | |
402 | mtmsrd r9,1; /* Clear MSR_RI */ \ | |
403 | /* Move original SRR0 and SRR1 into the respective regs */ \ | |
404 | ld r9,_MSR(r1); \ | |
405 | mtspr SPRN_SRR1,r9; \ | |
406 | ld r3,_NIP(r1); \ | |
407 | mtspr SPRN_SRR0,r3; \ | |
408 | ld r9,_CTR(r1); \ | |
409 | mtctr r9; \ | |
410 | ld r9,_XER(r1); \ | |
411 | mtxer r9; \ | |
412 | ld r9,_LINK(r1); \ | |
413 | mtlr r9; \ | |
414 | REST_GPR(0, r1); \ | |
415 | REST_8GPRS(2, r1); \ | |
416 | REST_GPR(10, r1); \ | |
417 | ld r11,_CCR(r1); \ | |
418 | mtcr r11; \ | |
419 | /* Decrement paca->in_mce. */ \ | |
420 | lhz r12,PACA_IN_MCE(r13); \ | |
421 | subi r12,r12,1; \ | |
422 | sth r12,PACA_IN_MCE(r13); \ | |
423 | REST_GPR(11, r1); \ | |
424 | REST_2GPRS(12, r1); \ | |
425 | /* restore original r1. */ \ | |
426 | ld r1,GPR1(r1) | |
427 | ||
1945bc45 NP |
428 | #ifdef CONFIG_PPC_P7_NAP |
429 | /* | |
430 | * This is an idle wakeup. Low level machine check has already been | |
431 | * done. Queue the event then call the idle code to do the wake up. | |
432 | */ | |
433 | EXC_COMMON_BEGIN(machine_check_idle_common) | |
434 | bl machine_check_queue_event | |
435 | ||
436 | /* | |
437 | * We have not used any non-volatile GPRs here, and as a rule | |
438 | * most exception code including machine check does not. | |
439 | * Therefore PACA_NAPSTATELOST does not need to be set. Idle | |
440 | * wakeup will restore volatile registers. | |
441 | * | |
442 | * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce. | |
443 | * | |
444 | * Then decrement MCE nesting after finishing with the stack. | |
445 | */ | |
446 | ld r3,_MSR(r1) | |
10d91611 | 447 | ld r4,_LINK(r1) |
1945bc45 NP |
448 | |
449 | lhz r11,PACA_IN_MCE(r13) | |
450 | subi r11,r11,1 | |
451 | sth r11,PACA_IN_MCE(r13) | |
452 | ||
10d91611 NP |
453 | mtlr r4 |
454 | rlwinm r10,r3,47-31,30,31 | |
455 | cmpwi cr1,r10,2 | |
456 | bltlr cr1 /* no state loss, return to idle caller */ | |
457 | b idle_return_gpr_loss | |
1945bc45 | 458 | #endif |
afcf0095 NP |
459 | /* |
460 | * Handle machine check early in real mode. We come here with | |
461 | * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. | |
462 | */ | |
463 | EXC_COMMON_BEGIN(machine_check_handle_early) | |
464 | std r0,GPR0(r1) /* Save r0 */ | |
465 | EXCEPTION_PROLOG_COMMON_3(0x200) | |
466 | bl save_nvgprs | |
467 | addi r3,r1,STACK_FRAME_OVERHEAD | |
468 | bl machine_check_early | |
469 | std r3,RESULT(r1) /* Save result */ | |
470 | ld r12,_MSR(r1) | |
db7d31ac MS |
471 | BEGIN_FTR_SECTION |
472 | b 4f | |
473 | END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE) | |
1945bc45 | 474 | |
afcf0095 NP |
475 | #ifdef CONFIG_PPC_P7_NAP |
476 | /* | |
477 | * Check if thread was in power saving mode. We come here when any | |
478 | * of the following is true: | |
479 | * a. thread wasn't in power saving mode | |
480 | * b. thread was in power saving mode with no state loss, | |
481 | * supervisor state loss or hypervisor state loss. | |
482 | * | |
483 | * Go back to nap/sleep/winkle mode again if (b) is true. | |
484 | */ | |
1945bc45 NP |
485 | BEGIN_FTR_SECTION |
486 | rlwinm. r11,r12,47-31,30,31 | |
6102c005 | 487 | bne machine_check_idle_common |
1945bc45 | 488 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
afcf0095 | 489 | #endif |
1945bc45 | 490 | |
afcf0095 NP |
491 | /* |
492 | * Check if we are coming from hypervisor userspace. If yes then we | |
493 | * continue in host kernel in V mode to deliver the MC event. | |
494 | */ | |
495 | rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ | |
496 | beq 5f | |
db7d31ac | 497 | 4: andi. r11,r12,MSR_PR /* See if coming from user. */ |
afcf0095 NP |
498 | bne 9f /* continue in V mode if we are. */ |
499 | ||
500 | 5: | |
501 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER | |
db7d31ac | 502 | BEGIN_FTR_SECTION |
afcf0095 NP |
503 | /* |
504 | * We are coming from kernel context. Check if we are coming from | |
505 | * guest. if yes, then we can continue. We will fall through | |
506 | * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. | |
507 | */ | |
508 | lbz r11,HSTATE_IN_GUEST(r13) | |
509 | cmpwi r11,0 /* Check if coming from guest */ | |
510 | bne 9f /* continue if we are. */ | |
db7d31ac | 511 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) |
afcf0095 NP |
512 | #endif |
513 | /* | |
514 | * At this point we are not sure about what context we come from. | |
515 | * Queue up the MCE event and return from the interrupt. | |
516 | * But before that, check if this is an un-recoverable exception. | |
517 | * If yes, then stay on emergency stack and panic. | |
518 | */ | |
519 | andi. r11,r12,MSR_RI | |
520 | bne 2f | |
521 | 1: mfspr r11,SPRN_SRR0 | |
522 | LOAD_HANDLER(r10,unrecover_mce) | |
523 | mtspr SPRN_SRR0,r10 | |
524 | ld r10,PACAKMSR(r13) | |
525 | /* | |
526 | * We are going down. But there are chances that we might get hit by | |
527 | * another MCE during panic path and we may run into unstable state | |
528 | * with no way out. Hence, turn ME bit off while going down, so that | |
529 | * when another MCE is hit during panic path, system will checkstop | |
530 | * and hypervisor will get restarted cleanly by SP. | |
531 | */ | |
532 | li r3,MSR_ME | |
533 | andc r10,r10,r3 /* Turn off MSR_ME */ | |
534 | mtspr SPRN_SRR1,r10 | |
222f20f1 | 535 | RFI_TO_KERNEL |
afcf0095 NP |
536 | b . |
537 | 2: | |
538 | /* | |
539 | * Check if we have successfully handled/recovered from error, if not | |
540 | * then stay on emergency stack and panic. | |
541 | */ | |
542 | ld r3,RESULT(r1) /* Load result */ | |
543 | cmpdi r3,0 /* see if we handled MCE successfully */ | |
544 | ||
545 | beq 1b /* if !handled then panic */ | |
db7d31ac | 546 | BEGIN_FTR_SECTION |
afcf0095 NP |
547 | /* |
548 | * Return from MC interrupt. | |
549 | * Queue up the MCE event so that we can log it later, while | |
550 | * returning from kernel or opal call. | |
551 | */ | |
552 | bl machine_check_queue_event | |
553 | MACHINE_CHECK_HANDLER_WINDUP | |
222f20f1 | 554 | RFI_TO_USER_OR_KERNEL |
db7d31ac MS |
555 | FTR_SECTION_ELSE |
556 | /* | |
557 | * pSeries: Return from MC interrupt. Before that stay on emergency | |
558 | * stack and call machine_check_exception to log the MCE event. | |
559 | */ | |
560 | LOAD_HANDLER(r10,mce_return) | |
561 | mtspr SPRN_SRR0,r10 | |
562 | ld r10,PACAKMSR(r13) | |
563 | mtspr SPRN_SRR1,r10 | |
564 | RFI_TO_KERNEL | |
565 | b . | |
566 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) | |
afcf0095 NP |
567 | 9: |
568 | /* Deliver the machine check to host kernel in V mode. */ | |
569 | MACHINE_CHECK_HANDLER_WINDUP | |
db7d31ac | 570 | SET_SCRATCH0(r13) /* save r13 */ |
5dba1d50 | 571 | EXCEPTION_PROLOG_0 PACA_EXMC |
db7d31ac | 572 | b machine_check_pSeries_0 |
afcf0095 NP |
573 | |
574 | EXC_COMMON_BEGIN(unrecover_mce) | |
575 | /* Invoke machine_check_exception to print MCE event and panic. */ | |
576 | addi r3,r1,STACK_FRAME_OVERHEAD | |
577 | bl machine_check_exception | |
578 | /* | |
579 | * We will not reach here. Even if we did, there is no way out. Call | |
580 | * unrecoverable_exception and die. | |
581 | */ | |
582 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
583 | bl unrecoverable_exception | |
584 | b 1b | |
585 | ||
a43c1590 MS |
586 | EXC_COMMON_BEGIN(mce_return) |
587 | /* Invoke machine_check_exception to print MCE event and return. */ | |
588 | addi r3,r1,STACK_FRAME_OVERHEAD | |
589 | bl machine_check_exception | |
db7d31ac | 590 | MACHINE_CHECK_HANDLER_WINDUP |
a43c1590 MS |
591 | RFI_TO_KERNEL |
592 | b . | |
0ebc4cda | 593 | |
e779fc93 NP |
594 | EXC_REAL_BEGIN(data_access, 0x300, 0x80) |
595 | SET_SCRATCH0(r13) /* save r13 */ | |
5dba1d50 | 596 | EXCEPTION_PROLOG_0 PACA_EXGEN |
e779fc93 NP |
597 | b tramp_real_data_access |
598 | EXC_REAL_END(data_access, 0x300, 0x80) | |
599 | ||
600 | TRAMP_REAL_BEGIN(tramp_real_data_access) | |
fa4cf6b7 | 601 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x300, 0 |
38555434 NP |
602 | /* |
603 | * DAR/DSISR must be read before setting MSR[RI], because | |
604 | * a d-side MCE will clobber those registers so is not | |
605 | * recoverable if they are live. | |
606 | */ | |
607 | mfspr r10,SPRN_DAR | |
608 | mfspr r11,SPRN_DSISR | |
609 | std r10,PACA_EXGEN+EX_DAR(r13) | |
610 | stw r11,PACA_EXGEN+EX_DSISR(r13) | |
2d046308 | 611 | EXCEPTION_PROLOG_2_REAL data_access_common, EXC_STD, 1 |
e779fc93 NP |
612 | |
613 | EXC_VIRT_BEGIN(data_access, 0x4300, 0x80) | |
614 | SET_SCRATCH0(r13) /* save r13 */ | |
5dba1d50 | 615 | EXCEPTION_PROLOG_0 PACA_EXGEN |
fa4cf6b7 | 616 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x300, 0 |
38555434 NP |
617 | mfspr r10,SPRN_DAR |
618 | mfspr r11,SPRN_DSISR | |
619 | std r10,PACA_EXGEN+EX_DAR(r13) | |
620 | stw r11,PACA_EXGEN+EX_DSISR(r13) | |
2d046308 | 621 | EXCEPTION_PROLOG_2_VIRT data_access_common, EXC_STD |
e779fc93 NP |
622 | EXC_VIRT_END(data_access, 0x4300, 0x80) |
623 | ||
80795e6c NP |
624 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x300) |
625 | ||
626 | EXC_COMMON_BEGIN(data_access_common) | |
627 | /* | |
628 | * Here r13 points to the paca, r9 contains the saved CR, | |
629 | * SRR0 and SRR1 are saved in r11 and r12, | |
630 | * r9 - r13 are saved in paca->exgen. | |
38555434 | 631 | * EX_DAR and EX_DSISR have saved DAR/DSISR |
80795e6c | 632 | */ |
80795e6c NP |
633 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) |
634 | RECONCILE_IRQ_STATE(r10, r11) | |
635 | ld r12,_MSR(r1) | |
636 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
637 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
638 | li r5,0x300 | |
639 | std r3,_DAR(r1) | |
640 | std r4,_DSISR(r1) | |
641 | BEGIN_MMU_FTR_SECTION | |
642 | b do_hash_page /* Try to handle as hpte fault */ | |
643 | MMU_FTR_SECTION_ELSE | |
644 | b handle_page_fault | |
645 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
646 | ||
0ebc4cda | 647 | |
1a6822d1 | 648 | EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80) |
e779fc93 | 649 | SET_SCRATCH0(r13) /* save r13 */ |
5dba1d50 | 650 | EXCEPTION_PROLOG_0 PACA_EXSLB |
e779fc93 | 651 | b tramp_real_data_access_slb |
1a6822d1 | 652 | EXC_REAL_END(data_access_slb, 0x380, 0x80) |
0ebc4cda | 653 | |
e779fc93 | 654 | TRAMP_REAL_BEGIN(tramp_real_data_access_slb) |
fa4cf6b7 | 655 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 1, 0x380, 0 |
38555434 NP |
656 | mfspr r10,SPRN_DAR |
657 | std r10,PACA_EXSLB+EX_DAR(r13) | |
2d046308 | 658 | EXCEPTION_PROLOG_2_REAL data_access_slb_common, EXC_STD, 1 |
e779fc93 | 659 | |
1a6822d1 | 660 | EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80) |
e779fc93 | 661 | SET_SCRATCH0(r13) /* save r13 */ |
5dba1d50 | 662 | EXCEPTION_PROLOG_0 PACA_EXSLB |
fa4cf6b7 | 663 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 0, 0x380, 0 |
38555434 NP |
664 | mfspr r10,SPRN_DAR |
665 | std r10,PACA_EXSLB+EX_DAR(r13) | |
2d046308 | 666 | EXCEPTION_PROLOG_2_VIRT data_access_slb_common, EXC_STD |
1a6822d1 | 667 | EXC_VIRT_END(data_access_slb, 0x4380, 0x80) |
48e7b769 | 668 | |
2b9af6e4 NP |
669 | TRAMP_KVM_SKIP(PACA_EXSLB, 0x380) |
670 | ||
48e7b769 | 671 | EXC_COMMON_BEGIN(data_access_slb_common) |
48e7b769 NP |
672 | EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB) |
673 | ld r4,PACA_EXSLB+EX_DAR(r13) | |
674 | std r4,_DAR(r1) | |
675 | addi r3,r1,STACK_FRAME_OVERHEAD | |
7100e870 NP |
676 | BEGIN_MMU_FTR_SECTION |
677 | /* HPT case, do SLB fault */ | |
48e7b769 NP |
678 | bl do_slb_fault |
679 | cmpdi r3,0 | |
680 | bne- 1f | |
681 | b fast_exception_return | |
682 | 1: /* Error case */ | |
7100e870 NP |
683 | MMU_FTR_SECTION_ELSE |
684 | /* Radix case, access is outside page table range */ | |
685 | li r3,-EFAULT | |
686 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
48e7b769 NP |
687 | std r3,RESULT(r1) |
688 | bl save_nvgprs | |
689 | RECONCILE_IRQ_STATE(r10, r11) | |
690 | ld r4,_DAR(r1) | |
691 | ld r5,RESULT(r1) | |
692 | addi r3,r1,STACK_FRAME_OVERHEAD | |
693 | bl do_bad_slb_fault | |
694 | b ret_from_except | |
695 | ||
2b9af6e4 | 696 | |
1a6822d1 NP |
697 | EXC_REAL(instruction_access, 0x400, 0x80) |
698 | EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400) | |
27ce77df NP |
699 | TRAMP_KVM(PACA_EXGEN, 0x400) |
700 | ||
701 | EXC_COMMON_BEGIN(instruction_access_common) | |
702 | EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) | |
703 | RECONCILE_IRQ_STATE(r10, r11) | |
704 | ld r12,_MSR(r1) | |
705 | ld r3,_NIP(r1) | |
475b581f | 706 | andis. r4,r12,DSISR_SRR1_MATCH_64S@h |
27ce77df NP |
707 | li r5,0x400 |
708 | std r3,_DAR(r1) | |
709 | std r4,_DSISR(r1) | |
710 | BEGIN_MMU_FTR_SECTION | |
711 | b do_hash_page /* Try to handle as hpte fault */ | |
712 | MMU_FTR_SECTION_ELSE | |
713 | b handle_page_fault | |
714 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
715 | ||
0ebc4cda | 716 | |
1a6822d1 | 717 | EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80) |
a7c1ca19 | 718 | EXCEPTION_PROLOG(PACA_EXSLB, instruction_access_slb_common, EXC_STD, 1, 0x480); |
1a6822d1 | 719 | EXC_REAL_END(instruction_access_slb, 0x480, 0x80) |
0ebc4cda | 720 | |
1a6822d1 | 721 | EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80) |
a7c1ca19 | 722 | EXCEPTION_RELON_PROLOG(PACA_EXSLB, instruction_access_slb_common, EXC_STD, 0, 0x480); |
1a6822d1 | 723 | EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80) |
54be0b9c | 724 | |
48e7b769 | 725 | TRAMP_KVM(PACA_EXSLB, 0x480) |
54be0b9c | 726 | |
48e7b769 NP |
727 | EXC_COMMON_BEGIN(instruction_access_slb_common) |
728 | EXCEPTION_PROLOG_COMMON(0x480, PACA_EXSLB) | |
729 | ld r4,_NIP(r1) | |
730 | addi r3,r1,STACK_FRAME_OVERHEAD | |
7100e870 NP |
731 | BEGIN_MMU_FTR_SECTION |
732 | /* HPT case, do SLB fault */ | |
48e7b769 NP |
733 | bl do_slb_fault |
734 | cmpdi r3,0 | |
735 | bne- 1f | |
736 | b fast_exception_return | |
737 | 1: /* Error case */ | |
7100e870 NP |
738 | MMU_FTR_SECTION_ELSE |
739 | /* Radix case, access is outside page table range */ | |
740 | li r3,-EFAULT | |
741 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
48e7b769 | 742 | std r3,RESULT(r1) |
8d04631a | 743 | bl save_nvgprs |
8d04631a | 744 | RECONCILE_IRQ_STATE(r10, r11) |
48e7b769 NP |
745 | ld r4,_NIP(r1) |
746 | ld r5,RESULT(r1) | |
747 | addi r3,r1,STACK_FRAME_OVERHEAD | |
748 | bl do_bad_slb_fault | |
8d04631a NP |
749 | b ret_from_except |
750 | ||
48e7b769 | 751 | |
1a6822d1 | 752 | EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100) |
b3e6b5df | 753 | .globl hardware_interrupt_hv; |
b3e6b5df | 754 | hardware_interrupt_hv: |
a5d4f3ad | 755 | BEGIN_FTR_SECTION |
0b924de4 | 756 | MASKABLE_EXCEPTION_HV(0x500, hardware_interrupt_common, IRQS_DISABLED) |
de56a948 | 757 | FTR_SECTION_ELSE |
0b924de4 | 758 | MASKABLE_EXCEPTION(0x500, hardware_interrupt_common, IRQS_DISABLED) |
969391c5 | 759 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
1a6822d1 | 760 | EXC_REAL_END(hardware_interrupt, 0x500, 0x100) |
da2bc464 | 761 | |
1a6822d1 | 762 | EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100) |
c138e588 NP |
763 | .globl hardware_interrupt_relon_hv; |
764 | hardware_interrupt_relon_hv: | |
765 | BEGIN_FTR_SECTION | |
0b924de4 ME |
766 | MASKABLE_RELON_EXCEPTION_HV(0x500, hardware_interrupt_common, |
767 | IRQS_DISABLED) | |
c138e588 | 768 | FTR_SECTION_ELSE |
0a55c241 | 769 | __MASKABLE_RELON_EXCEPTION(0x500, hardware_interrupt_common, |
a7c1ca19 | 770 | EXC_STD, 1, IRQS_DISABLED) |
c138e588 | 771 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
1a6822d1 | 772 | EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100) |
c138e588 | 773 | |
7ede5317 NP |
774 | TRAMP_KVM(PACA_EXGEN, 0x500) |
775 | TRAMP_KVM_HV(PACA_EXGEN, 0x500) | |
c138e588 NP |
776 | EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) |
777 | ||
778 | ||
e779fc93 NP |
779 | EXC_REAL_BEGIN(alignment, 0x600, 0x100) |
780 | SET_SCRATCH0(r13) /* save r13 */ | |
5dba1d50 | 781 | EXCEPTION_PROLOG_0 PACA_EXGEN |
fa4cf6b7 | 782 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x600, 0 |
38555434 NP |
783 | mfspr r10,SPRN_DAR |
784 | mfspr r11,SPRN_DSISR | |
785 | std r10,PACA_EXGEN+EX_DAR(r13) | |
786 | stw r11,PACA_EXGEN+EX_DSISR(r13) | |
2d046308 | 787 | EXCEPTION_PROLOG_2_REAL alignment_common, EXC_STD, 1 |
e779fc93 NP |
788 | EXC_REAL_END(alignment, 0x600, 0x100) |
789 | ||
790 | EXC_VIRT_BEGIN(alignment, 0x4600, 0x100) | |
791 | SET_SCRATCH0(r13) /* save r13 */ | |
5dba1d50 | 792 | EXCEPTION_PROLOG_0 PACA_EXGEN |
fa4cf6b7 | 793 | EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x600, 0 |
38555434 NP |
794 | mfspr r10,SPRN_DAR |
795 | mfspr r11,SPRN_DSISR | |
796 | std r10,PACA_EXGEN+EX_DAR(r13) | |
797 | stw r11,PACA_EXGEN+EX_DSISR(r13) | |
2d046308 | 798 | EXCEPTION_PROLOG_2_VIRT alignment_common, EXC_STD |
e779fc93 NP |
799 | EXC_VIRT_END(alignment, 0x4600, 0x100) |
800 | ||
da2bc464 | 801 | TRAMP_KVM(PACA_EXGEN, 0x600) |
f9aa6714 | 802 | EXC_COMMON_BEGIN(alignment_common) |
f9aa6714 NP |
803 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) |
804 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
805 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
806 | std r3,_DAR(r1) | |
807 | std r4,_DSISR(r1) | |
808 | bl save_nvgprs | |
809 | RECONCILE_IRQ_STATE(r10, r11) | |
810 | addi r3,r1,STACK_FRAME_OVERHEAD | |
811 | bl alignment_exception | |
812 | b ret_from_except | |
813 | ||
da2bc464 | 814 | |
1a6822d1 NP |
815 | EXC_REAL(program_check, 0x700, 0x100) |
816 | EXC_VIRT(program_check, 0x4700, 0x100, 0x700) | |
da2bc464 | 817 | TRAMP_KVM(PACA_EXGEN, 0x700) |
11e87346 | 818 | EXC_COMMON_BEGIN(program_check_common) |
265e60a1 CB |
819 | /* |
820 | * It's possible to receive a TM Bad Thing type program check with | |
821 | * userspace register values (in particular r1), but with SRR1 reporting | |
822 | * that we came from the kernel. Normally that would confuse the bad | |
823 | * stack logic, and we would report a bad kernel stack pointer. Instead | |
824 | * we switch to the emergency stack if we're taking a TM Bad Thing from | |
825 | * the kernel. | |
826 | */ | |
827 | li r10,MSR_PR /* Build a mask of MSR_PR .. */ | |
828 | oris r10,r10,0x200000@h /* .. and SRR1_PROGTM */ | |
829 | and r10,r10,r12 /* Mask SRR1 with that. */ | |
830 | srdi r10,r10,8 /* Shift it so we can compare */ | |
831 | cmpldi r10,(0x200000 >> 8) /* .. with an immediate. */ | |
832 | bne 1f /* If != go to normal path. */ | |
833 | ||
834 | /* SRR1 had PR=0 and SRR1_PROGTM=1, so use the emergency stack */ | |
835 | andi. r10,r12,MSR_PR; /* Set CR0 correctly for label */ | |
836 | /* 3 in EXCEPTION_PROLOG_COMMON */ | |
837 | mr r10,r1 /* Save r1 */ | |
838 | ld r1,PACAEMERGSP(r13) /* Use emergency stack */ | |
839 | subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
840 | b 3f /* Jump into the macro !! */ | |
841 | 1: EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) | |
11e87346 NP |
842 | bl save_nvgprs |
843 | RECONCILE_IRQ_STATE(r10, r11) | |
844 | addi r3,r1,STACK_FRAME_OVERHEAD | |
845 | bl program_check_exception | |
846 | b ret_from_except | |
847 | ||
b01c8b54 | 848 | |
1a6822d1 NP |
849 | EXC_REAL(fp_unavailable, 0x800, 0x100) |
850 | EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800) | |
da2bc464 | 851 | TRAMP_KVM(PACA_EXGEN, 0x800) |
c78d9b97 NP |
852 | EXC_COMMON_BEGIN(fp_unavailable_common) |
853 | EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) | |
854 | bne 1f /* if from user, just load it up */ | |
855 | bl save_nvgprs | |
856 | RECONCILE_IRQ_STATE(r10, r11) | |
857 | addi r3,r1,STACK_FRAME_OVERHEAD | |
858 | bl kernel_fp_unavailable_exception | |
859 | BUG_OPCODE | |
860 | 1: | |
861 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
862 | BEGIN_FTR_SECTION | |
863 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
864 | * transaction), go do TM stuff | |
865 | */ | |
866 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
867 | bne- 2f | |
868 | END_FTR_SECTION_IFSET(CPU_FTR_TM) | |
869 | #endif | |
870 | bl load_up_fpu | |
871 | b fast_exception_return | |
872 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
873 | 2: /* User process was in a transaction */ | |
874 | bl save_nvgprs | |
875 | RECONCILE_IRQ_STATE(r10, r11) | |
876 | addi r3,r1,STACK_FRAME_OVERHEAD | |
877 | bl fp_unavailable_tm | |
878 | b ret_from_except | |
879 | #endif | |
880 | ||
a5d4f3ad | 881 | |
a048a07d | 882 | EXC_REAL_OOL_MASKABLE(decrementer, 0x900, 0x80, IRQS_DISABLED) |
f14e953b | 883 | EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900, IRQS_DISABLED) |
39c0da57 NP |
884 | TRAMP_KVM(PACA_EXGEN, 0x900) |
885 | EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) | |
886 | ||
a485c709 | 887 | |
1a6822d1 NP |
888 | EXC_REAL_HV(hdecrementer, 0x980, 0x80) |
889 | EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980) | |
facc6d74 NP |
890 | TRAMP_KVM_HV(PACA_EXGEN, 0x980) |
891 | EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) | |
892 | ||
a5d4f3ad | 893 | |
f14e953b MS |
894 | EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100, IRQS_DISABLED) |
895 | EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00, IRQS_DISABLED) | |
da2bc464 | 896 | TRAMP_KVM(PACA_EXGEN, 0xa00) |
ca243163 NP |
897 | #ifdef CONFIG_PPC_DOORBELL |
898 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) | |
899 | #else | |
900 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) | |
901 | #endif | |
902 | ||
0ebc4cda | 903 | |
1a6822d1 NP |
904 | EXC_REAL(trap_0b, 0xb00, 0x100) |
905 | EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00) | |
da2bc464 | 906 | TRAMP_KVM(PACA_EXGEN, 0xb00) |
341215dc NP |
907 | EXC_COMMON(trap_0b_common, 0xb00, unknown_exception) |
908 | ||
acd7d8ce NP |
909 | /* |
910 | * system call / hypercall (0xc00, 0x4c00) | |
911 | * | |
912 | * The system call exception is invoked with "sc 0" and does not alter HV bit. | |
913 | * There is support for kernel code to invoke system calls but there are no | |
914 | * in-tree users. | |
915 | * | |
916 | * The hypercall is invoked with "sc 1" and sets HV=1. | |
917 | * | |
918 | * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to | |
919 | * 0x4c00 virtual mode. | |
920 | * | |
921 | * Call convention: | |
922 | * | |
923 | * syscall register convention is in Documentation/powerpc/syscall64-abi.txt | |
924 | * | |
925 | * For hypercalls, the register convention is as follows: | |
926 | * r0 volatile | |
927 | * r1-2 nonvolatile | |
928 | * r3 volatile parameter and return value for status | |
929 | * r4-r10 volatile input and output value | |
930 | * r11 volatile hypercall number and output value | |
76fc0cfc | 931 | * r12 volatile input and output value |
acd7d8ce NP |
932 | * r13-r31 nonvolatile |
933 | * LR nonvolatile | |
934 | * CTR volatile | |
935 | * XER volatile | |
936 | * CR0-1 CR5-7 volatile | |
937 | * CR2-4 nonvolatile | |
938 | * Other registers nonvolatile | |
939 | * | |
940 | * The intersection of volatile registers that don't contain possible | |
76fc0cfc NP |
941 | * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry |
942 | * without saving, though xer is not a good idea to use, as hardware may | |
943 | * interpret some bits so it may be costly to change them. | |
acd7d8ce | 944 | */ |
bc355125 | 945 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
acd7d8ce NP |
946 | /* |
947 | * There is a little bit of juggling to get syscall and hcall | |
76fc0cfc NP |
948 | * working well. Save r13 in ctr to avoid using SPRG scratch |
949 | * register. | |
acd7d8ce NP |
950 | * |
951 | * Userspace syscalls have already saved the PPR, hcalls must save | |
952 | * it before setting HMT_MEDIUM. | |
953 | */ | |
bc355125 | 954 | #define SYSCALL_KVMTEST \ |
76fc0cfc | 955 | mtctr r13; \ |
bc355125 | 956 | GET_PACA(r13); \ |
76fc0cfc | 957 | std r10,PACA_EXGEN+EX_R10(r13); \ |
a048a07d | 958 | INTERRUPT_TO_KERNEL; \ |
a7c1ca19 | 959 | KVMTEST EXC_STD 0xc00 ; /* uses r10, branch to do_kvm_0xc00_system_call */ \ |
bc355125 | 960 | HMT_MEDIUM; \ |
76fc0cfc | 961 | mfctr r9; |
bc355125 PM |
962 | |
963 | #else | |
964 | #define SYSCALL_KVMTEST \ | |
acd7d8ce NP |
965 | HMT_MEDIUM; \ |
966 | mr r9,r13; \ | |
a048a07d NP |
967 | GET_PACA(r13); \ |
968 | INTERRUPT_TO_KERNEL; | |
bc355125 PM |
969 | #endif |
970 | ||
fb479e44 NP |
971 | #define LOAD_SYSCALL_HANDLER(reg) \ |
972 | __LOAD_HANDLER(reg, system_call_common) | |
d807ad37 | 973 | |
acd7d8ce NP |
974 | /* |
975 | * After SYSCALL_KVMTEST, we reach here with PACA in r13, r13 in r9, | |
976 | * and HMT_MEDIUM. | |
977 | */ | |
978 | #define SYSCALL_REAL \ | |
979 | mfspr r11,SPRN_SRR0 ; \ | |
d807ad37 NP |
980 | mfspr r12,SPRN_SRR1 ; \ |
981 | LOAD_SYSCALL_HANDLER(r10) ; \ | |
982 | mtspr SPRN_SRR0,r10 ; \ | |
983 | ld r10,PACAKMSR(r13) ; \ | |
984 | mtspr SPRN_SRR1,r10 ; \ | |
222f20f1 | 985 | RFI_TO_KERNEL ; \ |
d807ad37 NP |
986 | b . ; /* prevent speculative execution */ |
987 | ||
727f1361 | 988 | #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH |
5c2511bf ME |
989 | #define SYSCALL_FASTENDIAN_TEST \ |
990 | BEGIN_FTR_SECTION \ | |
991 | cmpdi r0,0x1ebe ; \ | |
992 | beq- 1f ; \ | |
993 | END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ | |
994 | ||
acd7d8ce | 995 | #define SYSCALL_FASTENDIAN \ |
d807ad37 NP |
996 | /* Fast LE/BE switch system call */ \ |
997 | 1: mfspr r12,SPRN_SRR1 ; \ | |
998 | xori r12,r12,MSR_LE ; \ | |
999 | mtspr SPRN_SRR1,r12 ; \ | |
acd7d8ce | 1000 | mr r13,r9 ; \ |
222f20f1 | 1001 | RFI_TO_USER ; /* return to userspace */ \ |
d807ad37 | 1002 | b . ; /* prevent speculative execution */ |
727f1361 ME |
1003 | #else |
1004 | #define SYSCALL_FASTENDIAN_TEST | |
1005 | #define SYSCALL_FASTENDIAN | |
1006 | #endif /* CONFIG_PPC_FAST_ENDIAN_SWITCH */ | |
d807ad37 NP |
1007 | |
1008 | #if defined(CONFIG_RELOCATABLE) | |
1009 | /* | |
1010 | * We can't branch directly so we do it via the CTR which | |
1011 | * is volatile across system calls. | |
1012 | */ | |
acd7d8ce NP |
1013 | #define SYSCALL_VIRT \ |
1014 | LOAD_SYSCALL_HANDLER(r10) ; \ | |
1015 | mtctr r10 ; \ | |
1016 | mfspr r11,SPRN_SRR0 ; \ | |
d807ad37 NP |
1017 | mfspr r12,SPRN_SRR1 ; \ |
1018 | li r10,MSR_RI ; \ | |
1019 | mtmsrd r10,1 ; \ | |
1020 | bctr ; | |
1021 | #else | |
1022 | /* We can branch directly */ | |
acd7d8ce NP |
1023 | #define SYSCALL_VIRT \ |
1024 | mfspr r11,SPRN_SRR0 ; \ | |
d807ad37 NP |
1025 | mfspr r12,SPRN_SRR1 ; \ |
1026 | li r10,MSR_RI ; \ | |
1027 | mtmsrd r10,1 ; /* Set RI (EE=0) */ \ | |
1028 | b system_call_common ; | |
1029 | #endif | |
1030 | ||
1a6822d1 | 1031 | EXC_REAL_BEGIN(system_call, 0xc00, 0x100) |
acd7d8ce NP |
1032 | SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */ |
1033 | SYSCALL_FASTENDIAN_TEST | |
1034 | SYSCALL_REAL | |
1035 | SYSCALL_FASTENDIAN | |
1a6822d1 | 1036 | EXC_REAL_END(system_call, 0xc00, 0x100) |
da2bc464 | 1037 | |
1a6822d1 | 1038 | EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100) |
acd7d8ce NP |
1039 | SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */ |
1040 | SYSCALL_FASTENDIAN_TEST | |
1041 | SYSCALL_VIRT | |
1042 | SYSCALL_FASTENDIAN | |
1a6822d1 | 1043 | EXC_VIRT_END(system_call, 0x4c00, 0x100) |
d807ad37 | 1044 | |
acd7d8ce NP |
1045 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
1046 | /* | |
1047 | * This is a hcall, so register convention is as above, with these | |
1048 | * differences: | |
1049 | * r13 = PACA | |
76fc0cfc NP |
1050 | * ctr = orig r13 |
1051 | * orig r10 saved in PACA | |
acd7d8ce NP |
1052 | */ |
1053 | TRAMP_KVM_BEGIN(do_kvm_0xc00) | |
1054 | /* | |
1055 | * Save the PPR (on systems that support it) before changing to | |
1056 | * HMT_MEDIUM. That allows the KVM code to save that value into the | |
1057 | * guest state (it is the guest's PPR value). | |
1058 | */ | |
76fc0cfc | 1059 | OPT_GET_SPR(r10, SPRN_PPR, CPU_FTR_HAS_PPR) |
acd7d8ce | 1060 | HMT_MEDIUM |
76fc0cfc | 1061 | OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r10, CPU_FTR_HAS_PPR) |
acd7d8ce | 1062 | mfctr r10 |
76fc0cfc | 1063 | SET_SCRATCH0(r10) |
acd7d8ce NP |
1064 | std r9,PACA_EXGEN+EX_R9(r13) |
1065 | mfcr r9 | |
17bdc064 | 1066 | KVM_HANDLER PACA_EXGEN, EXC_STD, 0xc00, 0 |
acd7d8ce | 1067 | #endif |
da2bc464 | 1068 | |
d807ad37 | 1069 | |
1a6822d1 NP |
1070 | EXC_REAL(single_step, 0xd00, 0x100) |
1071 | EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00) | |
da2bc464 | 1072 | TRAMP_KVM(PACA_EXGEN, 0xd00) |
bc6675c6 | 1073 | EXC_COMMON(single_step_common, 0xd00, single_step_exception) |
b01c8b54 | 1074 | |
1a6822d1 | 1075 | EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20) |
da0e7e62 | 1076 | EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00) |
f5c32c1d NP |
1077 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) |
1078 | EXC_COMMON_BEGIN(h_data_storage_common) | |
1079 | mfspr r10,SPRN_HDAR | |
1080 | std r10,PACA_EXGEN+EX_DAR(r13) | |
1081 | mfspr r10,SPRN_HDSISR | |
1082 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
1083 | EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) | |
1084 | bl save_nvgprs | |
1085 | RECONCILE_IRQ_STATE(r10, r11) | |
1086 | addi r3,r1,STACK_FRAME_OVERHEAD | |
d7b45615 SJS |
1087 | BEGIN_MMU_FTR_SECTION |
1088 | ld r4,PACA_EXGEN+EX_DAR(r13) | |
1089 | lwz r5,PACA_EXGEN+EX_DSISR(r13) | |
1090 | std r4,_DAR(r1) | |
1091 | std r5,_DSISR(r1) | |
1092 | li r5,SIGSEGV | |
1093 | bl bad_page_fault | |
1094 | MMU_FTR_SECTION_ELSE | |
f5c32c1d | 1095 | bl unknown_exception |
d7b45615 | 1096 | ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX) |
f5c32c1d | 1097 | b ret_from_except |
f5c32c1d | 1098 | |
1707dd16 | 1099 | |
1a6822d1 | 1100 | EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20) |
da0e7e62 | 1101 | EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20) |
82517cab NP |
1102 | TRAMP_KVM_HV(PACA_EXGEN, 0xe20) |
1103 | EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) | |
1104 | ||
1707dd16 | 1105 | |
1a6822d1 NP |
1106 | EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20) |
1107 | EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40) | |
031b4026 NP |
1108 | TRAMP_KVM_HV(PACA_EXGEN, 0xe40) |
1109 | EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) | |
1110 | ||
1707dd16 | 1111 | |
e0319829 NP |
1112 | /* |
1113 | * hmi_exception trampoline is a special case. It jumps to hmi_exception_early | |
1114 | * first, and then eventaully from there to the trampoline to get into virtual | |
1115 | * mode. | |
1116 | */ | |
1a6822d1 | 1117 | __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early) |
f14e953b | 1118 | __TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60, IRQS_DISABLED) |
1a6822d1 | 1119 | EXC_VIRT_NONE(0x4e60, 0x20) |
62f9b03b NP |
1120 | TRAMP_KVM_HV(PACA_EXGEN, 0xe60) |
1121 | TRAMP_REAL_BEGIN(hmi_exception_early) | |
fa4cf6b7 | 1122 | EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0xe60, 0 |
a4087a4d NP |
1123 | mr r10,r1 /* Save r1 */ |
1124 | ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */ | |
62f9b03b | 1125 | subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ |
62f9b03b | 1126 | mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ |
a4087a4d NP |
1127 | mfspr r12,SPRN_HSRR1 /* Save HSRR1 */ |
1128 | EXCEPTION_PROLOG_COMMON_1() | |
890274c2 | 1129 | /* We don't touch AMR here, we never go to virtual mode */ |
62f9b03b NP |
1130 | EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) |
1131 | EXCEPTION_PROLOG_COMMON_3(0xe60) | |
1132 | addi r3,r1,STACK_FRAME_OVERHEAD | |
505a314f | 1133 | BRANCH_LINK_TO_FAR(DOTSYM(hmi_exception_realmode)) /* Function call ABI */ |
5080332c MN |
1134 | cmpdi cr0,r3,0 |
1135 | ||
62f9b03b NP |
1136 | /* Windup the stack. */ |
1137 | /* Move original HSRR0 and HSRR1 into the respective regs */ | |
1138 | ld r9,_MSR(r1) | |
1139 | mtspr SPRN_HSRR1,r9 | |
1140 | ld r3,_NIP(r1) | |
1141 | mtspr SPRN_HSRR0,r3 | |
1142 | ld r9,_CTR(r1) | |
1143 | mtctr r9 | |
1144 | ld r9,_XER(r1) | |
1145 | mtxer r9 | |
1146 | ld r9,_LINK(r1) | |
1147 | mtlr r9 | |
1148 | REST_GPR(0, r1) | |
1149 | REST_8GPRS(2, r1) | |
1150 | REST_GPR(10, r1) | |
1151 | ld r11,_CCR(r1) | |
5080332c MN |
1152 | REST_2GPRS(12, r1) |
1153 | bne 1f | |
62f9b03b NP |
1154 | mtcr r11 |
1155 | REST_GPR(11, r1) | |
5080332c | 1156 | ld r1,GPR1(r1) |
222f20f1 | 1157 | HRFI_TO_USER_OR_KERNEL |
5080332c MN |
1158 | |
1159 | 1: mtcr r11 | |
1160 | REST_GPR(11, r1) | |
62f9b03b NP |
1161 | ld r1,GPR1(r1) |
1162 | ||
1163 | /* | |
1164 | * Go to virtual mode and pull the HMI event information from | |
1165 | * firmware. | |
1166 | */ | |
1167 | .globl hmi_exception_after_realmode | |
1168 | hmi_exception_after_realmode: | |
1169 | SET_SCRATCH0(r13) | |
5dba1d50 | 1170 | EXCEPTION_PROLOG_0 PACA_EXGEN |
62f9b03b NP |
1171 | b tramp_real_hmi_exception |
1172 | ||
5080332c MN |
1173 | EXC_COMMON_BEGIN(hmi_exception_common) |
1174 | EXCEPTION_COMMON(PACA_EXGEN, 0xe60, hmi_exception_common, handle_hmi_exception, | |
1175 | ret_from_except, FINISH_NAP;ADD_NVGPRS;ADD_RECONCILE;RUNLATCH_ON) | |
1707dd16 | 1176 | |
f14e953b MS |
1177 | EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20, IRQS_DISABLED) |
1178 | EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80, IRQS_DISABLED) | |
9bcb81bf NP |
1179 | TRAMP_KVM_HV(PACA_EXGEN, 0xe80) |
1180 | #ifdef CONFIG_PPC_DOORBELL | |
1181 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) | |
1182 | #else | |
1183 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) | |
1184 | #endif | |
1185 | ||
0ebc4cda | 1186 | |
f14e953b MS |
1187 | EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20, IRQS_DISABLED) |
1188 | EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0, IRQS_DISABLED) | |
74408776 NP |
1189 | TRAMP_KVM_HV(PACA_EXGEN, 0xea0) |
1190 | EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) | |
1191 | ||
9baaef0a | 1192 | |
1a6822d1 NP |
1193 | EXC_REAL_NONE(0xec0, 0x20) |
1194 | EXC_VIRT_NONE(0x4ec0, 0x20) | |
1195 | EXC_REAL_NONE(0xee0, 0x20) | |
1196 | EXC_VIRT_NONE(0x4ee0, 0x20) | |
bda7fea2 | 1197 | |
0ebc4cda | 1198 | |
f442d004 MS |
1199 | EXC_REAL_OOL_MASKABLE(performance_monitor, 0xf00, 0x20, IRQS_PMI_DISABLED) |
1200 | EXC_VIRT_OOL_MASKABLE(performance_monitor, 0x4f00, 0x20, 0xf00, IRQS_PMI_DISABLED) | |
b1c7f150 NP |
1201 | TRAMP_KVM(PACA_EXGEN, 0xf00) |
1202 | EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) | |
1203 | ||
0ebc4cda | 1204 | |
1a6822d1 NP |
1205 | EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20) |
1206 | EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20) | |
d1a0ca9c NP |
1207 | TRAMP_KVM(PACA_EXGEN, 0xf20) |
1208 | EXC_COMMON_BEGIN(altivec_unavailable_common) | |
1209 | EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) | |
1210 | #ifdef CONFIG_ALTIVEC | |
1211 | BEGIN_FTR_SECTION | |
1212 | beq 1f | |
1213 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1214 | BEGIN_FTR_SECTION_NESTED(69) | |
1215 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1216 | * transaction), go do TM stuff | |
1217 | */ | |
1218 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1219 | bne- 2f | |
1220 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1221 | #endif | |
1222 | bl load_up_altivec | |
1223 | b fast_exception_return | |
1224 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1225 | 2: /* User process was in a transaction */ | |
1226 | bl save_nvgprs | |
1227 | RECONCILE_IRQ_STATE(r10, r11) | |
1228 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1229 | bl altivec_unavailable_tm | |
1230 | b ret_from_except | |
1231 | #endif | |
1232 | 1: | |
1233 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1234 | #endif | |
1235 | bl save_nvgprs | |
1236 | RECONCILE_IRQ_STATE(r10, r11) | |
1237 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1238 | bl altivec_unavailable_exception | |
1239 | b ret_from_except | |
1240 | ||
0ebc4cda | 1241 | |
1a6822d1 NP |
1242 | EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20) |
1243 | EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40) | |
792cbddd NP |
1244 | TRAMP_KVM(PACA_EXGEN, 0xf40) |
1245 | EXC_COMMON_BEGIN(vsx_unavailable_common) | |
1246 | EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) | |
1247 | #ifdef CONFIG_VSX | |
1248 | BEGIN_FTR_SECTION | |
1249 | beq 1f | |
1250 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1251 | BEGIN_FTR_SECTION_NESTED(69) | |
1252 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1253 | * transaction), go do TM stuff | |
1254 | */ | |
1255 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1256 | bne- 2f | |
1257 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1258 | #endif | |
1259 | b load_up_vsx | |
1260 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1261 | 2: /* User process was in a transaction */ | |
1262 | bl save_nvgprs | |
1263 | RECONCILE_IRQ_STATE(r10, r11) | |
1264 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1265 | bl vsx_unavailable_tm | |
1266 | b ret_from_except | |
1267 | #endif | |
1268 | 1: | |
1269 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
1270 | #endif | |
1271 | bl save_nvgprs | |
1272 | RECONCILE_IRQ_STATE(r10, r11) | |
1273 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1274 | bl vsx_unavailable_exception | |
1275 | b ret_from_except | |
1276 | ||
da2bc464 | 1277 | |
1a6822d1 NP |
1278 | EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20) |
1279 | EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60) | |
1134713c NP |
1280 | TRAMP_KVM(PACA_EXGEN, 0xf60) |
1281 | EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) | |
1282 | ||
da2bc464 | 1283 | |
1a6822d1 NP |
1284 | EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20) |
1285 | EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80) | |
14b0072c NP |
1286 | TRAMP_KVM_HV(PACA_EXGEN, 0xf80) |
1287 | EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) | |
1288 | ||
da2bc464 | 1289 | |
1a6822d1 NP |
1290 | EXC_REAL_NONE(0xfa0, 0x20) |
1291 | EXC_VIRT_NONE(0x4fa0, 0x20) | |
1292 | EXC_REAL_NONE(0xfc0, 0x20) | |
1293 | EXC_VIRT_NONE(0x4fc0, 0x20) | |
1294 | EXC_REAL_NONE(0xfe0, 0x20) | |
1295 | EXC_VIRT_NONE(0x4fe0, 0x20) | |
1296 | ||
1297 | EXC_REAL_NONE(0x1000, 0x100) | |
1298 | EXC_VIRT_NONE(0x5000, 0x100) | |
1299 | EXC_REAL_NONE(0x1100, 0x100) | |
1300 | EXC_VIRT_NONE(0x5100, 0x100) | |
d0c0c9a1 | 1301 | |
0ebc4cda | 1302 | #ifdef CONFIG_CBE_RAS |
1a6822d1 NP |
1303 | EXC_REAL_HV(cbe_system_error, 0x1200, 0x100) |
1304 | EXC_VIRT_NONE(0x5200, 0x100) | |
da2bc464 | 1305 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) |
ff1b3206 | 1306 | EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) |
da2bc464 | 1307 | #else /* CONFIG_CBE_RAS */ |
1a6822d1 NP |
1308 | EXC_REAL_NONE(0x1200, 0x100) |
1309 | EXC_VIRT_NONE(0x5200, 0x100) | |
da2bc464 | 1310 | #endif |
b01c8b54 | 1311 | |
ff1b3206 | 1312 | |
1a6822d1 NP |
1313 | EXC_REAL(instruction_breakpoint, 0x1300, 0x100) |
1314 | EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300) | |
da2bc464 | 1315 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) |
4e96dbbf NP |
1316 | EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) |
1317 | ||
1a6822d1 NP |
1318 | EXC_REAL_NONE(0x1400, 0x100) |
1319 | EXC_VIRT_NONE(0x5400, 0x100) | |
da2bc464 | 1320 | |
1a6822d1 | 1321 | EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100) |
b92a66a6 | 1322 | mtspr SPRN_SPRG_HSCRATCH0,r13 |
5dba1d50 | 1323 | EXCEPTION_PROLOG_0 PACA_EXGEN |
fa4cf6b7 | 1324 | EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 0, 0x1500, 0 |
b92a66a6 MN |
1325 | |
1326 | #ifdef CONFIG_PPC_DENORMALISATION | |
1327 | mfspr r10,SPRN_HSRR1 | |
afcf0095 | 1328 | andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ |
afcf0095 NP |
1329 | bne+ denorm_assist |
1330 | #endif | |
1e9b4507 | 1331 | |
a7c1ca19 | 1332 | KVMTEST EXC_HV 0x1500 |
2d046308 | 1333 | EXCEPTION_PROLOG_2_REAL denorm_common, EXC_HV, 1 |
1a6822d1 | 1334 | EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100) |
a74599a5 | 1335 | |
d7e89849 | 1336 | #ifdef CONFIG_PPC_DENORMALISATION |
1a6822d1 | 1337 | EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100) |
d7e89849 | 1338 | b exc_real_0x1500_denorm_exception_hv |
1a6822d1 | 1339 | EXC_VIRT_END(denorm_exception, 0x5500, 0x100) |
d7e89849 | 1340 | #else |
1a6822d1 | 1341 | EXC_VIRT_NONE(0x5500, 0x100) |
afcf0095 NP |
1342 | #endif |
1343 | ||
4bb3c7a0 | 1344 | TRAMP_KVM_HV(PACA_EXGEN, 0x1500) |
b01c8b54 | 1345 | |
b92a66a6 | 1346 | #ifdef CONFIG_PPC_DENORMALISATION |
da2bc464 | 1347 | TRAMP_REAL_BEGIN(denorm_assist) |
b92a66a6 MN |
1348 | BEGIN_FTR_SECTION |
1349 | /* | |
1350 | * To denormalise we need to move a copy of the register to itself. | |
1351 | * For POWER6 do that here for all FP regs. | |
1352 | */ | |
1353 | mfmsr r10 | |
1354 | ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) | |
1355 | xori r10,r10,(MSR_FE0|MSR_FE1) | |
1356 | mtmsrd r10 | |
1357 | sync | |
d7c67fb1 MN |
1358 | |
1359 | #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1 | |
1360 | #define FMR4(n) FMR2(n) ; FMR2(n+2) | |
1361 | #define FMR8(n) FMR4(n) ; FMR4(n+4) | |
1362 | #define FMR16(n) FMR8(n) ; FMR8(n+8) | |
1363 | #define FMR32(n) FMR16(n) ; FMR16(n+16) | |
1364 | FMR32(0) | |
1365 | ||
b92a66a6 MN |
1366 | FTR_SECTION_ELSE |
1367 | /* | |
1368 | * To denormalise we need to move a copy of the register to itself. | |
1369 | * For POWER7 do that here for the first 32 VSX registers only. | |
1370 | */ | |
1371 | mfmsr r10 | |
1372 | oris r10,r10,MSR_VSX@h | |
1373 | mtmsrd r10 | |
1374 | sync | |
d7c67fb1 MN |
1375 | |
1376 | #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1) | |
1377 | #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2) | |
1378 | #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4) | |
1379 | #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8) | |
1380 | #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16) | |
1381 | XVCPSGNDP32(0) | |
1382 | ||
b92a66a6 | 1383 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) |
fb0fce3e MN |
1384 | |
1385 | BEGIN_FTR_SECTION | |
1386 | b denorm_done | |
1387 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
1388 | /* | |
1389 | * To denormalise we need to move a copy of the register to itself. | |
1390 | * For POWER8 we need to do that for all 64 VSX registers | |
1391 | */ | |
1392 | XVCPSGNDP32(32) | |
1393 | denorm_done: | |
f14040bc MN |
1394 | mfspr r11,SPRN_HSRR0 |
1395 | subi r11,r11,4 | |
b92a66a6 MN |
1396 | mtspr SPRN_HSRR0,r11 |
1397 | mtcrf 0x80,r9 | |
1398 | ld r9,PACA_EXGEN+EX_R9(r13) | |
44e9309f | 1399 | RESTORE_PPR_PACA(PACA_EXGEN, r10) |
630573c1 PM |
1400 | BEGIN_FTR_SECTION |
1401 | ld r10,PACA_EXGEN+EX_CFAR(r13) | |
1402 | mtspr SPRN_CFAR,r10 | |
1403 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
b92a66a6 MN |
1404 | ld r10,PACA_EXGEN+EX_R10(r13) |
1405 | ld r11,PACA_EXGEN+EX_R11(r13) | |
1406 | ld r12,PACA_EXGEN+EX_R12(r13) | |
1407 | ld r13,PACA_EXGEN+EX_R13(r13) | |
222f20f1 | 1408 | HRFI_TO_UNKNOWN |
b92a66a6 MN |
1409 | b . |
1410 | #endif | |
1411 | ||
872e2ae4 | 1412 | EXC_COMMON(denorm_common, 0x1500, unknown_exception) |
d7e89849 NP |
1413 | |
1414 | ||
1415 | #ifdef CONFIG_CBE_RAS | |
1a6822d1 NP |
1416 | EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100) |
1417 | EXC_VIRT_NONE(0x5600, 0x100) | |
d7e89849 | 1418 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) |
69a79344 | 1419 | EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) |
d7e89849 | 1420 | #else /* CONFIG_CBE_RAS */ |
1a6822d1 NP |
1421 | EXC_REAL_NONE(0x1600, 0x100) |
1422 | EXC_VIRT_NONE(0x5600, 0x100) | |
d7e89849 NP |
1423 | #endif |
1424 | ||
69a79344 | 1425 | |
1a6822d1 NP |
1426 | EXC_REAL(altivec_assist, 0x1700, 0x100) |
1427 | EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700) | |
d7e89849 | 1428 | TRAMP_KVM(PACA_EXGEN, 0x1700) |
b51c079e NP |
1429 | #ifdef CONFIG_ALTIVEC |
1430 | EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) | |
1431 | #else | |
1432 | EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) | |
1433 | #endif | |
1434 | ||
d7e89849 NP |
1435 | |
1436 | #ifdef CONFIG_CBE_RAS | |
1a6822d1 NP |
1437 | EXC_REAL_HV(cbe_thermal, 0x1800, 0x100) |
1438 | EXC_VIRT_NONE(0x5800, 0x100) | |
d7e89849 | 1439 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) |
3965f8ab | 1440 | EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) |
d7e89849 | 1441 | #else /* CONFIG_CBE_RAS */ |
1a6822d1 NP |
1442 | EXC_REAL_NONE(0x1800, 0x100) |
1443 | EXC_VIRT_NONE(0x5800, 0x100) | |
d7e89849 NP |
1444 | #endif |
1445 | ||
75eb767e | 1446 | #ifdef CONFIG_PPC_WATCHDOG |
2104180a NP |
1447 | |
1448 | #define MASKED_DEC_HANDLER_LABEL 3f | |
1449 | ||
1450 | #define MASKED_DEC_HANDLER(_H) \ | |
1451 | 3: /* soft-nmi */ \ | |
1452 | std r12,PACA_EXGEN+EX_R12(r13); \ | |
1453 | GET_SCRATCH0(r10); \ | |
1454 | std r10,PACA_EXGEN+EX_R13(r13); \ | |
2d046308 | 1455 | EXCEPTION_PROLOG_2_REAL soft_nmi_common, _H, 1 |
2104180a | 1456 | |
cc491f1d NP |
1457 | /* |
1458 | * Branch to soft_nmi_interrupt using the emergency stack. The emergency | |
1459 | * stack is one that is usable by maskable interrupts so long as MSR_EE | |
1460 | * remains off. It is used for recovery when something has corrupted the | |
1461 | * normal kernel stack, for example. The "soft NMI" must not use the process | |
1462 | * stack because we want irq disabled sections to avoid touching the stack | |
1463 | * at all (other than PMU interrupts), so use the emergency stack for this, | |
1464 | * and run it entirely with interrupts hard disabled. | |
1465 | */ | |
2104180a NP |
1466 | EXC_COMMON_BEGIN(soft_nmi_common) |
1467 | mr r10,r1 | |
1468 | ld r1,PACAEMERGSP(r13) | |
2104180a NP |
1469 | subi r1,r1,INT_FRAME_SIZE |
1470 | EXCEPTION_COMMON_NORET_STACK(PACA_EXGEN, 0x900, | |
1471 | system_reset, soft_nmi_interrupt, | |
1472 | ADD_NVGPRS;ADD_RECONCILE) | |
1473 | b ret_from_except | |
1474 | ||
75eb767e | 1475 | #else /* CONFIG_PPC_WATCHDOG */ |
2104180a NP |
1476 | #define MASKED_DEC_HANDLER_LABEL 2f /* normal return */ |
1477 | #define MASKED_DEC_HANDLER(_H) | |
75eb767e | 1478 | #endif /* CONFIG_PPC_WATCHDOG */ |
d7e89849 | 1479 | |
0ebc4cda | 1480 | /* |
fe9e1d54 IM |
1481 | * An interrupt came in while soft-disabled. We set paca->irq_happened, then: |
1482 | * - If it was a decrementer interrupt, we bump the dec to max and and return. | |
1483 | * - If it was a doorbell we return immediately since doorbells are edge | |
1484 | * triggered and won't automatically refire. | |
0869b6fd MS |
1485 | * - If it was a HMI we return immediately since we handled it in realmode |
1486 | * and it won't refire. | |
6cc3f91b | 1487 | * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return. |
fe9e1d54 | 1488 | * This is called with r10 containing the value to OR to the paca field. |
0ebc4cda | 1489 | */ |
4508a74a NP |
1490 | .macro MASKED_INTERRUPT hsrr |
1491 | .if \hsrr | |
1492 | masked_Hinterrupt: | |
1493 | .else | |
1494 | masked_interrupt: | |
1495 | .endif | |
1496 | std r11,PACA_EXGEN+EX_R11(r13) | |
1497 | lbz r11,PACAIRQHAPPENED(r13) | |
1498 | or r11,r11,r10 | |
1499 | stb r11,PACAIRQHAPPENED(r13) | |
1500 | cmpwi r10,PACA_IRQ_DEC | |
1501 | bne 1f | |
1502 | lis r10,0x7fff | |
1503 | ori r10,r10,0xffff | |
1504 | mtspr SPRN_DEC,r10 | |
1505 | b MASKED_DEC_HANDLER_LABEL | |
1506 | 1: andi. r10,r10,PACA_IRQ_MUST_HARD_MASK | |
1507 | beq 2f | |
1508 | .if \hsrr | |
1509 | mfspr r10,SPRN_HSRR1 | |
1510 | xori r10,r10,MSR_EE /* clear MSR_EE */ | |
1511 | mtspr SPRN_HSRR1,r10 | |
1512 | .else | |
1513 | mfspr r10,SPRN_SRR1 | |
1514 | xori r10,r10,MSR_EE /* clear MSR_EE */ | |
1515 | mtspr SPRN_SRR1,r10 | |
1516 | .endif | |
1517 | ori r11,r11,PACA_IRQ_HARD_DIS | |
1518 | stb r11,PACAIRQHAPPENED(r13) | |
1519 | 2: /* done */ | |
1520 | mtcrf 0x80,r9 | |
1521 | std r1,PACAR1(r13) | |
1522 | ld r9,PACA_EXGEN+EX_R9(r13) | |
1523 | ld r10,PACA_EXGEN+EX_R10(r13) | |
1524 | ld r11,PACA_EXGEN+EX_R11(r13) | |
1525 | /* returns to kernel where r13 must be set up, so don't restore it */ | |
1526 | .if \hsrr | |
1527 | HRFI_TO_KERNEL | |
1528 | .else | |
1529 | RFI_TO_KERNEL | |
1530 | .endif | |
1531 | b . | |
1532 | MASKED_DEC_HANDLER(\hsrr\()) | |
1533 | .endm | |
57f26649 | 1534 | |
a048a07d NP |
1535 | TRAMP_REAL_BEGIN(stf_barrier_fallback) |
1536 | std r9,PACA_EXRFI+EX_R9(r13) | |
1537 | std r10,PACA_EXRFI+EX_R10(r13) | |
1538 | sync | |
1539 | ld r9,PACA_EXRFI+EX_R9(r13) | |
1540 | ld r10,PACA_EXRFI+EX_R10(r13) | |
1541 | ori 31,31,0 | |
1542 | .rept 14 | |
1543 | b 1f | |
1544 | 1: | |
1545 | .endr | |
1546 | blr | |
1547 | ||
aa8a5e00 ME |
1548 | TRAMP_REAL_BEGIN(rfi_flush_fallback) |
1549 | SET_SCRATCH0(r13); | |
1550 | GET_PACA(r13); | |
78ee9946 ME |
1551 | std r1,PACA_EXRFI+EX_R12(r13) |
1552 | ld r1,PACAKSAVE(r13) | |
aa8a5e00 ME |
1553 | std r9,PACA_EXRFI+EX_R9(r13) |
1554 | std r10,PACA_EXRFI+EX_R10(r13) | |
1555 | std r11,PACA_EXRFI+EX_R11(r13) | |
aa8a5e00 ME |
1556 | mfctr r9 |
1557 | ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) | |
bdcb1aef NP |
1558 | ld r11,PACA_L1D_FLUSH_SIZE(r13) |
1559 | srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ | |
aa8a5e00 | 1560 | mtctr r11 |
15a3204d | 1561 | DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ |
aa8a5e00 ME |
1562 | |
1563 | /* order ld/st prior to dcbt stop all streams with flushing */ | |
1564 | sync | |
bdcb1aef NP |
1565 | |
1566 | /* | |
1567 | * The load adresses are at staggered offsets within cachelines, | |
1568 | * which suits some pipelines better (on others it should not | |
1569 | * hurt). | |
1570 | */ | |
1571 | 1: | |
1572 | ld r11,(0x80 + 8)*0(r10) | |
1573 | ld r11,(0x80 + 8)*1(r10) | |
1574 | ld r11,(0x80 + 8)*2(r10) | |
1575 | ld r11,(0x80 + 8)*3(r10) | |
1576 | ld r11,(0x80 + 8)*4(r10) | |
1577 | ld r11,(0x80 + 8)*5(r10) | |
1578 | ld r11,(0x80 + 8)*6(r10) | |
1579 | ld r11,(0x80 + 8)*7(r10) | |
1580 | addi r10,r10,0x80*8 | |
aa8a5e00 ME |
1581 | bdnz 1b |
1582 | ||
1583 | mtctr r9 | |
1584 | ld r9,PACA_EXRFI+EX_R9(r13) | |
1585 | ld r10,PACA_EXRFI+EX_R10(r13) | |
1586 | ld r11,PACA_EXRFI+EX_R11(r13) | |
78ee9946 | 1587 | ld r1,PACA_EXRFI+EX_R12(r13) |
aa8a5e00 ME |
1588 | GET_SCRATCH0(r13); |
1589 | rfid | |
1590 | ||
1591 | TRAMP_REAL_BEGIN(hrfi_flush_fallback) | |
1592 | SET_SCRATCH0(r13); | |
1593 | GET_PACA(r13); | |
78ee9946 ME |
1594 | std r1,PACA_EXRFI+EX_R12(r13) |
1595 | ld r1,PACAKSAVE(r13) | |
aa8a5e00 ME |
1596 | std r9,PACA_EXRFI+EX_R9(r13) |
1597 | std r10,PACA_EXRFI+EX_R10(r13) | |
1598 | std r11,PACA_EXRFI+EX_R11(r13) | |
aa8a5e00 ME |
1599 | mfctr r9 |
1600 | ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) | |
bdcb1aef NP |
1601 | ld r11,PACA_L1D_FLUSH_SIZE(r13) |
1602 | srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ | |
aa8a5e00 | 1603 | mtctr r11 |
15a3204d | 1604 | DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ |
aa8a5e00 ME |
1605 | |
1606 | /* order ld/st prior to dcbt stop all streams with flushing */ | |
1607 | sync | |
bdcb1aef NP |
1608 | |
1609 | /* | |
1610 | * The load adresses are at staggered offsets within cachelines, | |
1611 | * which suits some pipelines better (on others it should not | |
1612 | * hurt). | |
1613 | */ | |
1614 | 1: | |
1615 | ld r11,(0x80 + 8)*0(r10) | |
1616 | ld r11,(0x80 + 8)*1(r10) | |
1617 | ld r11,(0x80 + 8)*2(r10) | |
1618 | ld r11,(0x80 + 8)*3(r10) | |
1619 | ld r11,(0x80 + 8)*4(r10) | |
1620 | ld r11,(0x80 + 8)*5(r10) | |
1621 | ld r11,(0x80 + 8)*6(r10) | |
1622 | ld r11,(0x80 + 8)*7(r10) | |
1623 | addi r10,r10,0x80*8 | |
aa8a5e00 ME |
1624 | bdnz 1b |
1625 | ||
1626 | mtctr r9 | |
1627 | ld r9,PACA_EXRFI+EX_R9(r13) | |
1628 | ld r10,PACA_EXRFI+EX_R10(r13) | |
1629 | ld r11,PACA_EXRFI+EX_R11(r13) | |
78ee9946 | 1630 | ld r1,PACA_EXRFI+EX_R12(r13) |
aa8a5e00 ME |
1631 | GET_SCRATCH0(r13); |
1632 | hrfid | |
1633 | ||
57f26649 NP |
1634 | /* |
1635 | * Real mode exceptions actually use this too, but alternate | |
1636 | * instruction code patches (which end up in the common .text area) | |
1637 | * cannot reach these if they are put there. | |
1638 | */ | |
1639 | USE_FIXED_SECTION(virt_trampolines) | |
4508a74a NP |
1640 | MASKED_INTERRUPT EXC_STD |
1641 | MASKED_INTERRUPT EXC_HV | |
0ebc4cda | 1642 | |
4f6c11db | 1643 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
da2bc464 | 1644 | TRAMP_REAL_BEGIN(kvmppc_skip_interrupt) |
4f6c11db PM |
1645 | /* |
1646 | * Here all GPRs are unchanged from when the interrupt happened | |
1647 | * except for r13, which is saved in SPRG_SCRATCH0. | |
1648 | */ | |
1649 | mfspr r13, SPRN_SRR0 | |
1650 | addi r13, r13, 4 | |
1651 | mtspr SPRN_SRR0, r13 | |
1652 | GET_SCRATCH0(r13) | |
222f20f1 | 1653 | RFI_TO_KERNEL |
4f6c11db PM |
1654 | b . |
1655 | ||
da2bc464 | 1656 | TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) |
4f6c11db PM |
1657 | /* |
1658 | * Here all GPRs are unchanged from when the interrupt happened | |
1659 | * except for r13, which is saved in SPRG_SCRATCH0. | |
1660 | */ | |
1661 | mfspr r13, SPRN_HSRR0 | |
1662 | addi r13, r13, 4 | |
1663 | mtspr SPRN_HSRR0, r13 | |
1664 | GET_SCRATCH0(r13) | |
222f20f1 | 1665 | HRFI_TO_KERNEL |
4f6c11db PM |
1666 | b . |
1667 | #endif | |
1668 | ||
0ebc4cda | 1669 | /* |
057b6d7e HB |
1670 | * Ensure that any handlers that get invoked from the exception prologs |
1671 | * above are below the first 64KB (0x10000) of the kernel image because | |
1672 | * the prologs assemble the addresses of these handlers using the | |
1673 | * LOAD_HANDLER macro, which uses an ori instruction. | |
0ebc4cda BH |
1674 | */ |
1675 | ||
1676 | /*** Common interrupt handlers ***/ | |
1677 | ||
0ebc4cda | 1678 | |
c1fb6816 MN |
1679 | /* |
1680 | * Relocation-on interrupts: A subset of the interrupts can be delivered | |
1681 | * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering | |
1682 | * it. Addresses are the same as the original interrupt addresses, but | |
1683 | * offset by 0xc000000000004000. | |
1684 | * It's impossible to receive interrupts below 0x300 via this mechanism. | |
1685 | * KVM: None of these traps are from the guest ; anything that escalated | |
1686 | * to HV=1 from HV=0 is delivered via real mode handlers. | |
1687 | */ | |
1688 | ||
1689 | /* | |
1690 | * This uses the standard macro, since the original 0x300 vector | |
1691 | * only has extra guff for STAB-based processors -- which never | |
1692 | * come here. | |
1693 | */ | |
da2bc464 | 1694 | |
57f26649 | 1695 | EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) |
b1576fec | 1696 | b __ppc64_runlatch_on |
fe1952fc | 1697 | |
57f26649 | 1698 | USE_FIXED_SECTION(virt_trampolines) |
8ed8ab40 HB |
1699 | /* |
1700 | * The __end_interrupts marker must be past the out-of-line (OOL) | |
1701 | * handlers, so that they are copied to real address 0x100 when running | |
1702 | * a relocatable kernel. This ensures they can be reached from the short | |
1703 | * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch | |
1704 | * directly, without using LOAD_HANDLER(). | |
1705 | */ | |
1706 | .align 7 | |
1707 | .globl __end_interrupts | |
1708 | __end_interrupts: | |
57f26649 | 1709 | DEFINE_FIXED_SYMBOL(__end_interrupts) |
61383407 | 1710 | |
087aa036 | 1711 | #ifdef CONFIG_PPC_970_NAP |
7c8cb4b5 | 1712 | EXC_COMMON_BEGIN(power4_fixup_nap) |
087aa036 CG |
1713 | andc r9,r9,r10 |
1714 | std r9,TI_LOCAL_FLAGS(r11) | |
1715 | ld r10,_LINK(r1) /* make idle task do the */ | |
1716 | std r10,_NIP(r1) /* equivalent of a blr */ | |
1717 | blr | |
1718 | #endif | |
1719 | ||
57f26649 NP |
1720 | CLOSE_FIXED_SECTION(real_vectors); |
1721 | CLOSE_FIXED_SECTION(real_trampolines); | |
1722 | CLOSE_FIXED_SECTION(virt_vectors); | |
1723 | CLOSE_FIXED_SECTION(virt_trampolines); | |
1724 | ||
1725 | USE_TEXT_SECTION() | |
1726 | ||
0ebc4cda BH |
1727 | /* |
1728 | * Hash table stuff | |
1729 | */ | |
f4329f2e | 1730 | .balign IFETCH_ALIGN_BYTES |
6a3bab90 | 1731 | do_hash_page: |
4e003747 | 1732 | #ifdef CONFIG_PPC_BOOK3S_64 |
e6c2a479 | 1733 | lis r0,(DSISR_BAD_FAULT_64S | DSISR_DABRMATCH | DSISR_KEYFAULT)@h |
398a719d BH |
1734 | ori r0,r0,DSISR_BAD_FAULT_64S@l |
1735 | and. r0,r4,r0 /* weird error? */ | |
0ebc4cda | 1736 | bne- handle_page_fault /* if not, try to insert a HPTE */ |
c911d2e1 | 1737 | ld r11, PACA_THREAD_INFO(r13) |
9c1e1052 PM |
1738 | lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ |
1739 | andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ | |
1740 | bne 77f /* then don't call hash_page now */ | |
0ebc4cda BH |
1741 | |
1742 | /* | |
1743 | * r3 contains the faulting address | |
106713a1 | 1744 | * r4 msr |
0ebc4cda | 1745 | * r5 contains the trap number |
aefa5688 | 1746 | * r6 contains dsisr |
0ebc4cda | 1747 | * |
7230c564 | 1748 | * at return r3 = 0 for success, 1 for page fault, negative for error |
0ebc4cda | 1749 | */ |
106713a1 | 1750 | mr r4,r12 |
aefa5688 | 1751 | ld r6,_DSISR(r1) |
106713a1 AK |
1752 | bl __hash_page /* build HPTE if possible */ |
1753 | cmpdi r3,0 /* see if __hash_page succeeded */ | |
0ebc4cda | 1754 | |
7230c564 | 1755 | /* Success */ |
0ebc4cda | 1756 | beq fast_exc_return_irq /* Return from exception on success */ |
0ebc4cda | 1757 | |
7230c564 BH |
1758 | /* Error */ |
1759 | blt- 13f | |
d89ba535 NR |
1760 | |
1761 | /* Reload DSISR into r4 for the DABR check below */ | |
1762 | ld r4,_DSISR(r1) | |
4e003747 | 1763 | #endif /* CONFIG_PPC_BOOK3S_64 */ |
9c7cc234 | 1764 | |
0ebc4cda BH |
1765 | /* Here we have a page fault that hash_page can't handle. */ |
1766 | handle_page_fault: | |
d89ba535 NR |
1767 | 11: andis. r0,r4,DSISR_DABRMATCH@h |
1768 | bne- handle_dabr_fault | |
1769 | ld r4,_DAR(r1) | |
0ebc4cda BH |
1770 | ld r5,_DSISR(r1) |
1771 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec | 1772 | bl do_page_fault |
0ebc4cda | 1773 | cmpdi r3,0 |
f474c28f | 1774 | beq+ ret_from_except_lite |
b1576fec | 1775 | bl save_nvgprs |
0ebc4cda BH |
1776 | mr r5,r3 |
1777 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1778 | lwz r4,_DAR(r1) | |
b1576fec AB |
1779 | bl bad_page_fault |
1780 | b ret_from_except | |
0ebc4cda | 1781 | |
a546498f BH |
1782 | /* We have a data breakpoint exception - handle it */ |
1783 | handle_dabr_fault: | |
b1576fec | 1784 | bl save_nvgprs |
a546498f BH |
1785 | ld r4,_DAR(r1) |
1786 | ld r5,_DSISR(r1) | |
1787 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec | 1788 | bl do_break |
f474c28f RB |
1789 | /* |
1790 | * do_break() may have changed the NV GPRS while handling a breakpoint. | |
1791 | * If so, we need to restore them with their updated values. Don't use | |
1792 | * ret_from_except_lite here. | |
1793 | */ | |
1794 | b ret_from_except | |
a546498f | 1795 | |
0ebc4cda | 1796 | |
4e003747 | 1797 | #ifdef CONFIG_PPC_BOOK3S_64 |
0ebc4cda BH |
1798 | /* We have a page fault that hash_page could handle but HV refused |
1799 | * the PTE insertion | |
1800 | */ | |
b1576fec | 1801 | 13: bl save_nvgprs |
0ebc4cda BH |
1802 | mr r5,r3 |
1803 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1804 | ld r4,_DAR(r1) | |
b1576fec AB |
1805 | bl low_hash_fault |
1806 | b ret_from_except | |
caca285e | 1807 | #endif |
0ebc4cda | 1808 | |
9c1e1052 PM |
1809 | /* |
1810 | * We come here as a result of a DSI at a point where we don't want | |
1811 | * to call hash_page, such as when we are accessing memory (possibly | |
1812 | * user memory) inside a PMU interrupt that occurred while interrupts | |
1813 | * were soft-disabled. We want to invoke the exception handler for | |
1814 | * the access, or panic if there isn't a handler. | |
1815 | */ | |
b1576fec | 1816 | 77: bl save_nvgprs |
9c1e1052 PM |
1817 | mr r4,r3 |
1818 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1819 | li r5,SIGSEGV | |
b1576fec AB |
1820 | bl bad_page_fault |
1821 | b ret_from_except | |
4e2bf01b ME |
1822 | |
1823 | /* | |
1824 | * Here we have detected that the kernel stack pointer is bad. | |
1825 | * R9 contains the saved CR, r13 points to the paca, | |
1826 | * r10 contains the (bad) kernel stack pointer, | |
1827 | * r11 and r12 contain the saved SRR0 and SRR1. | |
1828 | * We switch to using an emergency stack, save the registers there, | |
1829 | * and call kernel_bad_stack(), which panics. | |
1830 | */ | |
1831 | bad_stack: | |
1832 | ld r1,PACAEMERGSP(r13) | |
1833 | subi r1,r1,64+INT_FRAME_SIZE | |
1834 | std r9,_CCR(r1) | |
1835 | std r10,GPR1(r1) | |
1836 | std r11,_NIP(r1) | |
1837 | std r12,_MSR(r1) | |
1838 | mfspr r11,SPRN_DAR | |
1839 | mfspr r12,SPRN_DSISR | |
1840 | std r11,_DAR(r1) | |
1841 | std r12,_DSISR(r1) | |
1842 | mflr r10 | |
1843 | mfctr r11 | |
1844 | mfxer r12 | |
1845 | std r10,_LINK(r1) | |
1846 | std r11,_CTR(r1) | |
1847 | std r12,_XER(r1) | |
1848 | SAVE_GPR(0,r1) | |
1849 | SAVE_GPR(2,r1) | |
1850 | ld r10,EX_R3(r3) | |
1851 | std r10,GPR3(r1) | |
1852 | SAVE_GPR(4,r1) | |
1853 | SAVE_4GPRS(5,r1) | |
1854 | ld r9,EX_R9(r3) | |
1855 | ld r10,EX_R10(r3) | |
1856 | SAVE_2GPRS(9,r1) | |
1857 | ld r9,EX_R11(r3) | |
1858 | ld r10,EX_R12(r3) | |
1859 | ld r11,EX_R13(r3) | |
1860 | std r9,GPR11(r1) | |
1861 | std r10,GPR12(r1) | |
1862 | std r11,GPR13(r1) | |
1863 | BEGIN_FTR_SECTION | |
1864 | ld r10,EX_CFAR(r3) | |
1865 | std r10,ORIG_GPR3(r1) | |
1866 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
1867 | SAVE_8GPRS(14,r1) | |
1868 | SAVE_10GPRS(22,r1) | |
1869 | lhz r12,PACA_TRAP_SAVE(r13) | |
1870 | std r12,_TRAP(r1) | |
1871 | addi r11,r1,INT_FRAME_SIZE | |
1872 | std r11,0(r1) | |
1873 | li r12,0 | |
1874 | std r12,0(r11) | |
1875 | ld r2,PACATOC(r13) | |
1876 | ld r11,exception_marker@toc(r2) | |
1877 | std r12,RESULT(r1) | |
1878 | std r11,STACK_FRAME_OVERHEAD-16(r1) | |
1879 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
1880 | bl kernel_bad_stack | |
1881 | b 1b | |
15770a13 | 1882 | _ASM_NOKPROBE_SYMBOL(bad_stack); |
0f0c6ca1 | 1883 | |
a9af97aa NP |
1884 | /* |
1885 | * When doorbell is triggered from system reset wakeup, the message is | |
1886 | * not cleared, so it would fire again when EE is enabled. | |
1887 | * | |
1888 | * When coming from local_irq_enable, there may be the same problem if | |
1889 | * we were hard disabled. | |
1890 | * | |
1891 | * Execute msgclr to clear pending exceptions before handling it. | |
1892 | */ | |
1893 | h_doorbell_common_msgclr: | |
1894 | LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) | |
1895 | PPC_MSGCLR(3) | |
1896 | b h_doorbell_common | |
1897 | ||
1898 | doorbell_super_common_msgclr: | |
1899 | LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) | |
1900 | PPC_MSGCLRP(3) | |
1901 | b doorbell_super_common | |
1902 | ||
0f0c6ca1 NP |
1903 | /* |
1904 | * Called from arch_local_irq_enable when an interrupt needs | |
1905 | * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate | |
1906 | * which kind of interrupt. MSR:EE is already off. We generate a | |
1907 | * stackframe like if a real interrupt had happened. | |
1908 | * | |
1909 | * Note: While MSR:EE is off, we need to make sure that _MSR | |
1910 | * in the generated frame has EE set to 1 or the exception | |
1911 | * handler will not properly re-enable them. | |
b48bbb82 NP |
1912 | * |
1913 | * Note that we don't specify LR as the NIP (return address) for | |
1914 | * the interrupt because that would unbalance the return branch | |
1915 | * predictor. | |
0f0c6ca1 NP |
1916 | */ |
1917 | _GLOBAL(__replay_interrupt) | |
1918 | /* We are going to jump to the exception common code which | |
1919 | * will retrieve various register values from the PACA which | |
1920 | * we don't give a damn about, so we don't bother storing them. | |
1921 | */ | |
1922 | mfmsr r12 | |
3e23a12b | 1923 | LOAD_REG_ADDR(r11, replay_interrupt_return) |
0f0c6ca1 NP |
1924 | mfcr r9 |
1925 | ori r12,r12,MSR_EE | |
1926 | cmpwi r3,0x900 | |
1927 | beq decrementer_common | |
1928 | cmpwi r3,0x500 | |
e6c1203d NP |
1929 | BEGIN_FTR_SECTION |
1930 | beq h_virt_irq_common | |
1931 | FTR_SECTION_ELSE | |
0f0c6ca1 | 1932 | beq hardware_interrupt_common |
e6c1203d | 1933 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_300) |
f442d004 MS |
1934 | cmpwi r3,0xf00 |
1935 | beq performance_monitor_common | |
0f0c6ca1 | 1936 | BEGIN_FTR_SECTION |
d6f73fc6 | 1937 | cmpwi r3,0xa00 |
a9af97aa | 1938 | beq h_doorbell_common_msgclr |
0f0c6ca1 NP |
1939 | cmpwi r3,0xe60 |
1940 | beq hmi_exception_common | |
1941 | FTR_SECTION_ELSE | |
1942 | cmpwi r3,0xa00 | |
a9af97aa | 1943 | beq doorbell_super_common_msgclr |
0f0c6ca1 | 1944 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
3e23a12b | 1945 | replay_interrupt_return: |
0f0c6ca1 | 1946 | blr |
b48bbb82 | 1947 | |
15770a13 | 1948 | _ASM_NOKPROBE_SYMBOL(__replay_interrupt) |