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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
0ebc4cda BH |
2 | /* |
3 | * This file contains the 64-bit "server" PowerPC variant | |
4 | * of the low level exception handling including exception | |
5 | * vectors, exception return, part of the slb and stab | |
6 | * handling and other fixed offset specific things. | |
7 | * | |
8 | * This file is meant to be #included from head_64.S due to | |
25985edc | 9 | * position dependent assembly. |
0ebc4cda BH |
10 | * |
11 | * Most of this originates from head_64.S and thus has the same | |
12 | * copyright history. | |
13 | * | |
14 | */ | |
15 | ||
7230c564 | 16 | #include <asm/hw_irq.h> |
8aa34ab8 | 17 | #include <asm/exception-64s.h> |
46f52210 | 18 | #include <asm/ptrace.h> |
7cba160a | 19 | #include <asm/cpuidle.h> |
da2bc464 | 20 | #include <asm/head-64.h> |
2c86cd18 | 21 | #include <asm/feature-fixups.h> |
8aa34ab8 | 22 | |
0ebc4cda | 23 | /* |
57f26649 NP |
24 | * There are a few constraints to be concerned with. |
25 | * - Real mode exceptions code/data must be located at their physical location. | |
26 | * - Virtual mode exceptions must be mapped at their 0xc000... location. | |
27 | * - Fixed location code must not call directly beyond the __end_interrupts | |
28 | * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence | |
29 | * must be used. | |
30 | * - LOAD_HANDLER targets must be within first 64K of physical 0 / | |
31 | * virtual 0xc00... | |
32 | * - Conditional branch targets must be within +/-32K of caller. | |
33 | * | |
34 | * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and | |
35 | * therefore don't have to run in physically located code or rfid to | |
36 | * virtual mode kernel code. However on relocatable kernels they do have | |
37 | * to branch to KERNELBASE offset because the rest of the kernel (outside | |
38 | * the exception vectors) may be located elsewhere. | |
39 | * | |
40 | * Virtual exceptions correspond with physical, except their entry points | |
41 | * are offset by 0xc000000000000000 and also tend to get an added 0x4000 | |
42 | * offset applied. Virtual exceptions are enabled with the Alternate | |
43 | * Interrupt Location (AIL) bit set in the LPCR. However this does not | |
44 | * guarantee they will be delivered virtually. Some conditions (see the ISA) | |
45 | * cause exceptions to be delivered in real mode. | |
46 | * | |
47 | * It's impossible to receive interrupts below 0x300 via AIL. | |
48 | * | |
49 | * KVM: None of the virtual exceptions are from the guest. Anything that | |
50 | * escalated to HV=1 from HV=0 is delivered via real mode handlers. | |
51 | * | |
52 | * | |
0ebc4cda BH |
53 | * We layout physical memory as follows: |
54 | * 0x0000 - 0x00ff : Secondary processor spin code | |
57f26649 NP |
55 | * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors |
56 | * 0x1900 - 0x3fff : Real mode trampolines | |
57 | * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors | |
58 | * 0x5900 - 0x6fff : Relon mode trampolines | |
0ebc4cda | 59 | * 0x7000 - 0x7fff : FWNMI data area |
57f26649 NP |
60 | * 0x8000 - .... : Common interrupt handlers, remaining early |
61 | * setup code, rest of kernel. | |
e0319829 NP |
62 | * |
63 | * We could reclaim 0x4000-0x42ff for real mode trampolines if the space | |
64 | * is necessary. Until then it's more consistent to explicitly put VIRT_NONE | |
65 | * vectors there. | |
57f26649 NP |
66 | */ |
67 | OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) | |
68 | OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000) | |
69 | OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900) | |
70 | OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) | |
71 | #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) | |
72 | /* | |
73 | * Data area reserved for FWNMI option. | |
74 | * This address (0x7000) is fixed by the RPA. | |
75 | * pseries and powernv need to keep the whole page from | |
76 | * 0x7000 to 0x8000 free for use by the firmware | |
0ebc4cda | 77 | */ |
57f26649 NP |
78 | ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) |
79 | OPEN_TEXT_SECTION(0x8000) | |
80 | #else | |
81 | OPEN_TEXT_SECTION(0x7000) | |
82 | #endif | |
83 | ||
84 | USE_FIXED_SECTION(real_vectors) | |
85 | ||
0ebc4cda BH |
86 | /* |
87 | * This is the start of the interrupt handlers for pSeries | |
88 | * This code runs with relocation off. | |
89 | * Code from here to __end_interrupts gets copied down to real | |
90 | * address 0x100 when we are running a relocatable kernel. | |
91 | * Therefore any relative branches in this section must only | |
92 | * branch to labels in this section. | |
93 | */ | |
0ebc4cda BH |
94 | .globl __start_interrupts |
95 | __start_interrupts: | |
96 | ||
e0319829 | 97 | /* No virt vectors corresponding with 0x0..0x100 */ |
1a6822d1 | 98 | EXC_VIRT_NONE(0x4000, 0x100) |
e0319829 | 99 | |
fb479e44 | 100 | |
948cf67c | 101 | #ifdef CONFIG_PPC_P7_NAP |
fb479e44 NP |
102 | /* |
103 | * If running native on arch 2.06 or later, check if we are waking up | |
ba6d334a BH |
104 | * from nap/sleep/winkle, and branch to idle handler. This tests SRR1 |
105 | * bits 46:47. A non-0 value indicates that we are coming from a power | |
106 | * saving state. The idle wakeup handler initially runs in real mode, | |
107 | * but we branch to the 0xc000... address so we can turn on relocation | |
108 | * with mtmsr. | |
948cf67c | 109 | */ |
fb479e44 NP |
110 | #define IDLETEST(n) \ |
111 | BEGIN_FTR_SECTION ; \ | |
112 | mfspr r10,SPRN_SRR1 ; \ | |
113 | rlwinm. r10,r10,47-31,30,31 ; \ | |
114 | beq- 1f ; \ | |
115 | cmpwi cr3,r10,2 ; \ | |
b51351e2 | 116 | BRANCH_TO_C000(r10, system_reset_idle_common) ; \ |
fb479e44 | 117 | 1: \ |
6de6638b | 118 | KVMTEST_PR(n) ; \ |
fb479e44 NP |
119 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
120 | #else | |
121 | #define IDLETEST NOTEST | |
122 | #endif | |
371fefd6 | 123 | |
1a6822d1 | 124 | EXC_REAL_BEGIN(system_reset, 0x100, 0x100) |
fb479e44 | 125 | SET_SCRATCH0(r13) |
c4f3b52c NP |
126 | /* |
127 | * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is | |
128 | * being used, so a nested NMI exception would corrupt it. | |
129 | */ | |
94f3cc8e ME |
130 | EXCEPTION_PROLOG_NORI(PACA_EXNMI, system_reset_common, EXC_STD, |
131 | IDLETEST, 0x100) | |
fb479e44 | 132 | |
1a6822d1 NP |
133 | EXC_REAL_END(system_reset, 0x100, 0x100) |
134 | EXC_VIRT_NONE(0x4100, 0x100) | |
6de6638b | 135 | TRAMP_KVM(PACA_EXNMI, 0x100) |
fb479e44 NP |
136 | |
137 | #ifdef CONFIG_PPC_P7_NAP | |
138 | EXC_COMMON_BEGIN(system_reset_idle_common) | |
9d292501 | 139 | mfspr r12,SPRN_SRR1 |
bf0153c1 | 140 | b pnv_powersave_wakeup |
371fefd6 PM |
141 | #endif |
142 | ||
15b4dd79 NP |
143 | /* |
144 | * Set IRQS_ALL_DISABLED unconditionally so arch_irqs_disabled does | |
145 | * the right thing. We do not want to reconcile because that goes | |
146 | * through irq tracing which we don't want in NMI. | |
147 | * | |
148 | * Save PACAIRQHAPPENED because some code will do a hard disable | |
149 | * (e.g., xmon). So we want to restore this back to where it was | |
150 | * when we return. DAR is unused in the stack, so save it there. | |
151 | */ | |
152 | #define ADD_RECONCILE_NMI \ | |
153 | li r10,IRQS_ALL_DISABLED; \ | |
154 | stb r10,PACAIRQSOFTMASK(r13); \ | |
155 | lbz r10,PACAIRQHAPPENED(r13); \ | |
156 | std r10,_DAR(r1) | |
157 | ||
a3d96f70 | 158 | EXC_COMMON_BEGIN(system_reset_common) |
c4f3b52c NP |
159 | /* |
160 | * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able | |
161 | * to recover, but nested NMI will notice in_nmi and not recover | |
162 | * because of the use of the NMI stack. in_nmi reentrancy is tested in | |
163 | * system_reset_exception. | |
164 | */ | |
165 | lhz r10,PACA_IN_NMI(r13) | |
166 | addi r10,r10,1 | |
167 | sth r10,PACA_IN_NMI(r13) | |
168 | li r10,MSR_RI | |
169 | mtmsrd r10,1 | |
aca79d2b | 170 | |
b1ee8a3d NP |
171 | mr r10,r1 |
172 | ld r1,PACA_NMI_EMERG_SP(r13) | |
173 | subi r1,r1,INT_FRAME_SIZE | |
174 | EXCEPTION_COMMON_NORET_STACK(PACA_EXNMI, 0x100, | |
175 | system_reset, system_reset_exception, | |
15b4dd79 NP |
176 | ADD_NVGPRS;ADD_RECONCILE_NMI) |
177 | ||
178 | /* This (and MCE) can be simplified with mtmsrd L=1 */ | |
179 | /* Clear MSR_RI before setting SRR0 and SRR1. */ | |
180 | li r0,MSR_RI | |
181 | mfmsr r9 | |
182 | andc r9,r9,r0 | |
183 | mtmsrd r9,1 | |
c4f3b52c NP |
184 | |
185 | /* | |
15b4dd79 | 186 | * MSR_RI is clear, now we can decrement paca->in_nmi. |
c4f3b52c NP |
187 | */ |
188 | lhz r10,PACA_IN_NMI(r13) | |
189 | subi r10,r10,1 | |
190 | sth r10,PACA_IN_NMI(r13) | |
191 | ||
15b4dd79 NP |
192 | /* |
193 | * Restore soft mask settings. | |
194 | */ | |
195 | ld r10,_DAR(r1) | |
196 | stb r10,PACAIRQHAPPENED(r13) | |
197 | ld r10,SOFTE(r1) | |
198 | stb r10,PACAIRQSOFTMASK(r13) | |
199 | ||
200 | /* | |
201 | * Keep below code in synch with MACHINE_CHECK_HANDLER_WINDUP. | |
202 | * Should share common bits... | |
203 | */ | |
204 | ||
205 | /* Move original SRR0 and SRR1 into the respective regs */ | |
206 | ld r9,_MSR(r1) | |
207 | mtspr SPRN_SRR1,r9 | |
208 | ld r3,_NIP(r1) | |
209 | mtspr SPRN_SRR0,r3 | |
210 | ld r9,_CTR(r1) | |
211 | mtctr r9 | |
212 | ld r9,_XER(r1) | |
213 | mtxer r9 | |
214 | ld r9,_LINK(r1) | |
215 | mtlr r9 | |
216 | REST_GPR(0, r1) | |
217 | REST_8GPRS(2, r1) | |
218 | REST_GPR(10, r1) | |
219 | ld r11,_CCR(r1) | |
220 | mtcr r11 | |
221 | REST_GPR(11, r1) | |
222 | REST_2GPRS(12, r1) | |
223 | /* restore original r1. */ | |
224 | ld r1,GPR1(r1) | |
225 | RFI_TO_USER_OR_KERNEL | |
582baf44 NP |
226 | |
227 | #ifdef CONFIG_PPC_PSERIES | |
228 | /* | |
229 | * Vectors for the FWNMI option. Share common code. | |
230 | */ | |
231 | TRAMP_REAL_BEGIN(system_reset_fwnmi) | |
232 | SET_SCRATCH0(r13) /* save r13 */ | |
c4f3b52c | 233 | /* See comment at system_reset exception */ |
94f3cc8e ME |
234 | EXCEPTION_PROLOG_NORI(PACA_EXNMI, system_reset_common, EXC_STD, |
235 | NOTEST, 0x100) | |
582baf44 NP |
236 | #endif /* CONFIG_PPC_PSERIES */ |
237 | ||
0ebc4cda | 238 | |
1a6822d1 | 239 | EXC_REAL_BEGIN(machine_check, 0x200, 0x100) |
b01c8b54 PM |
240 | /* This is moved out of line as it can be patched by FW, but |
241 | * some code path might still want to branch into the original | |
242 | * vector | |
243 | */ | |
1707dd16 PM |
244 | SET_SCRATCH0(r13) /* save r13 */ |
245 | EXCEPTION_PROLOG_0(PACA_EXMC) | |
1e9b4507 | 246 | BEGIN_FTR_SECTION |
db7d31ac | 247 | b machine_check_common_early |
1e9b4507 | 248 | FTR_SECTION_ELSE |
1707dd16 | 249 | b machine_check_pSeries_0 |
1e9b4507 | 250 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
1a6822d1 NP |
251 | EXC_REAL_END(machine_check, 0x200, 0x100) |
252 | EXC_VIRT_NONE(0x4200, 0x100) | |
db7d31ac | 253 | TRAMP_REAL_BEGIN(machine_check_common_early) |
afcf0095 NP |
254 | EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200) |
255 | /* | |
256 | * Register contents: | |
257 | * R13 = PACA | |
258 | * R9 = CR | |
259 | * Original R9 to R13 is saved on PACA_EXMC | |
260 | * | |
261 | * Switch to mc_emergency stack and handle re-entrancy (we limit | |
262 | * the nested MCE upto level 4 to avoid stack overflow). | |
263 | * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 | |
264 | * | |
265 | * We use paca->in_mce to check whether this is the first entry or | |
266 | * nested machine check. We increment paca->in_mce to track nested | |
267 | * machine checks. | |
268 | * | |
269 | * If this is the first entry then set stack pointer to | |
270 | * paca->mc_emergency_sp, otherwise r1 is already pointing to | |
271 | * stack frame on mc_emergency stack. | |
272 | * | |
273 | * NOTE: We are here with MSR_ME=0 (off), which means we risk a | |
274 | * checkstop if we get another machine check exception before we do | |
275 | * rfid with MSR_ME=1. | |
1945bc45 NP |
276 | * |
277 | * This interrupt can wake directly from idle. If that is the case, | |
278 | * the machine check is handled then the idle wakeup code is called | |
2bf1071a | 279 | * to restore state. |
afcf0095 NP |
280 | */ |
281 | mr r11,r1 /* Save r1 */ | |
282 | lhz r10,PACA_IN_MCE(r13) | |
283 | cmpwi r10,0 /* Are we in nested machine check */ | |
284 | bne 0f /* Yes, we are. */ | |
285 | /* First machine check entry */ | |
286 | ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ | |
287 | 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
288 | addi r10,r10,1 /* increment paca->in_mce */ | |
289 | sth r10,PACA_IN_MCE(r13) | |
290 | /* Limit nested MCE to level 4 to avoid stack overflow */ | |
ba41e1e1 | 291 | cmpwi r10,MAX_MCE_DEPTH |
afcf0095 NP |
292 | bgt 2f /* Check if we hit limit of 4 */ |
293 | std r11,GPR1(r1) /* Save r1 on the stack. */ | |
294 | std r11,0(r1) /* make stack chain pointer */ | |
295 | mfspr r11,SPRN_SRR0 /* Save SRR0 */ | |
296 | std r11,_NIP(r1) | |
297 | mfspr r11,SPRN_SRR1 /* Save SRR1 */ | |
298 | std r11,_MSR(r1) | |
299 | mfspr r11,SPRN_DAR /* Save DAR */ | |
300 | std r11,_DAR(r1) | |
301 | mfspr r11,SPRN_DSISR /* Save DSISR */ | |
302 | std r11,_DSISR(r1) | |
303 | std r9,_CCR(r1) /* Save CR in stackframe */ | |
304 | /* Save r9 through r13 from EXMC save area to stack frame. */ | |
305 | EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) | |
306 | mfmsr r11 /* get MSR value */ | |
db7d31ac | 307 | BEGIN_FTR_SECTION |
afcf0095 | 308 | ori r11,r11,MSR_ME /* turn on ME bit */ |
db7d31ac | 309 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) |
afcf0095 NP |
310 | ori r11,r11,MSR_RI /* turn on RI bit */ |
311 | LOAD_HANDLER(r12, machine_check_handle_early) | |
312 | 1: mtspr SPRN_SRR0,r12 | |
313 | mtspr SPRN_SRR1,r11 | |
222f20f1 | 314 | RFI_TO_KERNEL |
afcf0095 NP |
315 | b . /* prevent speculative execution */ |
316 | 2: | |
317 | /* Stack overflow. Stay on emergency stack and panic. | |
318 | * Keep the ME bit off while panic-ing, so that if we hit | |
319 | * another machine check we checkstop. | |
320 | */ | |
321 | addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ | |
322 | ld r11,PACAKMSR(r13) | |
323 | LOAD_HANDLER(r12, unrecover_mce) | |
324 | li r10,MSR_ME | |
325 | andc r11,r11,r10 /* Turn off MSR_ME */ | |
326 | b 1b | |
327 | b . /* prevent speculative execution */ | |
afcf0095 NP |
328 | |
329 | TRAMP_REAL_BEGIN(machine_check_pSeries) | |
330 | .globl machine_check_fwnmi | |
331 | machine_check_fwnmi: | |
332 | SET_SCRATCH0(r13) /* save r13 */ | |
333 | EXCEPTION_PROLOG_0(PACA_EXMC) | |
a43c1590 | 334 | BEGIN_FTR_SECTION |
db7d31ac | 335 | b machine_check_common_early |
a43c1590 | 336 | END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE) |
afcf0095 NP |
337 | machine_check_pSeries_0: |
338 | EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200) | |
339 | /* | |
83a980f7 NP |
340 | * MSR_RI is not enabled, because PACA_EXMC is being used, so a |
341 | * nested machine check corrupts it. machine_check_common enables | |
342 | * MSR_RI. | |
afcf0095 | 343 | */ |
94f3cc8e | 344 | EXCEPTION_PROLOG_2_NORI(machine_check_common, EXC_STD) |
afcf0095 NP |
345 | |
346 | TRAMP_KVM_SKIP(PACA_EXMC, 0x200) | |
347 | ||
348 | EXC_COMMON_BEGIN(machine_check_common) | |
349 | /* | |
350 | * Machine check is different because we use a different | |
351 | * save area: PACA_EXMC instead of PACA_EXGEN. | |
352 | */ | |
353 | mfspr r10,SPRN_DAR | |
354 | std r10,PACA_EXMC+EX_DAR(r13) | |
355 | mfspr r10,SPRN_DSISR | |
356 | stw r10,PACA_EXMC+EX_DSISR(r13) | |
357 | EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) | |
358 | FINISH_NAP | |
359 | RECONCILE_IRQ_STATE(r10, r11) | |
360 | ld r3,PACA_EXMC+EX_DAR(r13) | |
361 | lwz r4,PACA_EXMC+EX_DSISR(r13) | |
362 | /* Enable MSR_RI when finished with PACA_EXMC */ | |
363 | li r10,MSR_RI | |
364 | mtmsrd r10,1 | |
365 | std r3,_DAR(r1) | |
366 | std r4,_DSISR(r1) | |
367 | bl save_nvgprs | |
368 | addi r3,r1,STACK_FRAME_OVERHEAD | |
369 | bl machine_check_exception | |
370 | b ret_from_except | |
371 | ||
372 | #define MACHINE_CHECK_HANDLER_WINDUP \ | |
373 | /* Clear MSR_RI before setting SRR0 and SRR1. */\ | |
374 | li r0,MSR_RI; \ | |
375 | mfmsr r9; /* get MSR value */ \ | |
376 | andc r9,r9,r0; \ | |
377 | mtmsrd r9,1; /* Clear MSR_RI */ \ | |
378 | /* Move original SRR0 and SRR1 into the respective regs */ \ | |
379 | ld r9,_MSR(r1); \ | |
380 | mtspr SPRN_SRR1,r9; \ | |
381 | ld r3,_NIP(r1); \ | |
382 | mtspr SPRN_SRR0,r3; \ | |
383 | ld r9,_CTR(r1); \ | |
384 | mtctr r9; \ | |
385 | ld r9,_XER(r1); \ | |
386 | mtxer r9; \ | |
387 | ld r9,_LINK(r1); \ | |
388 | mtlr r9; \ | |
389 | REST_GPR(0, r1); \ | |
390 | REST_8GPRS(2, r1); \ | |
391 | REST_GPR(10, r1); \ | |
392 | ld r11,_CCR(r1); \ | |
393 | mtcr r11; \ | |
394 | /* Decrement paca->in_mce. */ \ | |
395 | lhz r12,PACA_IN_MCE(r13); \ | |
396 | subi r12,r12,1; \ | |
397 | sth r12,PACA_IN_MCE(r13); \ | |
398 | REST_GPR(11, r1); \ | |
399 | REST_2GPRS(12, r1); \ | |
400 | /* restore original r1. */ \ | |
401 | ld r1,GPR1(r1) | |
402 | ||
1945bc45 NP |
403 | #ifdef CONFIG_PPC_P7_NAP |
404 | /* | |
405 | * This is an idle wakeup. Low level machine check has already been | |
406 | * done. Queue the event then call the idle code to do the wake up. | |
407 | */ | |
408 | EXC_COMMON_BEGIN(machine_check_idle_common) | |
409 | bl machine_check_queue_event | |
410 | ||
411 | /* | |
412 | * We have not used any non-volatile GPRs here, and as a rule | |
413 | * most exception code including machine check does not. | |
414 | * Therefore PACA_NAPSTATELOST does not need to be set. Idle | |
415 | * wakeup will restore volatile registers. | |
416 | * | |
417 | * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce. | |
418 | * | |
419 | * Then decrement MCE nesting after finishing with the stack. | |
420 | */ | |
421 | ld r3,_MSR(r1) | |
422 | ||
423 | lhz r11,PACA_IN_MCE(r13) | |
424 | subi r11,r11,1 | |
425 | sth r11,PACA_IN_MCE(r13) | |
426 | ||
427 | /* Turn off the RI bit because SRR1 is used by idle wakeup code. */ | |
428 | /* Recoverability could be improved by reducing the use of SRR1. */ | |
429 | li r11,0 | |
430 | mtmsrd r11,1 | |
431 | ||
432 | b pnv_powersave_wakeup_mce | |
433 | #endif | |
afcf0095 NP |
434 | /* |
435 | * Handle machine check early in real mode. We come here with | |
436 | * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. | |
437 | */ | |
438 | EXC_COMMON_BEGIN(machine_check_handle_early) | |
439 | std r0,GPR0(r1) /* Save r0 */ | |
440 | EXCEPTION_PROLOG_COMMON_3(0x200) | |
441 | bl save_nvgprs | |
442 | addi r3,r1,STACK_FRAME_OVERHEAD | |
443 | bl machine_check_early | |
444 | std r3,RESULT(r1) /* Save result */ | |
445 | ld r12,_MSR(r1) | |
db7d31ac MS |
446 | BEGIN_FTR_SECTION |
447 | b 4f | |
448 | END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE) | |
1945bc45 | 449 | |
afcf0095 NP |
450 | #ifdef CONFIG_PPC_P7_NAP |
451 | /* | |
452 | * Check if thread was in power saving mode. We come here when any | |
453 | * of the following is true: | |
454 | * a. thread wasn't in power saving mode | |
455 | * b. thread was in power saving mode with no state loss, | |
456 | * supervisor state loss or hypervisor state loss. | |
457 | * | |
458 | * Go back to nap/sleep/winkle mode again if (b) is true. | |
459 | */ | |
1945bc45 NP |
460 | BEGIN_FTR_SECTION |
461 | rlwinm. r11,r12,47-31,30,31 | |
6102c005 | 462 | bne machine_check_idle_common |
1945bc45 | 463 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
afcf0095 | 464 | #endif |
1945bc45 | 465 | |
afcf0095 NP |
466 | /* |
467 | * Check if we are coming from hypervisor userspace. If yes then we | |
468 | * continue in host kernel in V mode to deliver the MC event. | |
469 | */ | |
470 | rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ | |
471 | beq 5f | |
db7d31ac | 472 | 4: andi. r11,r12,MSR_PR /* See if coming from user. */ |
afcf0095 NP |
473 | bne 9f /* continue in V mode if we are. */ |
474 | ||
475 | 5: | |
476 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER | |
db7d31ac | 477 | BEGIN_FTR_SECTION |
afcf0095 NP |
478 | /* |
479 | * We are coming from kernel context. Check if we are coming from | |
480 | * guest. if yes, then we can continue. We will fall through | |
481 | * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. | |
482 | */ | |
483 | lbz r11,HSTATE_IN_GUEST(r13) | |
484 | cmpwi r11,0 /* Check if coming from guest */ | |
485 | bne 9f /* continue if we are. */ | |
db7d31ac | 486 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) |
afcf0095 NP |
487 | #endif |
488 | /* | |
489 | * At this point we are not sure about what context we come from. | |
490 | * Queue up the MCE event and return from the interrupt. | |
491 | * But before that, check if this is an un-recoverable exception. | |
492 | * If yes, then stay on emergency stack and panic. | |
493 | */ | |
494 | andi. r11,r12,MSR_RI | |
495 | bne 2f | |
496 | 1: mfspr r11,SPRN_SRR0 | |
497 | LOAD_HANDLER(r10,unrecover_mce) | |
498 | mtspr SPRN_SRR0,r10 | |
499 | ld r10,PACAKMSR(r13) | |
500 | /* | |
501 | * We are going down. But there are chances that we might get hit by | |
502 | * another MCE during panic path and we may run into unstable state | |
503 | * with no way out. Hence, turn ME bit off while going down, so that | |
504 | * when another MCE is hit during panic path, system will checkstop | |
505 | * and hypervisor will get restarted cleanly by SP. | |
506 | */ | |
507 | li r3,MSR_ME | |
508 | andc r10,r10,r3 /* Turn off MSR_ME */ | |
509 | mtspr SPRN_SRR1,r10 | |
222f20f1 | 510 | RFI_TO_KERNEL |
afcf0095 NP |
511 | b . |
512 | 2: | |
513 | /* | |
514 | * Check if we have successfully handled/recovered from error, if not | |
515 | * then stay on emergency stack and panic. | |
516 | */ | |
517 | ld r3,RESULT(r1) /* Load result */ | |
518 | cmpdi r3,0 /* see if we handled MCE successfully */ | |
519 | ||
520 | beq 1b /* if !handled then panic */ | |
db7d31ac | 521 | BEGIN_FTR_SECTION |
afcf0095 NP |
522 | /* |
523 | * Return from MC interrupt. | |
524 | * Queue up the MCE event so that we can log it later, while | |
525 | * returning from kernel or opal call. | |
526 | */ | |
527 | bl machine_check_queue_event | |
528 | MACHINE_CHECK_HANDLER_WINDUP | |
222f20f1 | 529 | RFI_TO_USER_OR_KERNEL |
db7d31ac MS |
530 | FTR_SECTION_ELSE |
531 | /* | |
532 | * pSeries: Return from MC interrupt. Before that stay on emergency | |
533 | * stack and call machine_check_exception to log the MCE event. | |
534 | */ | |
535 | LOAD_HANDLER(r10,mce_return) | |
536 | mtspr SPRN_SRR0,r10 | |
537 | ld r10,PACAKMSR(r13) | |
538 | mtspr SPRN_SRR1,r10 | |
539 | RFI_TO_KERNEL | |
540 | b . | |
541 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) | |
afcf0095 NP |
542 | 9: |
543 | /* Deliver the machine check to host kernel in V mode. */ | |
544 | MACHINE_CHECK_HANDLER_WINDUP | |
db7d31ac MS |
545 | SET_SCRATCH0(r13) /* save r13 */ |
546 | EXCEPTION_PROLOG_0(PACA_EXMC) | |
547 | b machine_check_pSeries_0 | |
afcf0095 NP |
548 | |
549 | EXC_COMMON_BEGIN(unrecover_mce) | |
550 | /* Invoke machine_check_exception to print MCE event and panic. */ | |
551 | addi r3,r1,STACK_FRAME_OVERHEAD | |
552 | bl machine_check_exception | |
553 | /* | |
554 | * We will not reach here. Even if we did, there is no way out. Call | |
555 | * unrecoverable_exception and die. | |
556 | */ | |
557 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
558 | bl unrecoverable_exception | |
559 | b 1b | |
560 | ||
a43c1590 MS |
561 | EXC_COMMON_BEGIN(mce_return) |
562 | /* Invoke machine_check_exception to print MCE event and return. */ | |
563 | addi r3,r1,STACK_FRAME_OVERHEAD | |
564 | bl machine_check_exception | |
db7d31ac | 565 | MACHINE_CHECK_HANDLER_WINDUP |
a43c1590 MS |
566 | RFI_TO_KERNEL |
567 | b . | |
0ebc4cda | 568 | |
1a6822d1 NP |
569 | EXC_REAL(data_access, 0x300, 0x80) |
570 | EXC_VIRT(data_access, 0x4300, 0x80, 0x300) | |
80795e6c NP |
571 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x300) |
572 | ||
573 | EXC_COMMON_BEGIN(data_access_common) | |
574 | /* | |
575 | * Here r13 points to the paca, r9 contains the saved CR, | |
576 | * SRR0 and SRR1 are saved in r11 and r12, | |
577 | * r9 - r13 are saved in paca->exgen. | |
578 | */ | |
579 | mfspr r10,SPRN_DAR | |
580 | std r10,PACA_EXGEN+EX_DAR(r13) | |
581 | mfspr r10,SPRN_DSISR | |
582 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
583 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) | |
584 | RECONCILE_IRQ_STATE(r10, r11) | |
585 | ld r12,_MSR(r1) | |
586 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
587 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
588 | li r5,0x300 | |
589 | std r3,_DAR(r1) | |
590 | std r4,_DSISR(r1) | |
591 | BEGIN_MMU_FTR_SECTION | |
592 | b do_hash_page /* Try to handle as hpte fault */ | |
593 | MMU_FTR_SECTION_ELSE | |
594 | b handle_page_fault | |
595 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
596 | ||
0ebc4cda | 597 | |
1a6822d1 | 598 | EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80) |
54be0b9c ME |
599 | SET_SCRATCH0(r13) |
600 | EXCEPTION_PROLOG_0(PACA_EXSLB) | |
601 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380) | |
602 | mr r12,r3 /* save r3 */ | |
603 | mfspr r3,SPRN_DAR | |
604 | mfspr r11,SPRN_SRR1 | |
605 | crset 4*cr6+eq | |
606 | BRANCH_TO_COMMON(r10, slb_miss_common) | |
1a6822d1 | 607 | EXC_REAL_END(data_access_slb, 0x380, 0x80) |
0ebc4cda | 608 | |
1a6822d1 | 609 | EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80) |
54be0b9c ME |
610 | SET_SCRATCH0(r13) |
611 | EXCEPTION_PROLOG_0(PACA_EXSLB) | |
612 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380) | |
613 | mr r12,r3 /* save r3 */ | |
614 | mfspr r3,SPRN_DAR | |
615 | mfspr r11,SPRN_SRR1 | |
616 | crset 4*cr6+eq | |
617 | BRANCH_TO_COMMON(r10, slb_miss_common) | |
1a6822d1 | 618 | EXC_VIRT_END(data_access_slb, 0x4380, 0x80) |
2b9af6e4 NP |
619 | TRAMP_KVM_SKIP(PACA_EXSLB, 0x380) |
620 | ||
621 | ||
1a6822d1 NP |
622 | EXC_REAL(instruction_access, 0x400, 0x80) |
623 | EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400) | |
27ce77df NP |
624 | TRAMP_KVM(PACA_EXGEN, 0x400) |
625 | ||
626 | EXC_COMMON_BEGIN(instruction_access_common) | |
627 | EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) | |
628 | RECONCILE_IRQ_STATE(r10, r11) | |
629 | ld r12,_MSR(r1) | |
630 | ld r3,_NIP(r1) | |
475b581f | 631 | andis. r4,r12,DSISR_SRR1_MATCH_64S@h |
27ce77df NP |
632 | li r5,0x400 |
633 | std r3,_DAR(r1) | |
634 | std r4,_DSISR(r1) | |
635 | BEGIN_MMU_FTR_SECTION | |
636 | b do_hash_page /* Try to handle as hpte fault */ | |
637 | MMU_FTR_SECTION_ELSE | |
638 | b handle_page_fault | |
639 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
640 | ||
0ebc4cda | 641 | |
1a6822d1 | 642 | EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80) |
54be0b9c ME |
643 | SET_SCRATCH0(r13) |
644 | EXCEPTION_PROLOG_0(PACA_EXSLB) | |
645 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480) | |
646 | mr r12,r3 /* save r3 */ | |
647 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
648 | mfspr r11,SPRN_SRR1 | |
649 | crclr 4*cr6+eq | |
650 | BRANCH_TO_COMMON(r10, slb_miss_common) | |
1a6822d1 | 651 | EXC_REAL_END(instruction_access_slb, 0x480, 0x80) |
0ebc4cda | 652 | |
1a6822d1 | 653 | EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80) |
54be0b9c ME |
654 | SET_SCRATCH0(r13) |
655 | EXCEPTION_PROLOG_0(PACA_EXSLB) | |
656 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480) | |
657 | mr r12,r3 /* save r3 */ | |
658 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
659 | mfspr r11,SPRN_SRR1 | |
660 | crclr 4*cr6+eq | |
661 | BRANCH_TO_COMMON(r10, slb_miss_common) | |
1a6822d1 | 662 | EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80) |
5e46e29e | 663 | TRAMP_KVM(PACA_EXSLB, 0x480) |
8d04631a | 664 | |
54be0b9c ME |
665 | |
666 | /* | |
667 | * This handler is used by the 0x380 and 0x480 SLB miss interrupts, as well as | |
668 | * the virtual mode 0x4380 and 0x4480 interrupts if AIL is enabled. | |
669 | */ | |
670 | EXC_COMMON_BEGIN(slb_miss_common) | |
671 | /* | |
672 | * r13 points to the PACA, r9 contains the saved CR, | |
673 | * r12 contains the saved r3, | |
674 | * r11 contain the saved SRR1, SRR0 is still ready for return | |
675 | * r3 has the faulting address | |
676 | * r9 - r13 are saved in paca->exslb. | |
677 | * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss | |
678 | * We assume we aren't going to take any exceptions during this | |
679 | * procedure. | |
680 | */ | |
681 | mflr r10 | |
682 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
683 | std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ | |
684 | ||
685 | andi. r9,r11,MSR_PR // Check for exception from userspace | |
686 | cmpdi cr4,r9,MSR_PR // And save the result in CR4 for later | |
687 | ||
688 | /* | |
689 | * Test MSR_RI before calling slb_allocate_realmode, because the | |
690 | * MSR in r11 gets clobbered. However we still want to allocate | |
691 | * SLB in case MSR_RI=0, to minimise the risk of getting stuck in | |
692 | * recursive SLB faults. So use cr5 for this, which is preserved. | |
693 | */ | |
694 | andi. r11,r11,MSR_RI /* check for unrecoverable exception */ | |
695 | cmpdi cr5,r11,MSR_RI | |
696 | ||
697 | crset 4*cr0+eq | |
698 | #ifdef CONFIG_PPC_BOOK3S_64 | |
699 | BEGIN_MMU_FTR_SECTION | |
700 | bl slb_allocate | |
701 | END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX) | |
702 | #endif | |
703 | ||
704 | ld r10,PACA_EXSLB+EX_LR(r13) | |
705 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
706 | mtlr r10 | |
707 | ||
708 | /* | |
709 | * Large address, check whether we have to allocate new contexts. | |
710 | */ | |
711 | beq- 8f | |
712 | ||
713 | bne- cr5,2f /* if unrecoverable exception, oops */ | |
714 | ||
715 | /* All done -- return from exception. */ | |
716 | ||
717 | bne cr4,1f /* returning to kernel */ | |
718 | ||
719 | mtcrf 0x80,r9 | |
720 | mtcrf 0x08,r9 /* MSR[PR] indication is in cr4 */ | |
721 | mtcrf 0x04,r9 /* MSR[RI] indication is in cr5 */ | |
722 | mtcrf 0x02,r9 /* I/D indication is in cr6 */ | |
723 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ | |
724 | ||
725 | RESTORE_CTR(r9, PACA_EXSLB) | |
726 | RESTORE_PPR_PACA(PACA_EXSLB, r9) | |
727 | mr r3,r12 | |
728 | ld r9,PACA_EXSLB+EX_R9(r13) | |
729 | ld r10,PACA_EXSLB+EX_R10(r13) | |
730 | ld r11,PACA_EXSLB+EX_R11(r13) | |
731 | ld r12,PACA_EXSLB+EX_R12(r13) | |
732 | ld r13,PACA_EXSLB+EX_R13(r13) | |
733 | RFI_TO_USER | |
734 | b . /* prevent speculative execution */ | |
735 | 1: | |
736 | mtcrf 0x80,r9 | |
737 | mtcrf 0x08,r9 /* MSR[PR] indication is in cr4 */ | |
738 | mtcrf 0x04,r9 /* MSR[RI] indication is in cr5 */ | |
739 | mtcrf 0x02,r9 /* I/D indication is in cr6 */ | |
740 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ | |
741 | ||
742 | RESTORE_CTR(r9, PACA_EXSLB) | |
743 | RESTORE_PPR_PACA(PACA_EXSLB, r9) | |
744 | mr r3,r12 | |
745 | ld r9,PACA_EXSLB+EX_R9(r13) | |
746 | ld r10,PACA_EXSLB+EX_R10(r13) | |
747 | ld r11,PACA_EXSLB+EX_R11(r13) | |
748 | ld r12,PACA_EXSLB+EX_R12(r13) | |
749 | ld r13,PACA_EXSLB+EX_R13(r13) | |
750 | RFI_TO_KERNEL | |
751 | b . /* prevent speculative execution */ | |
752 | ||
753 | ||
754 | 2: std r3,PACA_EXSLB+EX_DAR(r13) | |
755 | mr r3,r12 | |
756 | mfspr r11,SPRN_SRR0 | |
757 | mfspr r12,SPRN_SRR1 | |
758 | LOAD_HANDLER(r10,unrecov_slb) | |
759 | mtspr SPRN_SRR0,r10 | |
760 | ld r10,PACAKMSR(r13) | |
761 | mtspr SPRN_SRR1,r10 | |
762 | RFI_TO_KERNEL | |
763 | b . | |
764 | ||
765 | 8: std r3,PACA_EXSLB+EX_DAR(r13) | |
766 | mr r3,r12 | |
767 | mfspr r11,SPRN_SRR0 | |
768 | mfspr r12,SPRN_SRR1 | |
769 | LOAD_HANDLER(r10, large_addr_slb) | |
770 | mtspr SPRN_SRR0,r10 | |
771 | ld r10,PACAKMSR(r13) | |
772 | mtspr SPRN_SRR1,r10 | |
773 | RFI_TO_KERNEL | |
774 | b . | |
775 | ||
776 | EXC_COMMON_BEGIN(unrecov_slb) | |
777 | EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) | |
778 | RECONCILE_IRQ_STATE(r10, r11) | |
8d04631a | 779 | bl save_nvgprs |
54be0b9c ME |
780 | 1: addi r3,r1,STACK_FRAME_OVERHEAD |
781 | bl unrecoverable_exception | |
782 | b 1b | |
783 | ||
784 | EXC_COMMON_BEGIN(large_addr_slb) | |
785 | EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB) | |
8d04631a | 786 | RECONCILE_IRQ_STATE(r10, r11) |
54be0b9c ME |
787 | ld r3, PACA_EXSLB+EX_DAR(r13) |
788 | std r3, _DAR(r1) | |
789 | beq cr6, 2f | |
790 | li r10, 0x481 /* fix trap number for I-SLB miss */ | |
791 | std r10, _TRAP(r1) | |
792 | 2: bl save_nvgprs | |
793 | addi r3, r1, STACK_FRAME_OVERHEAD | |
794 | bl slb_miss_large_addr | |
8d04631a NP |
795 | b ret_from_except |
796 | ||
1a6822d1 | 797 | EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100) |
b3e6b5df | 798 | .globl hardware_interrupt_hv; |
b3e6b5df | 799 | hardware_interrupt_hv: |
a5d4f3ad | 800 | BEGIN_FTR_SECTION |
0b924de4 | 801 | MASKABLE_EXCEPTION_HV(0x500, hardware_interrupt_common, IRQS_DISABLED) |
de56a948 | 802 | FTR_SECTION_ELSE |
0b924de4 | 803 | MASKABLE_EXCEPTION(0x500, hardware_interrupt_common, IRQS_DISABLED) |
969391c5 | 804 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
1a6822d1 | 805 | EXC_REAL_END(hardware_interrupt, 0x500, 0x100) |
da2bc464 | 806 | |
1a6822d1 | 807 | EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100) |
c138e588 NP |
808 | .globl hardware_interrupt_relon_hv; |
809 | hardware_interrupt_relon_hv: | |
810 | BEGIN_FTR_SECTION | |
0b924de4 ME |
811 | MASKABLE_RELON_EXCEPTION_HV(0x500, hardware_interrupt_common, |
812 | IRQS_DISABLED) | |
c138e588 | 813 | FTR_SECTION_ELSE |
0a55c241 | 814 | __MASKABLE_RELON_EXCEPTION(0x500, hardware_interrupt_common, |
0b924de4 | 815 | EXC_STD, SOFTEN_TEST_PR, IRQS_DISABLED) |
c138e588 | 816 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
1a6822d1 | 817 | EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100) |
c138e588 | 818 | |
7ede5317 NP |
819 | TRAMP_KVM(PACA_EXGEN, 0x500) |
820 | TRAMP_KVM_HV(PACA_EXGEN, 0x500) | |
c138e588 NP |
821 | EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) |
822 | ||
823 | ||
1a6822d1 NP |
824 | EXC_REAL(alignment, 0x600, 0x100) |
825 | EXC_VIRT(alignment, 0x4600, 0x100, 0x600) | |
da2bc464 | 826 | TRAMP_KVM(PACA_EXGEN, 0x600) |
f9aa6714 NP |
827 | EXC_COMMON_BEGIN(alignment_common) |
828 | mfspr r10,SPRN_DAR | |
829 | std r10,PACA_EXGEN+EX_DAR(r13) | |
830 | mfspr r10,SPRN_DSISR | |
831 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
832 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) | |
833 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
834 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
835 | std r3,_DAR(r1) | |
836 | std r4,_DSISR(r1) | |
837 | bl save_nvgprs | |
838 | RECONCILE_IRQ_STATE(r10, r11) | |
839 | addi r3,r1,STACK_FRAME_OVERHEAD | |
840 | bl alignment_exception | |
841 | b ret_from_except | |
842 | ||
da2bc464 | 843 | |
1a6822d1 NP |
844 | EXC_REAL(program_check, 0x700, 0x100) |
845 | EXC_VIRT(program_check, 0x4700, 0x100, 0x700) | |
da2bc464 | 846 | TRAMP_KVM(PACA_EXGEN, 0x700) |
11e87346 | 847 | EXC_COMMON_BEGIN(program_check_common) |
265e60a1 CB |
848 | /* |
849 | * It's possible to receive a TM Bad Thing type program check with | |
850 | * userspace register values (in particular r1), but with SRR1 reporting | |
851 | * that we came from the kernel. Normally that would confuse the bad | |
852 | * stack logic, and we would report a bad kernel stack pointer. Instead | |
853 | * we switch to the emergency stack if we're taking a TM Bad Thing from | |
854 | * the kernel. | |
855 | */ | |
856 | li r10,MSR_PR /* Build a mask of MSR_PR .. */ | |
857 | oris r10,r10,0x200000@h /* .. and SRR1_PROGTM */ | |
858 | and r10,r10,r12 /* Mask SRR1 with that. */ | |
859 | srdi r10,r10,8 /* Shift it so we can compare */ | |
860 | cmpldi r10,(0x200000 >> 8) /* .. with an immediate. */ | |
861 | bne 1f /* If != go to normal path. */ | |
862 | ||
863 | /* SRR1 had PR=0 and SRR1_PROGTM=1, so use the emergency stack */ | |
864 | andi. r10,r12,MSR_PR; /* Set CR0 correctly for label */ | |
865 | /* 3 in EXCEPTION_PROLOG_COMMON */ | |
866 | mr r10,r1 /* Save r1 */ | |
867 | ld r1,PACAEMERGSP(r13) /* Use emergency stack */ | |
868 | subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
869 | b 3f /* Jump into the macro !! */ | |
870 | 1: EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) | |
11e87346 NP |
871 | bl save_nvgprs |
872 | RECONCILE_IRQ_STATE(r10, r11) | |
873 | addi r3,r1,STACK_FRAME_OVERHEAD | |
874 | bl program_check_exception | |
875 | b ret_from_except | |
876 | ||
b01c8b54 | 877 | |
1a6822d1 NP |
878 | EXC_REAL(fp_unavailable, 0x800, 0x100) |
879 | EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800) | |
da2bc464 | 880 | TRAMP_KVM(PACA_EXGEN, 0x800) |
c78d9b97 NP |
881 | EXC_COMMON_BEGIN(fp_unavailable_common) |
882 | EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) | |
883 | bne 1f /* if from user, just load it up */ | |
884 | bl save_nvgprs | |
885 | RECONCILE_IRQ_STATE(r10, r11) | |
886 | addi r3,r1,STACK_FRAME_OVERHEAD | |
887 | bl kernel_fp_unavailable_exception | |
888 | BUG_OPCODE | |
889 | 1: | |
890 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
891 | BEGIN_FTR_SECTION | |
892 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
893 | * transaction), go do TM stuff | |
894 | */ | |
895 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
896 | bne- 2f | |
897 | END_FTR_SECTION_IFSET(CPU_FTR_TM) | |
898 | #endif | |
899 | bl load_up_fpu | |
900 | b fast_exception_return | |
901 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
902 | 2: /* User process was in a transaction */ | |
903 | bl save_nvgprs | |
904 | RECONCILE_IRQ_STATE(r10, r11) | |
905 | addi r3,r1,STACK_FRAME_OVERHEAD | |
906 | bl fp_unavailable_tm | |
907 | b ret_from_except | |
908 | #endif | |
909 | ||
a5d4f3ad | 910 | |
a048a07d | 911 | EXC_REAL_OOL_MASKABLE(decrementer, 0x900, 0x80, IRQS_DISABLED) |
f14e953b | 912 | EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900, IRQS_DISABLED) |
39c0da57 NP |
913 | TRAMP_KVM(PACA_EXGEN, 0x900) |
914 | EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) | |
915 | ||
a485c709 | 916 | |
1a6822d1 NP |
917 | EXC_REAL_HV(hdecrementer, 0x980, 0x80) |
918 | EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980) | |
facc6d74 NP |
919 | TRAMP_KVM_HV(PACA_EXGEN, 0x980) |
920 | EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) | |
921 | ||
a5d4f3ad | 922 | |
f14e953b MS |
923 | EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100, IRQS_DISABLED) |
924 | EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00, IRQS_DISABLED) | |
da2bc464 | 925 | TRAMP_KVM(PACA_EXGEN, 0xa00) |
ca243163 NP |
926 | #ifdef CONFIG_PPC_DOORBELL |
927 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) | |
928 | #else | |
929 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) | |
930 | #endif | |
931 | ||
0ebc4cda | 932 | |
1a6822d1 NP |
933 | EXC_REAL(trap_0b, 0xb00, 0x100) |
934 | EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00) | |
da2bc464 | 935 | TRAMP_KVM(PACA_EXGEN, 0xb00) |
341215dc NP |
936 | EXC_COMMON(trap_0b_common, 0xb00, unknown_exception) |
937 | ||
acd7d8ce NP |
938 | /* |
939 | * system call / hypercall (0xc00, 0x4c00) | |
940 | * | |
941 | * The system call exception is invoked with "sc 0" and does not alter HV bit. | |
942 | * There is support for kernel code to invoke system calls but there are no | |
943 | * in-tree users. | |
944 | * | |
945 | * The hypercall is invoked with "sc 1" and sets HV=1. | |
946 | * | |
947 | * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to | |
948 | * 0x4c00 virtual mode. | |
949 | * | |
950 | * Call convention: | |
951 | * | |
952 | * syscall register convention is in Documentation/powerpc/syscall64-abi.txt | |
953 | * | |
954 | * For hypercalls, the register convention is as follows: | |
955 | * r0 volatile | |
956 | * r1-2 nonvolatile | |
957 | * r3 volatile parameter and return value for status | |
958 | * r4-r10 volatile input and output value | |
959 | * r11 volatile hypercall number and output value | |
76fc0cfc | 960 | * r12 volatile input and output value |
acd7d8ce NP |
961 | * r13-r31 nonvolatile |
962 | * LR nonvolatile | |
963 | * CTR volatile | |
964 | * XER volatile | |
965 | * CR0-1 CR5-7 volatile | |
966 | * CR2-4 nonvolatile | |
967 | * Other registers nonvolatile | |
968 | * | |
969 | * The intersection of volatile registers that don't contain possible | |
76fc0cfc NP |
970 | * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry |
971 | * without saving, though xer is not a good idea to use, as hardware may | |
972 | * interpret some bits so it may be costly to change them. | |
acd7d8ce | 973 | */ |
bc355125 | 974 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
acd7d8ce NP |
975 | /* |
976 | * There is a little bit of juggling to get syscall and hcall | |
76fc0cfc NP |
977 | * working well. Save r13 in ctr to avoid using SPRG scratch |
978 | * register. | |
acd7d8ce NP |
979 | * |
980 | * Userspace syscalls have already saved the PPR, hcalls must save | |
981 | * it before setting HMT_MEDIUM. | |
982 | */ | |
bc355125 | 983 | #define SYSCALL_KVMTEST \ |
76fc0cfc | 984 | mtctr r13; \ |
bc355125 | 985 | GET_PACA(r13); \ |
76fc0cfc | 986 | std r10,PACA_EXGEN+EX_R10(r13); \ |
a048a07d | 987 | INTERRUPT_TO_KERNEL; \ |
acd7d8ce | 988 | KVMTEST_PR(0xc00); /* uses r10, branch to do_kvm_0xc00_system_call */ \ |
bc355125 | 989 | HMT_MEDIUM; \ |
76fc0cfc | 990 | mfctr r9; |
bc355125 PM |
991 | |
992 | #else | |
993 | #define SYSCALL_KVMTEST \ | |
acd7d8ce NP |
994 | HMT_MEDIUM; \ |
995 | mr r9,r13; \ | |
a048a07d NP |
996 | GET_PACA(r13); \ |
997 | INTERRUPT_TO_KERNEL; | |
bc355125 PM |
998 | #endif |
999 | ||
fb479e44 NP |
1000 | #define LOAD_SYSCALL_HANDLER(reg) \ |
1001 | __LOAD_HANDLER(reg, system_call_common) | |
d807ad37 | 1002 | |
acd7d8ce NP |
1003 | /* |
1004 | * After SYSCALL_KVMTEST, we reach here with PACA in r13, r13 in r9, | |
1005 | * and HMT_MEDIUM. | |
1006 | */ | |
1007 | #define SYSCALL_REAL \ | |
1008 | mfspr r11,SPRN_SRR0 ; \ | |
d807ad37 NP |
1009 | mfspr r12,SPRN_SRR1 ; \ |
1010 | LOAD_SYSCALL_HANDLER(r10) ; \ | |
1011 | mtspr SPRN_SRR0,r10 ; \ | |
1012 | ld r10,PACAKMSR(r13) ; \ | |
1013 | mtspr SPRN_SRR1,r10 ; \ | |
222f20f1 | 1014 | RFI_TO_KERNEL ; \ |
d807ad37 NP |
1015 | b . ; /* prevent speculative execution */ |
1016 | ||
727f1361 | 1017 | #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH |
5c2511bf ME |
1018 | #define SYSCALL_FASTENDIAN_TEST \ |
1019 | BEGIN_FTR_SECTION \ | |
1020 | cmpdi r0,0x1ebe ; \ | |
1021 | beq- 1f ; \ | |
1022 | END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ | |
1023 | ||
acd7d8ce | 1024 | #define SYSCALL_FASTENDIAN \ |
d807ad37 NP |
1025 | /* Fast LE/BE switch system call */ \ |
1026 | 1: mfspr r12,SPRN_SRR1 ; \ | |
1027 | xori r12,r12,MSR_LE ; \ | |
1028 | mtspr SPRN_SRR1,r12 ; \ | |
acd7d8ce | 1029 | mr r13,r9 ; \ |
222f20f1 | 1030 | RFI_TO_USER ; /* return to userspace */ \ |
d807ad37 | 1031 | b . ; /* prevent speculative execution */ |
727f1361 ME |
1032 | #else |
1033 | #define SYSCALL_FASTENDIAN_TEST | |
1034 | #define SYSCALL_FASTENDIAN | |
1035 | #endif /* CONFIG_PPC_FAST_ENDIAN_SWITCH */ | |
d807ad37 NP |
1036 | |
1037 | #if defined(CONFIG_RELOCATABLE) | |
1038 | /* | |
1039 | * We can't branch directly so we do it via the CTR which | |
1040 | * is volatile across system calls. | |
1041 | */ | |
acd7d8ce NP |
1042 | #define SYSCALL_VIRT \ |
1043 | LOAD_SYSCALL_HANDLER(r10) ; \ | |
1044 | mtctr r10 ; \ | |
1045 | mfspr r11,SPRN_SRR0 ; \ | |
d807ad37 NP |
1046 | mfspr r12,SPRN_SRR1 ; \ |
1047 | li r10,MSR_RI ; \ | |
1048 | mtmsrd r10,1 ; \ | |
1049 | bctr ; | |
1050 | #else | |
1051 | /* We can branch directly */ | |
acd7d8ce NP |
1052 | #define SYSCALL_VIRT \ |
1053 | mfspr r11,SPRN_SRR0 ; \ | |
d807ad37 NP |
1054 | mfspr r12,SPRN_SRR1 ; \ |
1055 | li r10,MSR_RI ; \ | |
1056 | mtmsrd r10,1 ; /* Set RI (EE=0) */ \ | |
1057 | b system_call_common ; | |
1058 | #endif | |
1059 | ||
1a6822d1 | 1060 | EXC_REAL_BEGIN(system_call, 0xc00, 0x100) |
acd7d8ce NP |
1061 | SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */ |
1062 | SYSCALL_FASTENDIAN_TEST | |
1063 | SYSCALL_REAL | |
1064 | SYSCALL_FASTENDIAN | |
1a6822d1 | 1065 | EXC_REAL_END(system_call, 0xc00, 0x100) |
da2bc464 | 1066 | |
1a6822d1 | 1067 | EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100) |
acd7d8ce NP |
1068 | SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */ |
1069 | SYSCALL_FASTENDIAN_TEST | |
1070 | SYSCALL_VIRT | |
1071 | SYSCALL_FASTENDIAN | |
1a6822d1 | 1072 | EXC_VIRT_END(system_call, 0x4c00, 0x100) |
d807ad37 | 1073 | |
acd7d8ce NP |
1074 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
1075 | /* | |
1076 | * This is a hcall, so register convention is as above, with these | |
1077 | * differences: | |
1078 | * r13 = PACA | |
76fc0cfc NP |
1079 | * ctr = orig r13 |
1080 | * orig r10 saved in PACA | |
acd7d8ce NP |
1081 | */ |
1082 | TRAMP_KVM_BEGIN(do_kvm_0xc00) | |
1083 | /* | |
1084 | * Save the PPR (on systems that support it) before changing to | |
1085 | * HMT_MEDIUM. That allows the KVM code to save that value into the | |
1086 | * guest state (it is the guest's PPR value). | |
1087 | */ | |
76fc0cfc | 1088 | OPT_GET_SPR(r10, SPRN_PPR, CPU_FTR_HAS_PPR) |
acd7d8ce | 1089 | HMT_MEDIUM |
76fc0cfc | 1090 | OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r10, CPU_FTR_HAS_PPR) |
acd7d8ce | 1091 | mfctr r10 |
76fc0cfc | 1092 | SET_SCRATCH0(r10) |
acd7d8ce NP |
1093 | std r9,PACA_EXGEN+EX_R9(r13) |
1094 | mfcr r9 | |
acd7d8ce NP |
1095 | KVM_HANDLER(PACA_EXGEN, EXC_STD, 0xc00) |
1096 | #endif | |
da2bc464 | 1097 | |
d807ad37 | 1098 | |
1a6822d1 NP |
1099 | EXC_REAL(single_step, 0xd00, 0x100) |
1100 | EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00) | |
da2bc464 | 1101 | TRAMP_KVM(PACA_EXGEN, 0xd00) |
bc6675c6 | 1102 | EXC_COMMON(single_step_common, 0xd00, single_step_exception) |
b01c8b54 | 1103 | |
1a6822d1 | 1104 | EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20) |
da0e7e62 | 1105 | EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00) |
f5c32c1d NP |
1106 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) |
1107 | EXC_COMMON_BEGIN(h_data_storage_common) | |
1108 | mfspr r10,SPRN_HDAR | |
1109 | std r10,PACA_EXGEN+EX_DAR(r13) | |
1110 | mfspr r10,SPRN_HDSISR | |
1111 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
1112 | EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) | |
1113 | bl save_nvgprs | |
1114 | RECONCILE_IRQ_STATE(r10, r11) | |
1115 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1116 | bl unknown_exception | |
1117 | b ret_from_except | |
f5c32c1d | 1118 | |
1707dd16 | 1119 | |
1a6822d1 | 1120 | EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20) |
da0e7e62 | 1121 | EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20) |
82517cab NP |
1122 | TRAMP_KVM_HV(PACA_EXGEN, 0xe20) |
1123 | EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) | |
1124 | ||
1707dd16 | 1125 | |
1a6822d1 NP |
1126 | EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20) |
1127 | EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40) | |
031b4026 NP |
1128 | TRAMP_KVM_HV(PACA_EXGEN, 0xe40) |
1129 | EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) | |
1130 | ||
1707dd16 | 1131 | |
e0319829 NP |
1132 | /* |
1133 | * hmi_exception trampoline is a special case. It jumps to hmi_exception_early | |
1134 | * first, and then eventaully from there to the trampoline to get into virtual | |
1135 | * mode. | |
1136 | */ | |
1a6822d1 | 1137 | __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early) |
f14e953b | 1138 | __TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60, IRQS_DISABLED) |
1a6822d1 | 1139 | EXC_VIRT_NONE(0x4e60, 0x20) |
62f9b03b NP |
1140 | TRAMP_KVM_HV(PACA_EXGEN, 0xe60) |
1141 | TRAMP_REAL_BEGIN(hmi_exception_early) | |
1142 | EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60) | |
a4087a4d NP |
1143 | mr r10,r1 /* Save r1 */ |
1144 | ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */ | |
62f9b03b | 1145 | subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ |
62f9b03b | 1146 | mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ |
a4087a4d NP |
1147 | mfspr r12,SPRN_HSRR1 /* Save HSRR1 */ |
1148 | EXCEPTION_PROLOG_COMMON_1() | |
62f9b03b NP |
1149 | EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) |
1150 | EXCEPTION_PROLOG_COMMON_3(0xe60) | |
1151 | addi r3,r1,STACK_FRAME_OVERHEAD | |
be5c5e84 | 1152 | BRANCH_LINK_TO_FAR(hmi_exception_realmode) /* Function call ABI */ |
5080332c MN |
1153 | cmpdi cr0,r3,0 |
1154 | ||
62f9b03b NP |
1155 | /* Windup the stack. */ |
1156 | /* Move original HSRR0 and HSRR1 into the respective regs */ | |
1157 | ld r9,_MSR(r1) | |
1158 | mtspr SPRN_HSRR1,r9 | |
1159 | ld r3,_NIP(r1) | |
1160 | mtspr SPRN_HSRR0,r3 | |
1161 | ld r9,_CTR(r1) | |
1162 | mtctr r9 | |
1163 | ld r9,_XER(r1) | |
1164 | mtxer r9 | |
1165 | ld r9,_LINK(r1) | |
1166 | mtlr r9 | |
1167 | REST_GPR(0, r1) | |
1168 | REST_8GPRS(2, r1) | |
1169 | REST_GPR(10, r1) | |
1170 | ld r11,_CCR(r1) | |
5080332c MN |
1171 | REST_2GPRS(12, r1) |
1172 | bne 1f | |
62f9b03b NP |
1173 | mtcr r11 |
1174 | REST_GPR(11, r1) | |
5080332c | 1175 | ld r1,GPR1(r1) |
222f20f1 | 1176 | HRFI_TO_USER_OR_KERNEL |
5080332c MN |
1177 | |
1178 | 1: mtcr r11 | |
1179 | REST_GPR(11, r1) | |
62f9b03b NP |
1180 | ld r1,GPR1(r1) |
1181 | ||
1182 | /* | |
1183 | * Go to virtual mode and pull the HMI event information from | |
1184 | * firmware. | |
1185 | */ | |
1186 | .globl hmi_exception_after_realmode | |
1187 | hmi_exception_after_realmode: | |
1188 | SET_SCRATCH0(r13) | |
1189 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
1190 | b tramp_real_hmi_exception | |
1191 | ||
5080332c MN |
1192 | EXC_COMMON_BEGIN(hmi_exception_common) |
1193 | EXCEPTION_COMMON(PACA_EXGEN, 0xe60, hmi_exception_common, handle_hmi_exception, | |
1194 | ret_from_except, FINISH_NAP;ADD_NVGPRS;ADD_RECONCILE;RUNLATCH_ON) | |
1707dd16 | 1195 | |
f14e953b MS |
1196 | EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20, IRQS_DISABLED) |
1197 | EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80, IRQS_DISABLED) | |
9bcb81bf NP |
1198 | TRAMP_KVM_HV(PACA_EXGEN, 0xe80) |
1199 | #ifdef CONFIG_PPC_DOORBELL | |
1200 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) | |
1201 | #else | |
1202 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) | |
1203 | #endif | |
1204 | ||
0ebc4cda | 1205 | |
f14e953b MS |
1206 | EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20, IRQS_DISABLED) |
1207 | EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0, IRQS_DISABLED) | |
74408776 NP |
1208 | TRAMP_KVM_HV(PACA_EXGEN, 0xea0) |
1209 | EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) | |
1210 | ||
9baaef0a | 1211 | |
1a6822d1 NP |
1212 | EXC_REAL_NONE(0xec0, 0x20) |
1213 | EXC_VIRT_NONE(0x4ec0, 0x20) | |
1214 | EXC_REAL_NONE(0xee0, 0x20) | |
1215 | EXC_VIRT_NONE(0x4ee0, 0x20) | |
bda7fea2 | 1216 | |
0ebc4cda | 1217 | |
f442d004 MS |
1218 | EXC_REAL_OOL_MASKABLE(performance_monitor, 0xf00, 0x20, IRQS_PMI_DISABLED) |
1219 | EXC_VIRT_OOL_MASKABLE(performance_monitor, 0x4f00, 0x20, 0xf00, IRQS_PMI_DISABLED) | |
b1c7f150 NP |
1220 | TRAMP_KVM(PACA_EXGEN, 0xf00) |
1221 | EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) | |
1222 | ||
0ebc4cda | 1223 | |
1a6822d1 NP |
1224 | EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20) |
1225 | EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20) | |
d1a0ca9c NP |
1226 | TRAMP_KVM(PACA_EXGEN, 0xf20) |
1227 | EXC_COMMON_BEGIN(altivec_unavailable_common) | |
1228 | EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) | |
1229 | #ifdef CONFIG_ALTIVEC | |
1230 | BEGIN_FTR_SECTION | |
1231 | beq 1f | |
1232 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1233 | BEGIN_FTR_SECTION_NESTED(69) | |
1234 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1235 | * transaction), go do TM stuff | |
1236 | */ | |
1237 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1238 | bne- 2f | |
1239 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1240 | #endif | |
1241 | bl load_up_altivec | |
1242 | b fast_exception_return | |
1243 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1244 | 2: /* User process was in a transaction */ | |
1245 | bl save_nvgprs | |
1246 | RECONCILE_IRQ_STATE(r10, r11) | |
1247 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1248 | bl altivec_unavailable_tm | |
1249 | b ret_from_except | |
1250 | #endif | |
1251 | 1: | |
1252 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1253 | #endif | |
1254 | bl save_nvgprs | |
1255 | RECONCILE_IRQ_STATE(r10, r11) | |
1256 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1257 | bl altivec_unavailable_exception | |
1258 | b ret_from_except | |
1259 | ||
0ebc4cda | 1260 | |
1a6822d1 NP |
1261 | EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20) |
1262 | EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40) | |
792cbddd NP |
1263 | TRAMP_KVM(PACA_EXGEN, 0xf40) |
1264 | EXC_COMMON_BEGIN(vsx_unavailable_common) | |
1265 | EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) | |
1266 | #ifdef CONFIG_VSX | |
1267 | BEGIN_FTR_SECTION | |
1268 | beq 1f | |
1269 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1270 | BEGIN_FTR_SECTION_NESTED(69) | |
1271 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1272 | * transaction), go do TM stuff | |
1273 | */ | |
1274 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1275 | bne- 2f | |
1276 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1277 | #endif | |
1278 | b load_up_vsx | |
1279 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1280 | 2: /* User process was in a transaction */ | |
1281 | bl save_nvgprs | |
1282 | RECONCILE_IRQ_STATE(r10, r11) | |
1283 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1284 | bl vsx_unavailable_tm | |
1285 | b ret_from_except | |
1286 | #endif | |
1287 | 1: | |
1288 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
1289 | #endif | |
1290 | bl save_nvgprs | |
1291 | RECONCILE_IRQ_STATE(r10, r11) | |
1292 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1293 | bl vsx_unavailable_exception | |
1294 | b ret_from_except | |
1295 | ||
da2bc464 | 1296 | |
1a6822d1 NP |
1297 | EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20) |
1298 | EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60) | |
1134713c NP |
1299 | TRAMP_KVM(PACA_EXGEN, 0xf60) |
1300 | EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) | |
1301 | ||
da2bc464 | 1302 | |
1a6822d1 NP |
1303 | EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20) |
1304 | EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80) | |
14b0072c NP |
1305 | TRAMP_KVM_HV(PACA_EXGEN, 0xf80) |
1306 | EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) | |
1307 | ||
da2bc464 | 1308 | |
1a6822d1 NP |
1309 | EXC_REAL_NONE(0xfa0, 0x20) |
1310 | EXC_VIRT_NONE(0x4fa0, 0x20) | |
1311 | EXC_REAL_NONE(0xfc0, 0x20) | |
1312 | EXC_VIRT_NONE(0x4fc0, 0x20) | |
1313 | EXC_REAL_NONE(0xfe0, 0x20) | |
1314 | EXC_VIRT_NONE(0x4fe0, 0x20) | |
1315 | ||
1316 | EXC_REAL_NONE(0x1000, 0x100) | |
1317 | EXC_VIRT_NONE(0x5000, 0x100) | |
1318 | EXC_REAL_NONE(0x1100, 0x100) | |
1319 | EXC_VIRT_NONE(0x5100, 0x100) | |
d0c0c9a1 | 1320 | |
0ebc4cda | 1321 | #ifdef CONFIG_CBE_RAS |
1a6822d1 NP |
1322 | EXC_REAL_HV(cbe_system_error, 0x1200, 0x100) |
1323 | EXC_VIRT_NONE(0x5200, 0x100) | |
da2bc464 | 1324 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) |
ff1b3206 | 1325 | EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) |
da2bc464 | 1326 | #else /* CONFIG_CBE_RAS */ |
1a6822d1 NP |
1327 | EXC_REAL_NONE(0x1200, 0x100) |
1328 | EXC_VIRT_NONE(0x5200, 0x100) | |
da2bc464 | 1329 | #endif |
b01c8b54 | 1330 | |
ff1b3206 | 1331 | |
1a6822d1 NP |
1332 | EXC_REAL(instruction_breakpoint, 0x1300, 0x100) |
1333 | EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300) | |
da2bc464 | 1334 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) |
4e96dbbf NP |
1335 | EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) |
1336 | ||
1a6822d1 NP |
1337 | EXC_REAL_NONE(0x1400, 0x100) |
1338 | EXC_VIRT_NONE(0x5400, 0x100) | |
da2bc464 | 1339 | |
1a6822d1 | 1340 | EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100) |
b92a66a6 | 1341 | mtspr SPRN_SPRG_HSCRATCH0,r13 |
1707dd16 | 1342 | EXCEPTION_PROLOG_0(PACA_EXGEN) |
630573c1 | 1343 | EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500) |
b92a66a6 MN |
1344 | |
1345 | #ifdef CONFIG_PPC_DENORMALISATION | |
1346 | mfspr r10,SPRN_HSRR1 | |
afcf0095 | 1347 | andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ |
afcf0095 NP |
1348 | bne+ denorm_assist |
1349 | #endif | |
1e9b4507 | 1350 | |
4bb3c7a0 | 1351 | KVMTEST_HV(0x1500) |
cb58a4a4 | 1352 | EXCEPTION_PROLOG_2(denorm_common, EXC_HV) |
1a6822d1 | 1353 | EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100) |
a74599a5 | 1354 | |
d7e89849 | 1355 | #ifdef CONFIG_PPC_DENORMALISATION |
1a6822d1 | 1356 | EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100) |
d7e89849 | 1357 | b exc_real_0x1500_denorm_exception_hv |
1a6822d1 | 1358 | EXC_VIRT_END(denorm_exception, 0x5500, 0x100) |
d7e89849 | 1359 | #else |
1a6822d1 | 1360 | EXC_VIRT_NONE(0x5500, 0x100) |
afcf0095 NP |
1361 | #endif |
1362 | ||
4bb3c7a0 | 1363 | TRAMP_KVM_HV(PACA_EXGEN, 0x1500) |
b01c8b54 | 1364 | |
b92a66a6 | 1365 | #ifdef CONFIG_PPC_DENORMALISATION |
da2bc464 | 1366 | TRAMP_REAL_BEGIN(denorm_assist) |
b92a66a6 MN |
1367 | BEGIN_FTR_SECTION |
1368 | /* | |
1369 | * To denormalise we need to move a copy of the register to itself. | |
1370 | * For POWER6 do that here for all FP regs. | |
1371 | */ | |
1372 | mfmsr r10 | |
1373 | ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) | |
1374 | xori r10,r10,(MSR_FE0|MSR_FE1) | |
1375 | mtmsrd r10 | |
1376 | sync | |
d7c67fb1 MN |
1377 | |
1378 | #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1 | |
1379 | #define FMR4(n) FMR2(n) ; FMR2(n+2) | |
1380 | #define FMR8(n) FMR4(n) ; FMR4(n+4) | |
1381 | #define FMR16(n) FMR8(n) ; FMR8(n+8) | |
1382 | #define FMR32(n) FMR16(n) ; FMR16(n+16) | |
1383 | FMR32(0) | |
1384 | ||
b92a66a6 MN |
1385 | FTR_SECTION_ELSE |
1386 | /* | |
1387 | * To denormalise we need to move a copy of the register to itself. | |
1388 | * For POWER7 do that here for the first 32 VSX registers only. | |
1389 | */ | |
1390 | mfmsr r10 | |
1391 | oris r10,r10,MSR_VSX@h | |
1392 | mtmsrd r10 | |
1393 | sync | |
d7c67fb1 MN |
1394 | |
1395 | #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1) | |
1396 | #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2) | |
1397 | #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4) | |
1398 | #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8) | |
1399 | #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16) | |
1400 | XVCPSGNDP32(0) | |
1401 | ||
b92a66a6 | 1402 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) |
fb0fce3e MN |
1403 | |
1404 | BEGIN_FTR_SECTION | |
1405 | b denorm_done | |
1406 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
1407 | /* | |
1408 | * To denormalise we need to move a copy of the register to itself. | |
1409 | * For POWER8 we need to do that for all 64 VSX registers | |
1410 | */ | |
1411 | XVCPSGNDP32(32) | |
1412 | denorm_done: | |
f14040bc MN |
1413 | mfspr r11,SPRN_HSRR0 |
1414 | subi r11,r11,4 | |
b92a66a6 MN |
1415 | mtspr SPRN_HSRR0,r11 |
1416 | mtcrf 0x80,r9 | |
1417 | ld r9,PACA_EXGEN+EX_R9(r13) | |
44e9309f | 1418 | RESTORE_PPR_PACA(PACA_EXGEN, r10) |
630573c1 PM |
1419 | BEGIN_FTR_SECTION |
1420 | ld r10,PACA_EXGEN+EX_CFAR(r13) | |
1421 | mtspr SPRN_CFAR,r10 | |
1422 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
b92a66a6 MN |
1423 | ld r10,PACA_EXGEN+EX_R10(r13) |
1424 | ld r11,PACA_EXGEN+EX_R11(r13) | |
1425 | ld r12,PACA_EXGEN+EX_R12(r13) | |
1426 | ld r13,PACA_EXGEN+EX_R13(r13) | |
222f20f1 | 1427 | HRFI_TO_UNKNOWN |
b92a66a6 MN |
1428 | b . |
1429 | #endif | |
1430 | ||
872e2ae4 | 1431 | EXC_COMMON(denorm_common, 0x1500, unknown_exception) |
d7e89849 NP |
1432 | |
1433 | ||
1434 | #ifdef CONFIG_CBE_RAS | |
1a6822d1 NP |
1435 | EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100) |
1436 | EXC_VIRT_NONE(0x5600, 0x100) | |
d7e89849 | 1437 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) |
69a79344 | 1438 | EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) |
d7e89849 | 1439 | #else /* CONFIG_CBE_RAS */ |
1a6822d1 NP |
1440 | EXC_REAL_NONE(0x1600, 0x100) |
1441 | EXC_VIRT_NONE(0x5600, 0x100) | |
d7e89849 NP |
1442 | #endif |
1443 | ||
69a79344 | 1444 | |
1a6822d1 NP |
1445 | EXC_REAL(altivec_assist, 0x1700, 0x100) |
1446 | EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700) | |
d7e89849 | 1447 | TRAMP_KVM(PACA_EXGEN, 0x1700) |
b51c079e NP |
1448 | #ifdef CONFIG_ALTIVEC |
1449 | EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) | |
1450 | #else | |
1451 | EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) | |
1452 | #endif | |
1453 | ||
d7e89849 NP |
1454 | |
1455 | #ifdef CONFIG_CBE_RAS | |
1a6822d1 NP |
1456 | EXC_REAL_HV(cbe_thermal, 0x1800, 0x100) |
1457 | EXC_VIRT_NONE(0x5800, 0x100) | |
d7e89849 | 1458 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) |
3965f8ab | 1459 | EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) |
d7e89849 | 1460 | #else /* CONFIG_CBE_RAS */ |
1a6822d1 NP |
1461 | EXC_REAL_NONE(0x1800, 0x100) |
1462 | EXC_VIRT_NONE(0x5800, 0x100) | |
d7e89849 NP |
1463 | #endif |
1464 | ||
75eb767e | 1465 | #ifdef CONFIG_PPC_WATCHDOG |
2104180a NP |
1466 | |
1467 | #define MASKED_DEC_HANDLER_LABEL 3f | |
1468 | ||
1469 | #define MASKED_DEC_HANDLER(_H) \ | |
1470 | 3: /* soft-nmi */ \ | |
1471 | std r12,PACA_EXGEN+EX_R12(r13); \ | |
1472 | GET_SCRATCH0(r10); \ | |
1473 | std r10,PACA_EXGEN+EX_R13(r13); \ | |
cb58a4a4 | 1474 | EXCEPTION_PROLOG_2(soft_nmi_common, _H) |
2104180a | 1475 | |
cc491f1d NP |
1476 | /* |
1477 | * Branch to soft_nmi_interrupt using the emergency stack. The emergency | |
1478 | * stack is one that is usable by maskable interrupts so long as MSR_EE | |
1479 | * remains off. It is used for recovery when something has corrupted the | |
1480 | * normal kernel stack, for example. The "soft NMI" must not use the process | |
1481 | * stack because we want irq disabled sections to avoid touching the stack | |
1482 | * at all (other than PMU interrupts), so use the emergency stack for this, | |
1483 | * and run it entirely with interrupts hard disabled. | |
1484 | */ | |
2104180a NP |
1485 | EXC_COMMON_BEGIN(soft_nmi_common) |
1486 | mr r10,r1 | |
1487 | ld r1,PACAEMERGSP(r13) | |
2104180a NP |
1488 | subi r1,r1,INT_FRAME_SIZE |
1489 | EXCEPTION_COMMON_NORET_STACK(PACA_EXGEN, 0x900, | |
1490 | system_reset, soft_nmi_interrupt, | |
1491 | ADD_NVGPRS;ADD_RECONCILE) | |
1492 | b ret_from_except | |
1493 | ||
75eb767e | 1494 | #else /* CONFIG_PPC_WATCHDOG */ |
2104180a NP |
1495 | #define MASKED_DEC_HANDLER_LABEL 2f /* normal return */ |
1496 | #define MASKED_DEC_HANDLER(_H) | |
75eb767e | 1497 | #endif /* CONFIG_PPC_WATCHDOG */ |
d7e89849 | 1498 | |
0ebc4cda | 1499 | /* |
fe9e1d54 IM |
1500 | * An interrupt came in while soft-disabled. We set paca->irq_happened, then: |
1501 | * - If it was a decrementer interrupt, we bump the dec to max and and return. | |
1502 | * - If it was a doorbell we return immediately since doorbells are edge | |
1503 | * triggered and won't automatically refire. | |
0869b6fd MS |
1504 | * - If it was a HMI we return immediately since we handled it in realmode |
1505 | * and it won't refire. | |
6cc3f91b | 1506 | * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return. |
fe9e1d54 | 1507 | * This is called with r10 containing the value to OR to the paca field. |
0ebc4cda | 1508 | */ |
7230c564 BH |
1509 | #define MASKED_INTERRUPT(_H) \ |
1510 | masked_##_H##interrupt: \ | |
1511 | std r11,PACA_EXGEN+EX_R11(r13); \ | |
1512 | lbz r11,PACAIRQHAPPENED(r13); \ | |
1513 | or r11,r11,r10; \ | |
1514 | stb r11,PACAIRQHAPPENED(r13); \ | |
fe9e1d54 IM |
1515 | cmpwi r10,PACA_IRQ_DEC; \ |
1516 | bne 1f; \ | |
7230c564 BH |
1517 | lis r10,0x7fff; \ |
1518 | ori r10,r10,0xffff; \ | |
1519 | mtspr SPRN_DEC,r10; \ | |
2104180a | 1520 | b MASKED_DEC_HANDLER_LABEL; \ |
6cc3f91b NP |
1521 | 1: andi. r10,r10,PACA_IRQ_MUST_HARD_MASK; \ |
1522 | beq 2f; \ | |
fe9e1d54 | 1523 | mfspr r10,SPRN_##_H##SRR1; \ |
6e9a2f6e | 1524 | xori r10,r10,MSR_EE; /* clear MSR_EE */ \ |
7230c564 | 1525 | mtspr SPRN_##_H##SRR1,r10; \ |
9b81c021 NP |
1526 | ori r11,r11,PACA_IRQ_HARD_DIS; \ |
1527 | stb r11,PACAIRQHAPPENED(r13); \ | |
1528 | 2: /* done */ \ | |
1529 | mtcrf 0x80,r9; \ | |
7b08729c | 1530 | std r1,PACAR1(r13); \ |
7230c564 BH |
1531 | ld r9,PACA_EXGEN+EX_R9(r13); \ |
1532 | ld r10,PACA_EXGEN+EX_R10(r13); \ | |
1533 | ld r11,PACA_EXGEN+EX_R11(r13); \ | |
c05f0be8 | 1534 | /* returns to kernel where r13 must be set up, so don't restore it */ \ |
222f20f1 | 1535 | ##_H##RFI_TO_KERNEL; \ |
2104180a NP |
1536 | b .; \ |
1537 | MASKED_DEC_HANDLER(_H) | |
57f26649 | 1538 | |
a048a07d NP |
1539 | TRAMP_REAL_BEGIN(stf_barrier_fallback) |
1540 | std r9,PACA_EXRFI+EX_R9(r13) | |
1541 | std r10,PACA_EXRFI+EX_R10(r13) | |
1542 | sync | |
1543 | ld r9,PACA_EXRFI+EX_R9(r13) | |
1544 | ld r10,PACA_EXRFI+EX_R10(r13) | |
1545 | ori 31,31,0 | |
1546 | .rept 14 | |
1547 | b 1f | |
1548 | 1: | |
1549 | .endr | |
1550 | blr | |
1551 | ||
aa8a5e00 ME |
1552 | TRAMP_REAL_BEGIN(rfi_flush_fallback) |
1553 | SET_SCRATCH0(r13); | |
1554 | GET_PACA(r13); | |
78ee9946 ME |
1555 | std r1,PACA_EXRFI+EX_R12(r13) |
1556 | ld r1,PACAKSAVE(r13) | |
aa8a5e00 ME |
1557 | std r9,PACA_EXRFI+EX_R9(r13) |
1558 | std r10,PACA_EXRFI+EX_R10(r13) | |
1559 | std r11,PACA_EXRFI+EX_R11(r13) | |
aa8a5e00 ME |
1560 | mfctr r9 |
1561 | ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) | |
bdcb1aef NP |
1562 | ld r11,PACA_L1D_FLUSH_SIZE(r13) |
1563 | srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ | |
aa8a5e00 | 1564 | mtctr r11 |
15a3204d | 1565 | DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ |
aa8a5e00 ME |
1566 | |
1567 | /* order ld/st prior to dcbt stop all streams with flushing */ | |
1568 | sync | |
bdcb1aef NP |
1569 | |
1570 | /* | |
1571 | * The load adresses are at staggered offsets within cachelines, | |
1572 | * which suits some pipelines better (on others it should not | |
1573 | * hurt). | |
1574 | */ | |
1575 | 1: | |
1576 | ld r11,(0x80 + 8)*0(r10) | |
1577 | ld r11,(0x80 + 8)*1(r10) | |
1578 | ld r11,(0x80 + 8)*2(r10) | |
1579 | ld r11,(0x80 + 8)*3(r10) | |
1580 | ld r11,(0x80 + 8)*4(r10) | |
1581 | ld r11,(0x80 + 8)*5(r10) | |
1582 | ld r11,(0x80 + 8)*6(r10) | |
1583 | ld r11,(0x80 + 8)*7(r10) | |
1584 | addi r10,r10,0x80*8 | |
aa8a5e00 ME |
1585 | bdnz 1b |
1586 | ||
1587 | mtctr r9 | |
1588 | ld r9,PACA_EXRFI+EX_R9(r13) | |
1589 | ld r10,PACA_EXRFI+EX_R10(r13) | |
1590 | ld r11,PACA_EXRFI+EX_R11(r13) | |
78ee9946 | 1591 | ld r1,PACA_EXRFI+EX_R12(r13) |
aa8a5e00 ME |
1592 | GET_SCRATCH0(r13); |
1593 | rfid | |
1594 | ||
1595 | TRAMP_REAL_BEGIN(hrfi_flush_fallback) | |
1596 | SET_SCRATCH0(r13); | |
1597 | GET_PACA(r13); | |
78ee9946 ME |
1598 | std r1,PACA_EXRFI+EX_R12(r13) |
1599 | ld r1,PACAKSAVE(r13) | |
aa8a5e00 ME |
1600 | std r9,PACA_EXRFI+EX_R9(r13) |
1601 | std r10,PACA_EXRFI+EX_R10(r13) | |
1602 | std r11,PACA_EXRFI+EX_R11(r13) | |
aa8a5e00 ME |
1603 | mfctr r9 |
1604 | ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) | |
bdcb1aef NP |
1605 | ld r11,PACA_L1D_FLUSH_SIZE(r13) |
1606 | srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ | |
aa8a5e00 | 1607 | mtctr r11 |
15a3204d | 1608 | DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ |
aa8a5e00 ME |
1609 | |
1610 | /* order ld/st prior to dcbt stop all streams with flushing */ | |
1611 | sync | |
bdcb1aef NP |
1612 | |
1613 | /* | |
1614 | * The load adresses are at staggered offsets within cachelines, | |
1615 | * which suits some pipelines better (on others it should not | |
1616 | * hurt). | |
1617 | */ | |
1618 | 1: | |
1619 | ld r11,(0x80 + 8)*0(r10) | |
1620 | ld r11,(0x80 + 8)*1(r10) | |
1621 | ld r11,(0x80 + 8)*2(r10) | |
1622 | ld r11,(0x80 + 8)*3(r10) | |
1623 | ld r11,(0x80 + 8)*4(r10) | |
1624 | ld r11,(0x80 + 8)*5(r10) | |
1625 | ld r11,(0x80 + 8)*6(r10) | |
1626 | ld r11,(0x80 + 8)*7(r10) | |
1627 | addi r10,r10,0x80*8 | |
aa8a5e00 ME |
1628 | bdnz 1b |
1629 | ||
1630 | mtctr r9 | |
1631 | ld r9,PACA_EXRFI+EX_R9(r13) | |
1632 | ld r10,PACA_EXRFI+EX_R10(r13) | |
1633 | ld r11,PACA_EXRFI+EX_R11(r13) | |
78ee9946 | 1634 | ld r1,PACA_EXRFI+EX_R12(r13) |
aa8a5e00 ME |
1635 | GET_SCRATCH0(r13); |
1636 | hrfid | |
1637 | ||
57f26649 NP |
1638 | /* |
1639 | * Real mode exceptions actually use this too, but alternate | |
1640 | * instruction code patches (which end up in the common .text area) | |
1641 | * cannot reach these if they are put there. | |
1642 | */ | |
1643 | USE_FIXED_SECTION(virt_trampolines) | |
7230c564 BH |
1644 | MASKED_INTERRUPT() |
1645 | MASKED_INTERRUPT(H) | |
0ebc4cda | 1646 | |
4f6c11db | 1647 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
da2bc464 | 1648 | TRAMP_REAL_BEGIN(kvmppc_skip_interrupt) |
4f6c11db PM |
1649 | /* |
1650 | * Here all GPRs are unchanged from when the interrupt happened | |
1651 | * except for r13, which is saved in SPRG_SCRATCH0. | |
1652 | */ | |
1653 | mfspr r13, SPRN_SRR0 | |
1654 | addi r13, r13, 4 | |
1655 | mtspr SPRN_SRR0, r13 | |
1656 | GET_SCRATCH0(r13) | |
222f20f1 | 1657 | RFI_TO_KERNEL |
4f6c11db PM |
1658 | b . |
1659 | ||
da2bc464 | 1660 | TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) |
4f6c11db PM |
1661 | /* |
1662 | * Here all GPRs are unchanged from when the interrupt happened | |
1663 | * except for r13, which is saved in SPRG_SCRATCH0. | |
1664 | */ | |
1665 | mfspr r13, SPRN_HSRR0 | |
1666 | addi r13, r13, 4 | |
1667 | mtspr SPRN_HSRR0, r13 | |
1668 | GET_SCRATCH0(r13) | |
222f20f1 | 1669 | HRFI_TO_KERNEL |
4f6c11db PM |
1670 | b . |
1671 | #endif | |
1672 | ||
0ebc4cda | 1673 | /* |
057b6d7e HB |
1674 | * Ensure that any handlers that get invoked from the exception prologs |
1675 | * above are below the first 64KB (0x10000) of the kernel image because | |
1676 | * the prologs assemble the addresses of these handlers using the | |
1677 | * LOAD_HANDLER macro, which uses an ori instruction. | |
0ebc4cda BH |
1678 | */ |
1679 | ||
1680 | /*** Common interrupt handlers ***/ | |
1681 | ||
0ebc4cda | 1682 | |
c1fb6816 MN |
1683 | /* |
1684 | * Relocation-on interrupts: A subset of the interrupts can be delivered | |
1685 | * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering | |
1686 | * it. Addresses are the same as the original interrupt addresses, but | |
1687 | * offset by 0xc000000000004000. | |
1688 | * It's impossible to receive interrupts below 0x300 via this mechanism. | |
1689 | * KVM: None of these traps are from the guest ; anything that escalated | |
1690 | * to HV=1 from HV=0 is delivered via real mode handlers. | |
1691 | */ | |
1692 | ||
1693 | /* | |
1694 | * This uses the standard macro, since the original 0x300 vector | |
1695 | * only has extra guff for STAB-based processors -- which never | |
1696 | * come here. | |
1697 | */ | |
da2bc464 | 1698 | |
57f26649 | 1699 | EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) |
b1576fec | 1700 | b __ppc64_runlatch_on |
fe1952fc | 1701 | |
57f26649 | 1702 | USE_FIXED_SECTION(virt_trampolines) |
8ed8ab40 HB |
1703 | /* |
1704 | * The __end_interrupts marker must be past the out-of-line (OOL) | |
1705 | * handlers, so that they are copied to real address 0x100 when running | |
1706 | * a relocatable kernel. This ensures they can be reached from the short | |
1707 | * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch | |
1708 | * directly, without using LOAD_HANDLER(). | |
1709 | */ | |
1710 | .align 7 | |
1711 | .globl __end_interrupts | |
1712 | __end_interrupts: | |
57f26649 | 1713 | DEFINE_FIXED_SYMBOL(__end_interrupts) |
61383407 | 1714 | |
087aa036 | 1715 | #ifdef CONFIG_PPC_970_NAP |
7c8cb4b5 | 1716 | EXC_COMMON_BEGIN(power4_fixup_nap) |
087aa036 CG |
1717 | andc r9,r9,r10 |
1718 | std r9,TI_LOCAL_FLAGS(r11) | |
1719 | ld r10,_LINK(r1) /* make idle task do the */ | |
1720 | std r10,_NIP(r1) /* equivalent of a blr */ | |
1721 | blr | |
1722 | #endif | |
1723 | ||
57f26649 NP |
1724 | CLOSE_FIXED_SECTION(real_vectors); |
1725 | CLOSE_FIXED_SECTION(real_trampolines); | |
1726 | CLOSE_FIXED_SECTION(virt_vectors); | |
1727 | CLOSE_FIXED_SECTION(virt_trampolines); | |
1728 | ||
1729 | USE_TEXT_SECTION() | |
1730 | ||
0ebc4cda BH |
1731 | /* |
1732 | * Hash table stuff | |
1733 | */ | |
f4329f2e | 1734 | .balign IFETCH_ALIGN_BYTES |
6a3bab90 | 1735 | do_hash_page: |
4e003747 | 1736 | #ifdef CONFIG_PPC_BOOK3S_64 |
e6c2a479 | 1737 | lis r0,(DSISR_BAD_FAULT_64S | DSISR_DABRMATCH | DSISR_KEYFAULT)@h |
398a719d BH |
1738 | ori r0,r0,DSISR_BAD_FAULT_64S@l |
1739 | and. r0,r4,r0 /* weird error? */ | |
0ebc4cda | 1740 | bne- handle_page_fault /* if not, try to insert a HPTE */ |
9778b696 | 1741 | CURRENT_THREAD_INFO(r11, r1) |
9c1e1052 PM |
1742 | lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ |
1743 | andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ | |
1744 | bne 77f /* then don't call hash_page now */ | |
0ebc4cda BH |
1745 | |
1746 | /* | |
1747 | * r3 contains the faulting address | |
106713a1 | 1748 | * r4 msr |
0ebc4cda | 1749 | * r5 contains the trap number |
aefa5688 | 1750 | * r6 contains dsisr |
0ebc4cda | 1751 | * |
7230c564 | 1752 | * at return r3 = 0 for success, 1 for page fault, negative for error |
0ebc4cda | 1753 | */ |
106713a1 | 1754 | mr r4,r12 |
aefa5688 | 1755 | ld r6,_DSISR(r1) |
106713a1 AK |
1756 | bl __hash_page /* build HPTE if possible */ |
1757 | cmpdi r3,0 /* see if __hash_page succeeded */ | |
0ebc4cda | 1758 | |
7230c564 | 1759 | /* Success */ |
0ebc4cda | 1760 | beq fast_exc_return_irq /* Return from exception on success */ |
0ebc4cda | 1761 | |
7230c564 BH |
1762 | /* Error */ |
1763 | blt- 13f | |
d89ba535 NR |
1764 | |
1765 | /* Reload DSISR into r4 for the DABR check below */ | |
1766 | ld r4,_DSISR(r1) | |
4e003747 | 1767 | #endif /* CONFIG_PPC_BOOK3S_64 */ |
9c7cc234 | 1768 | |
0ebc4cda BH |
1769 | /* Here we have a page fault that hash_page can't handle. */ |
1770 | handle_page_fault: | |
d89ba535 NR |
1771 | 11: andis. r0,r4,DSISR_DABRMATCH@h |
1772 | bne- handle_dabr_fault | |
1773 | ld r4,_DAR(r1) | |
0ebc4cda BH |
1774 | ld r5,_DSISR(r1) |
1775 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec | 1776 | bl do_page_fault |
0ebc4cda | 1777 | cmpdi r3,0 |
a546498f | 1778 | beq+ 12f |
b1576fec | 1779 | bl save_nvgprs |
0ebc4cda BH |
1780 | mr r5,r3 |
1781 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1782 | lwz r4,_DAR(r1) | |
b1576fec AB |
1783 | bl bad_page_fault |
1784 | b ret_from_except | |
0ebc4cda | 1785 | |
a546498f BH |
1786 | /* We have a data breakpoint exception - handle it */ |
1787 | handle_dabr_fault: | |
b1576fec | 1788 | bl save_nvgprs |
a546498f BH |
1789 | ld r4,_DAR(r1) |
1790 | ld r5,_DSISR(r1) | |
1791 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec AB |
1792 | bl do_break |
1793 | 12: b ret_from_except_lite | |
a546498f | 1794 | |
0ebc4cda | 1795 | |
4e003747 | 1796 | #ifdef CONFIG_PPC_BOOK3S_64 |
0ebc4cda BH |
1797 | /* We have a page fault that hash_page could handle but HV refused |
1798 | * the PTE insertion | |
1799 | */ | |
b1576fec | 1800 | 13: bl save_nvgprs |
0ebc4cda BH |
1801 | mr r5,r3 |
1802 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1803 | ld r4,_DAR(r1) | |
b1576fec AB |
1804 | bl low_hash_fault |
1805 | b ret_from_except | |
caca285e | 1806 | #endif |
0ebc4cda | 1807 | |
9c1e1052 PM |
1808 | /* |
1809 | * We come here as a result of a DSI at a point where we don't want | |
1810 | * to call hash_page, such as when we are accessing memory (possibly | |
1811 | * user memory) inside a PMU interrupt that occurred while interrupts | |
1812 | * were soft-disabled. We want to invoke the exception handler for | |
1813 | * the access, or panic if there isn't a handler. | |
1814 | */ | |
b1576fec | 1815 | 77: bl save_nvgprs |
9c1e1052 PM |
1816 | mr r4,r3 |
1817 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1818 | li r5,SIGSEGV | |
b1576fec AB |
1819 | bl bad_page_fault |
1820 | b ret_from_except | |
4e2bf01b ME |
1821 | |
1822 | /* | |
1823 | * Here we have detected that the kernel stack pointer is bad. | |
1824 | * R9 contains the saved CR, r13 points to the paca, | |
1825 | * r10 contains the (bad) kernel stack pointer, | |
1826 | * r11 and r12 contain the saved SRR0 and SRR1. | |
1827 | * We switch to using an emergency stack, save the registers there, | |
1828 | * and call kernel_bad_stack(), which panics. | |
1829 | */ | |
1830 | bad_stack: | |
1831 | ld r1,PACAEMERGSP(r13) | |
1832 | subi r1,r1,64+INT_FRAME_SIZE | |
1833 | std r9,_CCR(r1) | |
1834 | std r10,GPR1(r1) | |
1835 | std r11,_NIP(r1) | |
1836 | std r12,_MSR(r1) | |
1837 | mfspr r11,SPRN_DAR | |
1838 | mfspr r12,SPRN_DSISR | |
1839 | std r11,_DAR(r1) | |
1840 | std r12,_DSISR(r1) | |
1841 | mflr r10 | |
1842 | mfctr r11 | |
1843 | mfxer r12 | |
1844 | std r10,_LINK(r1) | |
1845 | std r11,_CTR(r1) | |
1846 | std r12,_XER(r1) | |
1847 | SAVE_GPR(0,r1) | |
1848 | SAVE_GPR(2,r1) | |
1849 | ld r10,EX_R3(r3) | |
1850 | std r10,GPR3(r1) | |
1851 | SAVE_GPR(4,r1) | |
1852 | SAVE_4GPRS(5,r1) | |
1853 | ld r9,EX_R9(r3) | |
1854 | ld r10,EX_R10(r3) | |
1855 | SAVE_2GPRS(9,r1) | |
1856 | ld r9,EX_R11(r3) | |
1857 | ld r10,EX_R12(r3) | |
1858 | ld r11,EX_R13(r3) | |
1859 | std r9,GPR11(r1) | |
1860 | std r10,GPR12(r1) | |
1861 | std r11,GPR13(r1) | |
1862 | BEGIN_FTR_SECTION | |
1863 | ld r10,EX_CFAR(r3) | |
1864 | std r10,ORIG_GPR3(r1) | |
1865 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
1866 | SAVE_8GPRS(14,r1) | |
1867 | SAVE_10GPRS(22,r1) | |
1868 | lhz r12,PACA_TRAP_SAVE(r13) | |
1869 | std r12,_TRAP(r1) | |
1870 | addi r11,r1,INT_FRAME_SIZE | |
1871 | std r11,0(r1) | |
1872 | li r12,0 | |
1873 | std r12,0(r11) | |
1874 | ld r2,PACATOC(r13) | |
1875 | ld r11,exception_marker@toc(r2) | |
1876 | std r12,RESULT(r1) | |
1877 | std r11,STACK_FRAME_OVERHEAD-16(r1) | |
1878 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
1879 | bl kernel_bad_stack | |
1880 | b 1b | |
15770a13 | 1881 | _ASM_NOKPROBE_SYMBOL(bad_stack); |
0f0c6ca1 | 1882 | |
a9af97aa NP |
1883 | /* |
1884 | * When doorbell is triggered from system reset wakeup, the message is | |
1885 | * not cleared, so it would fire again when EE is enabled. | |
1886 | * | |
1887 | * When coming from local_irq_enable, there may be the same problem if | |
1888 | * we were hard disabled. | |
1889 | * | |
1890 | * Execute msgclr to clear pending exceptions before handling it. | |
1891 | */ | |
1892 | h_doorbell_common_msgclr: | |
1893 | LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) | |
1894 | PPC_MSGCLR(3) | |
1895 | b h_doorbell_common | |
1896 | ||
1897 | doorbell_super_common_msgclr: | |
1898 | LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) | |
1899 | PPC_MSGCLRP(3) | |
1900 | b doorbell_super_common | |
1901 | ||
0f0c6ca1 NP |
1902 | /* |
1903 | * Called from arch_local_irq_enable when an interrupt needs | |
1904 | * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate | |
1905 | * which kind of interrupt. MSR:EE is already off. We generate a | |
1906 | * stackframe like if a real interrupt had happened. | |
1907 | * | |
1908 | * Note: While MSR:EE is off, we need to make sure that _MSR | |
1909 | * in the generated frame has EE set to 1 or the exception | |
1910 | * handler will not properly re-enable them. | |
b48bbb82 NP |
1911 | * |
1912 | * Note that we don't specify LR as the NIP (return address) for | |
1913 | * the interrupt because that would unbalance the return branch | |
1914 | * predictor. | |
0f0c6ca1 NP |
1915 | */ |
1916 | _GLOBAL(__replay_interrupt) | |
1917 | /* We are going to jump to the exception common code which | |
1918 | * will retrieve various register values from the PACA which | |
1919 | * we don't give a damn about, so we don't bother storing them. | |
1920 | */ | |
1921 | mfmsr r12 | |
3e23a12b | 1922 | LOAD_REG_ADDR(r11, replay_interrupt_return) |
0f0c6ca1 NP |
1923 | mfcr r9 |
1924 | ori r12,r12,MSR_EE | |
1925 | cmpwi r3,0x900 | |
1926 | beq decrementer_common | |
1927 | cmpwi r3,0x500 | |
e6c1203d NP |
1928 | BEGIN_FTR_SECTION |
1929 | beq h_virt_irq_common | |
1930 | FTR_SECTION_ELSE | |
0f0c6ca1 | 1931 | beq hardware_interrupt_common |
e6c1203d | 1932 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_300) |
f442d004 MS |
1933 | cmpwi r3,0xf00 |
1934 | beq performance_monitor_common | |
0f0c6ca1 | 1935 | BEGIN_FTR_SECTION |
d6f73fc6 | 1936 | cmpwi r3,0xa00 |
a9af97aa | 1937 | beq h_doorbell_common_msgclr |
0f0c6ca1 NP |
1938 | cmpwi r3,0xe60 |
1939 | beq hmi_exception_common | |
1940 | FTR_SECTION_ELSE | |
1941 | cmpwi r3,0xa00 | |
a9af97aa | 1942 | beq doorbell_super_common_msgclr |
0f0c6ca1 | 1943 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
3e23a12b | 1944 | replay_interrupt_return: |
0f0c6ca1 | 1945 | blr |
b48bbb82 | 1946 | |
15770a13 | 1947 | _ASM_NOKPROBE_SYMBOL(__replay_interrupt) |