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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
0ebc4cda BH |
2 | /* |
3 | * This file contains the 64-bit "server" PowerPC variant | |
4 | * of the low level exception handling including exception | |
5 | * vectors, exception return, part of the slb and stab | |
6 | * handling and other fixed offset specific things. | |
7 | * | |
8 | * This file is meant to be #included from head_64.S due to | |
25985edc | 9 | * position dependent assembly. |
0ebc4cda BH |
10 | * |
11 | * Most of this originates from head_64.S and thus has the same | |
12 | * copyright history. | |
13 | * | |
14 | */ | |
15 | ||
7230c564 | 16 | #include <asm/hw_irq.h> |
8aa34ab8 | 17 | #include <asm/exception-64s.h> |
46f52210 | 18 | #include <asm/ptrace.h> |
7cba160a | 19 | #include <asm/cpuidle.h> |
da2bc464 | 20 | #include <asm/head-64.h> |
2c86cd18 | 21 | #include <asm/feature-fixups.h> |
8aa34ab8 | 22 | |
0ebc4cda | 23 | /* |
57f26649 NP |
24 | * There are a few constraints to be concerned with. |
25 | * - Real mode exceptions code/data must be located at their physical location. | |
26 | * - Virtual mode exceptions must be mapped at their 0xc000... location. | |
27 | * - Fixed location code must not call directly beyond the __end_interrupts | |
28 | * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence | |
29 | * must be used. | |
30 | * - LOAD_HANDLER targets must be within first 64K of physical 0 / | |
31 | * virtual 0xc00... | |
32 | * - Conditional branch targets must be within +/-32K of caller. | |
33 | * | |
34 | * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and | |
35 | * therefore don't have to run in physically located code or rfid to | |
36 | * virtual mode kernel code. However on relocatable kernels they do have | |
37 | * to branch to KERNELBASE offset because the rest of the kernel (outside | |
38 | * the exception vectors) may be located elsewhere. | |
39 | * | |
40 | * Virtual exceptions correspond with physical, except their entry points | |
41 | * are offset by 0xc000000000000000 and also tend to get an added 0x4000 | |
42 | * offset applied. Virtual exceptions are enabled with the Alternate | |
43 | * Interrupt Location (AIL) bit set in the LPCR. However this does not | |
44 | * guarantee they will be delivered virtually. Some conditions (see the ISA) | |
45 | * cause exceptions to be delivered in real mode. | |
46 | * | |
47 | * It's impossible to receive interrupts below 0x300 via AIL. | |
48 | * | |
49 | * KVM: None of the virtual exceptions are from the guest. Anything that | |
50 | * escalated to HV=1 from HV=0 is delivered via real mode handlers. | |
51 | * | |
52 | * | |
0ebc4cda BH |
53 | * We layout physical memory as follows: |
54 | * 0x0000 - 0x00ff : Secondary processor spin code | |
57f26649 NP |
55 | * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors |
56 | * 0x1900 - 0x3fff : Real mode trampolines | |
57 | * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors | |
58 | * 0x5900 - 0x6fff : Relon mode trampolines | |
0ebc4cda | 59 | * 0x7000 - 0x7fff : FWNMI data area |
57f26649 NP |
60 | * 0x8000 - .... : Common interrupt handlers, remaining early |
61 | * setup code, rest of kernel. | |
e0319829 NP |
62 | * |
63 | * We could reclaim 0x4000-0x42ff for real mode trampolines if the space | |
64 | * is necessary. Until then it's more consistent to explicitly put VIRT_NONE | |
65 | * vectors there. | |
57f26649 NP |
66 | */ |
67 | OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) | |
68 | OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000) | |
69 | OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900) | |
70 | OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) | |
71 | #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) | |
72 | /* | |
73 | * Data area reserved for FWNMI option. | |
74 | * This address (0x7000) is fixed by the RPA. | |
75 | * pseries and powernv need to keep the whole page from | |
76 | * 0x7000 to 0x8000 free for use by the firmware | |
0ebc4cda | 77 | */ |
57f26649 NP |
78 | ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) |
79 | OPEN_TEXT_SECTION(0x8000) | |
80 | #else | |
81 | OPEN_TEXT_SECTION(0x7000) | |
82 | #endif | |
83 | ||
84 | USE_FIXED_SECTION(real_vectors) | |
85 | ||
0ebc4cda BH |
86 | /* |
87 | * This is the start of the interrupt handlers for pSeries | |
88 | * This code runs with relocation off. | |
89 | * Code from here to __end_interrupts gets copied down to real | |
90 | * address 0x100 when we are running a relocatable kernel. | |
91 | * Therefore any relative branches in this section must only | |
92 | * branch to labels in this section. | |
93 | */ | |
0ebc4cda BH |
94 | .globl __start_interrupts |
95 | __start_interrupts: | |
96 | ||
e0319829 | 97 | /* No virt vectors corresponding with 0x0..0x100 */ |
1a6822d1 | 98 | EXC_VIRT_NONE(0x4000, 0x100) |
e0319829 | 99 | |
fb479e44 | 100 | |
948cf67c | 101 | #ifdef CONFIG_PPC_P7_NAP |
fb479e44 NP |
102 | /* |
103 | * If running native on arch 2.06 or later, check if we are waking up | |
ba6d334a BH |
104 | * from nap/sleep/winkle, and branch to idle handler. This tests SRR1 |
105 | * bits 46:47. A non-0 value indicates that we are coming from a power | |
106 | * saving state. The idle wakeup handler initially runs in real mode, | |
107 | * but we branch to the 0xc000... address so we can turn on relocation | |
108 | * with mtmsr. | |
948cf67c | 109 | */ |
fb479e44 NP |
110 | #define IDLETEST(n) \ |
111 | BEGIN_FTR_SECTION ; \ | |
112 | mfspr r10,SPRN_SRR1 ; \ | |
113 | rlwinm. r10,r10,47-31,30,31 ; \ | |
114 | beq- 1f ; \ | |
115 | cmpwi cr3,r10,2 ; \ | |
b51351e2 | 116 | BRANCH_TO_C000(r10, system_reset_idle_common) ; \ |
fb479e44 | 117 | 1: \ |
6de6638b | 118 | KVMTEST_PR(n) ; \ |
fb479e44 NP |
119 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
120 | #else | |
121 | #define IDLETEST NOTEST | |
122 | #endif | |
371fefd6 | 123 | |
1a6822d1 | 124 | EXC_REAL_BEGIN(system_reset, 0x100, 0x100) |
fb479e44 | 125 | SET_SCRATCH0(r13) |
c4f3b52c NP |
126 | /* |
127 | * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is | |
128 | * being used, so a nested NMI exception would corrupt it. | |
129 | */ | |
94f3cc8e ME |
130 | EXCEPTION_PROLOG_NORI(PACA_EXNMI, system_reset_common, EXC_STD, |
131 | IDLETEST, 0x100) | |
fb479e44 | 132 | |
1a6822d1 NP |
133 | EXC_REAL_END(system_reset, 0x100, 0x100) |
134 | EXC_VIRT_NONE(0x4100, 0x100) | |
6de6638b | 135 | TRAMP_KVM(PACA_EXNMI, 0x100) |
fb479e44 NP |
136 | |
137 | #ifdef CONFIG_PPC_P7_NAP | |
138 | EXC_COMMON_BEGIN(system_reset_idle_common) | |
9d292501 | 139 | mfspr r12,SPRN_SRR1 |
bf0153c1 | 140 | b pnv_powersave_wakeup |
371fefd6 PM |
141 | #endif |
142 | ||
15b4dd79 NP |
143 | /* |
144 | * Set IRQS_ALL_DISABLED unconditionally so arch_irqs_disabled does | |
145 | * the right thing. We do not want to reconcile because that goes | |
146 | * through irq tracing which we don't want in NMI. | |
147 | * | |
148 | * Save PACAIRQHAPPENED because some code will do a hard disable | |
149 | * (e.g., xmon). So we want to restore this back to where it was | |
150 | * when we return. DAR is unused in the stack, so save it there. | |
151 | */ | |
152 | #define ADD_RECONCILE_NMI \ | |
153 | li r10,IRQS_ALL_DISABLED; \ | |
154 | stb r10,PACAIRQSOFTMASK(r13); \ | |
155 | lbz r10,PACAIRQHAPPENED(r13); \ | |
156 | std r10,_DAR(r1) | |
157 | ||
a3d96f70 | 158 | EXC_COMMON_BEGIN(system_reset_common) |
c4f3b52c NP |
159 | /* |
160 | * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able | |
161 | * to recover, but nested NMI will notice in_nmi and not recover | |
162 | * because of the use of the NMI stack. in_nmi reentrancy is tested in | |
163 | * system_reset_exception. | |
164 | */ | |
165 | lhz r10,PACA_IN_NMI(r13) | |
166 | addi r10,r10,1 | |
167 | sth r10,PACA_IN_NMI(r13) | |
168 | li r10,MSR_RI | |
169 | mtmsrd r10,1 | |
aca79d2b | 170 | |
b1ee8a3d NP |
171 | mr r10,r1 |
172 | ld r1,PACA_NMI_EMERG_SP(r13) | |
173 | subi r1,r1,INT_FRAME_SIZE | |
174 | EXCEPTION_COMMON_NORET_STACK(PACA_EXNMI, 0x100, | |
175 | system_reset, system_reset_exception, | |
15b4dd79 NP |
176 | ADD_NVGPRS;ADD_RECONCILE_NMI) |
177 | ||
178 | /* This (and MCE) can be simplified with mtmsrd L=1 */ | |
179 | /* Clear MSR_RI before setting SRR0 and SRR1. */ | |
180 | li r0,MSR_RI | |
181 | mfmsr r9 | |
182 | andc r9,r9,r0 | |
183 | mtmsrd r9,1 | |
c4f3b52c NP |
184 | |
185 | /* | |
15b4dd79 | 186 | * MSR_RI is clear, now we can decrement paca->in_nmi. |
c4f3b52c NP |
187 | */ |
188 | lhz r10,PACA_IN_NMI(r13) | |
189 | subi r10,r10,1 | |
190 | sth r10,PACA_IN_NMI(r13) | |
191 | ||
15b4dd79 NP |
192 | /* |
193 | * Restore soft mask settings. | |
194 | */ | |
195 | ld r10,_DAR(r1) | |
196 | stb r10,PACAIRQHAPPENED(r13) | |
197 | ld r10,SOFTE(r1) | |
198 | stb r10,PACAIRQSOFTMASK(r13) | |
199 | ||
200 | /* | |
201 | * Keep below code in synch with MACHINE_CHECK_HANDLER_WINDUP. | |
202 | * Should share common bits... | |
203 | */ | |
204 | ||
205 | /* Move original SRR0 and SRR1 into the respective regs */ | |
206 | ld r9,_MSR(r1) | |
207 | mtspr SPRN_SRR1,r9 | |
208 | ld r3,_NIP(r1) | |
209 | mtspr SPRN_SRR0,r3 | |
210 | ld r9,_CTR(r1) | |
211 | mtctr r9 | |
212 | ld r9,_XER(r1) | |
213 | mtxer r9 | |
214 | ld r9,_LINK(r1) | |
215 | mtlr r9 | |
216 | REST_GPR(0, r1) | |
217 | REST_8GPRS(2, r1) | |
218 | REST_GPR(10, r1) | |
219 | ld r11,_CCR(r1) | |
220 | mtcr r11 | |
221 | REST_GPR(11, r1) | |
222 | REST_2GPRS(12, r1) | |
223 | /* restore original r1. */ | |
224 | ld r1,GPR1(r1) | |
225 | RFI_TO_USER_OR_KERNEL | |
582baf44 NP |
226 | |
227 | #ifdef CONFIG_PPC_PSERIES | |
228 | /* | |
229 | * Vectors for the FWNMI option. Share common code. | |
230 | */ | |
231 | TRAMP_REAL_BEGIN(system_reset_fwnmi) | |
232 | SET_SCRATCH0(r13) /* save r13 */ | |
c4f3b52c | 233 | /* See comment at system_reset exception */ |
94f3cc8e ME |
234 | EXCEPTION_PROLOG_NORI(PACA_EXNMI, system_reset_common, EXC_STD, |
235 | NOTEST, 0x100) | |
582baf44 NP |
236 | #endif /* CONFIG_PPC_PSERIES */ |
237 | ||
0ebc4cda | 238 | |
1a6822d1 | 239 | EXC_REAL_BEGIN(machine_check, 0x200, 0x100) |
b01c8b54 PM |
240 | /* This is moved out of line as it can be patched by FW, but |
241 | * some code path might still want to branch into the original | |
242 | * vector | |
243 | */ | |
1707dd16 PM |
244 | SET_SCRATCH0(r13) /* save r13 */ |
245 | EXCEPTION_PROLOG_0(PACA_EXMC) | |
1e9b4507 | 246 | BEGIN_FTR_SECTION |
db7d31ac | 247 | b machine_check_common_early |
1e9b4507 | 248 | FTR_SECTION_ELSE |
1707dd16 | 249 | b machine_check_pSeries_0 |
1e9b4507 | 250 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
1a6822d1 NP |
251 | EXC_REAL_END(machine_check, 0x200, 0x100) |
252 | EXC_VIRT_NONE(0x4200, 0x100) | |
db7d31ac | 253 | TRAMP_REAL_BEGIN(machine_check_common_early) |
afcf0095 NP |
254 | EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200) |
255 | /* | |
256 | * Register contents: | |
257 | * R13 = PACA | |
258 | * R9 = CR | |
259 | * Original R9 to R13 is saved on PACA_EXMC | |
260 | * | |
261 | * Switch to mc_emergency stack and handle re-entrancy (we limit | |
262 | * the nested MCE upto level 4 to avoid stack overflow). | |
263 | * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 | |
264 | * | |
265 | * We use paca->in_mce to check whether this is the first entry or | |
266 | * nested machine check. We increment paca->in_mce to track nested | |
267 | * machine checks. | |
268 | * | |
269 | * If this is the first entry then set stack pointer to | |
270 | * paca->mc_emergency_sp, otherwise r1 is already pointing to | |
271 | * stack frame on mc_emergency stack. | |
272 | * | |
273 | * NOTE: We are here with MSR_ME=0 (off), which means we risk a | |
274 | * checkstop if we get another machine check exception before we do | |
275 | * rfid with MSR_ME=1. | |
1945bc45 NP |
276 | * |
277 | * This interrupt can wake directly from idle. If that is the case, | |
278 | * the machine check is handled then the idle wakeup code is called | |
2bf1071a | 279 | * to restore state. |
afcf0095 NP |
280 | */ |
281 | mr r11,r1 /* Save r1 */ | |
282 | lhz r10,PACA_IN_MCE(r13) | |
283 | cmpwi r10,0 /* Are we in nested machine check */ | |
284 | bne 0f /* Yes, we are. */ | |
285 | /* First machine check entry */ | |
286 | ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ | |
287 | 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
288 | addi r10,r10,1 /* increment paca->in_mce */ | |
289 | sth r10,PACA_IN_MCE(r13) | |
290 | /* Limit nested MCE to level 4 to avoid stack overflow */ | |
ba41e1e1 | 291 | cmpwi r10,MAX_MCE_DEPTH |
afcf0095 NP |
292 | bgt 2f /* Check if we hit limit of 4 */ |
293 | std r11,GPR1(r1) /* Save r1 on the stack. */ | |
294 | std r11,0(r1) /* make stack chain pointer */ | |
295 | mfspr r11,SPRN_SRR0 /* Save SRR0 */ | |
296 | std r11,_NIP(r1) | |
297 | mfspr r11,SPRN_SRR1 /* Save SRR1 */ | |
298 | std r11,_MSR(r1) | |
299 | mfspr r11,SPRN_DAR /* Save DAR */ | |
300 | std r11,_DAR(r1) | |
301 | mfspr r11,SPRN_DSISR /* Save DSISR */ | |
302 | std r11,_DSISR(r1) | |
303 | std r9,_CCR(r1) /* Save CR in stackframe */ | |
304 | /* Save r9 through r13 from EXMC save area to stack frame. */ | |
305 | EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) | |
306 | mfmsr r11 /* get MSR value */ | |
db7d31ac | 307 | BEGIN_FTR_SECTION |
afcf0095 | 308 | ori r11,r11,MSR_ME /* turn on ME bit */ |
db7d31ac | 309 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) |
afcf0095 NP |
310 | ori r11,r11,MSR_RI /* turn on RI bit */ |
311 | LOAD_HANDLER(r12, machine_check_handle_early) | |
312 | 1: mtspr SPRN_SRR0,r12 | |
313 | mtspr SPRN_SRR1,r11 | |
222f20f1 | 314 | RFI_TO_KERNEL |
afcf0095 NP |
315 | b . /* prevent speculative execution */ |
316 | 2: | |
317 | /* Stack overflow. Stay on emergency stack and panic. | |
318 | * Keep the ME bit off while panic-ing, so that if we hit | |
319 | * another machine check we checkstop. | |
320 | */ | |
321 | addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ | |
322 | ld r11,PACAKMSR(r13) | |
323 | LOAD_HANDLER(r12, unrecover_mce) | |
324 | li r10,MSR_ME | |
325 | andc r11,r11,r10 /* Turn off MSR_ME */ | |
326 | b 1b | |
327 | b . /* prevent speculative execution */ | |
afcf0095 NP |
328 | |
329 | TRAMP_REAL_BEGIN(machine_check_pSeries) | |
330 | .globl machine_check_fwnmi | |
331 | machine_check_fwnmi: | |
332 | SET_SCRATCH0(r13) /* save r13 */ | |
333 | EXCEPTION_PROLOG_0(PACA_EXMC) | |
a43c1590 | 334 | BEGIN_FTR_SECTION |
db7d31ac | 335 | b machine_check_common_early |
a43c1590 | 336 | END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE) |
afcf0095 NP |
337 | machine_check_pSeries_0: |
338 | EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200) | |
339 | /* | |
83a980f7 NP |
340 | * MSR_RI is not enabled, because PACA_EXMC is being used, so a |
341 | * nested machine check corrupts it. machine_check_common enables | |
342 | * MSR_RI. | |
afcf0095 | 343 | */ |
94f3cc8e | 344 | EXCEPTION_PROLOG_2_NORI(machine_check_common, EXC_STD) |
afcf0095 NP |
345 | |
346 | TRAMP_KVM_SKIP(PACA_EXMC, 0x200) | |
347 | ||
348 | EXC_COMMON_BEGIN(machine_check_common) | |
349 | /* | |
350 | * Machine check is different because we use a different | |
351 | * save area: PACA_EXMC instead of PACA_EXGEN. | |
352 | */ | |
353 | mfspr r10,SPRN_DAR | |
354 | std r10,PACA_EXMC+EX_DAR(r13) | |
355 | mfspr r10,SPRN_DSISR | |
356 | stw r10,PACA_EXMC+EX_DSISR(r13) | |
357 | EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) | |
358 | FINISH_NAP | |
359 | RECONCILE_IRQ_STATE(r10, r11) | |
360 | ld r3,PACA_EXMC+EX_DAR(r13) | |
361 | lwz r4,PACA_EXMC+EX_DSISR(r13) | |
362 | /* Enable MSR_RI when finished with PACA_EXMC */ | |
363 | li r10,MSR_RI | |
364 | mtmsrd r10,1 | |
365 | std r3,_DAR(r1) | |
366 | std r4,_DSISR(r1) | |
367 | bl save_nvgprs | |
368 | addi r3,r1,STACK_FRAME_OVERHEAD | |
369 | bl machine_check_exception | |
370 | b ret_from_except | |
371 | ||
372 | #define MACHINE_CHECK_HANDLER_WINDUP \ | |
373 | /* Clear MSR_RI before setting SRR0 and SRR1. */\ | |
374 | li r0,MSR_RI; \ | |
375 | mfmsr r9; /* get MSR value */ \ | |
376 | andc r9,r9,r0; \ | |
377 | mtmsrd r9,1; /* Clear MSR_RI */ \ | |
378 | /* Move original SRR0 and SRR1 into the respective regs */ \ | |
379 | ld r9,_MSR(r1); \ | |
380 | mtspr SPRN_SRR1,r9; \ | |
381 | ld r3,_NIP(r1); \ | |
382 | mtspr SPRN_SRR0,r3; \ | |
383 | ld r9,_CTR(r1); \ | |
384 | mtctr r9; \ | |
385 | ld r9,_XER(r1); \ | |
386 | mtxer r9; \ | |
387 | ld r9,_LINK(r1); \ | |
388 | mtlr r9; \ | |
389 | REST_GPR(0, r1); \ | |
390 | REST_8GPRS(2, r1); \ | |
391 | REST_GPR(10, r1); \ | |
392 | ld r11,_CCR(r1); \ | |
393 | mtcr r11; \ | |
394 | /* Decrement paca->in_mce. */ \ | |
395 | lhz r12,PACA_IN_MCE(r13); \ | |
396 | subi r12,r12,1; \ | |
397 | sth r12,PACA_IN_MCE(r13); \ | |
398 | REST_GPR(11, r1); \ | |
399 | REST_2GPRS(12, r1); \ | |
400 | /* restore original r1. */ \ | |
401 | ld r1,GPR1(r1) | |
402 | ||
1945bc45 NP |
403 | #ifdef CONFIG_PPC_P7_NAP |
404 | /* | |
405 | * This is an idle wakeup. Low level machine check has already been | |
406 | * done. Queue the event then call the idle code to do the wake up. | |
407 | */ | |
408 | EXC_COMMON_BEGIN(machine_check_idle_common) | |
409 | bl machine_check_queue_event | |
410 | ||
411 | /* | |
412 | * We have not used any non-volatile GPRs here, and as a rule | |
413 | * most exception code including machine check does not. | |
414 | * Therefore PACA_NAPSTATELOST does not need to be set. Idle | |
415 | * wakeup will restore volatile registers. | |
416 | * | |
417 | * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce. | |
418 | * | |
419 | * Then decrement MCE nesting after finishing with the stack. | |
420 | */ | |
421 | ld r3,_MSR(r1) | |
422 | ||
423 | lhz r11,PACA_IN_MCE(r13) | |
424 | subi r11,r11,1 | |
425 | sth r11,PACA_IN_MCE(r13) | |
426 | ||
427 | /* Turn off the RI bit because SRR1 is used by idle wakeup code. */ | |
428 | /* Recoverability could be improved by reducing the use of SRR1. */ | |
429 | li r11,0 | |
430 | mtmsrd r11,1 | |
431 | ||
432 | b pnv_powersave_wakeup_mce | |
433 | #endif | |
afcf0095 NP |
434 | /* |
435 | * Handle machine check early in real mode. We come here with | |
436 | * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. | |
437 | */ | |
438 | EXC_COMMON_BEGIN(machine_check_handle_early) | |
439 | std r0,GPR0(r1) /* Save r0 */ | |
440 | EXCEPTION_PROLOG_COMMON_3(0x200) | |
441 | bl save_nvgprs | |
442 | addi r3,r1,STACK_FRAME_OVERHEAD | |
443 | bl machine_check_early | |
444 | std r3,RESULT(r1) /* Save result */ | |
445 | ld r12,_MSR(r1) | |
db7d31ac MS |
446 | BEGIN_FTR_SECTION |
447 | b 4f | |
448 | END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE) | |
1945bc45 | 449 | |
afcf0095 NP |
450 | #ifdef CONFIG_PPC_P7_NAP |
451 | /* | |
452 | * Check if thread was in power saving mode. We come here when any | |
453 | * of the following is true: | |
454 | * a. thread wasn't in power saving mode | |
455 | * b. thread was in power saving mode with no state loss, | |
456 | * supervisor state loss or hypervisor state loss. | |
457 | * | |
458 | * Go back to nap/sleep/winkle mode again if (b) is true. | |
459 | */ | |
1945bc45 NP |
460 | BEGIN_FTR_SECTION |
461 | rlwinm. r11,r12,47-31,30,31 | |
6102c005 | 462 | bne machine_check_idle_common |
1945bc45 | 463 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
afcf0095 | 464 | #endif |
1945bc45 | 465 | |
afcf0095 NP |
466 | /* |
467 | * Check if we are coming from hypervisor userspace. If yes then we | |
468 | * continue in host kernel in V mode to deliver the MC event. | |
469 | */ | |
470 | rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ | |
471 | beq 5f | |
db7d31ac | 472 | 4: andi. r11,r12,MSR_PR /* See if coming from user. */ |
afcf0095 NP |
473 | bne 9f /* continue in V mode if we are. */ |
474 | ||
475 | 5: | |
476 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER | |
db7d31ac | 477 | BEGIN_FTR_SECTION |
afcf0095 NP |
478 | /* |
479 | * We are coming from kernel context. Check if we are coming from | |
480 | * guest. if yes, then we can continue. We will fall through | |
481 | * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. | |
482 | */ | |
483 | lbz r11,HSTATE_IN_GUEST(r13) | |
484 | cmpwi r11,0 /* Check if coming from guest */ | |
485 | bne 9f /* continue if we are. */ | |
db7d31ac | 486 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) |
afcf0095 NP |
487 | #endif |
488 | /* | |
489 | * At this point we are not sure about what context we come from. | |
490 | * Queue up the MCE event and return from the interrupt. | |
491 | * But before that, check if this is an un-recoverable exception. | |
492 | * If yes, then stay on emergency stack and panic. | |
493 | */ | |
494 | andi. r11,r12,MSR_RI | |
495 | bne 2f | |
496 | 1: mfspr r11,SPRN_SRR0 | |
497 | LOAD_HANDLER(r10,unrecover_mce) | |
498 | mtspr SPRN_SRR0,r10 | |
499 | ld r10,PACAKMSR(r13) | |
500 | /* | |
501 | * We are going down. But there are chances that we might get hit by | |
502 | * another MCE during panic path and we may run into unstable state | |
503 | * with no way out. Hence, turn ME bit off while going down, so that | |
504 | * when another MCE is hit during panic path, system will checkstop | |
505 | * and hypervisor will get restarted cleanly by SP. | |
506 | */ | |
507 | li r3,MSR_ME | |
508 | andc r10,r10,r3 /* Turn off MSR_ME */ | |
509 | mtspr SPRN_SRR1,r10 | |
222f20f1 | 510 | RFI_TO_KERNEL |
afcf0095 NP |
511 | b . |
512 | 2: | |
513 | /* | |
514 | * Check if we have successfully handled/recovered from error, if not | |
515 | * then stay on emergency stack and panic. | |
516 | */ | |
517 | ld r3,RESULT(r1) /* Load result */ | |
518 | cmpdi r3,0 /* see if we handled MCE successfully */ | |
519 | ||
520 | beq 1b /* if !handled then panic */ | |
db7d31ac | 521 | BEGIN_FTR_SECTION |
afcf0095 NP |
522 | /* |
523 | * Return from MC interrupt. | |
524 | * Queue up the MCE event so that we can log it later, while | |
525 | * returning from kernel or opal call. | |
526 | */ | |
527 | bl machine_check_queue_event | |
528 | MACHINE_CHECK_HANDLER_WINDUP | |
222f20f1 | 529 | RFI_TO_USER_OR_KERNEL |
db7d31ac MS |
530 | FTR_SECTION_ELSE |
531 | /* | |
532 | * pSeries: Return from MC interrupt. Before that stay on emergency | |
533 | * stack and call machine_check_exception to log the MCE event. | |
534 | */ | |
535 | LOAD_HANDLER(r10,mce_return) | |
536 | mtspr SPRN_SRR0,r10 | |
537 | ld r10,PACAKMSR(r13) | |
538 | mtspr SPRN_SRR1,r10 | |
539 | RFI_TO_KERNEL | |
540 | b . | |
541 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) | |
afcf0095 NP |
542 | 9: |
543 | /* Deliver the machine check to host kernel in V mode. */ | |
544 | MACHINE_CHECK_HANDLER_WINDUP | |
db7d31ac MS |
545 | SET_SCRATCH0(r13) /* save r13 */ |
546 | EXCEPTION_PROLOG_0(PACA_EXMC) | |
547 | b machine_check_pSeries_0 | |
afcf0095 NP |
548 | |
549 | EXC_COMMON_BEGIN(unrecover_mce) | |
550 | /* Invoke machine_check_exception to print MCE event and panic. */ | |
551 | addi r3,r1,STACK_FRAME_OVERHEAD | |
552 | bl machine_check_exception | |
553 | /* | |
554 | * We will not reach here. Even if we did, there is no way out. Call | |
555 | * unrecoverable_exception and die. | |
556 | */ | |
557 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
558 | bl unrecoverable_exception | |
559 | b 1b | |
560 | ||
a43c1590 MS |
561 | EXC_COMMON_BEGIN(mce_return) |
562 | /* Invoke machine_check_exception to print MCE event and return. */ | |
563 | addi r3,r1,STACK_FRAME_OVERHEAD | |
564 | bl machine_check_exception | |
db7d31ac | 565 | MACHINE_CHECK_HANDLER_WINDUP |
a43c1590 MS |
566 | RFI_TO_KERNEL |
567 | b . | |
0ebc4cda | 568 | |
1a6822d1 NP |
569 | EXC_REAL(data_access, 0x300, 0x80) |
570 | EXC_VIRT(data_access, 0x4300, 0x80, 0x300) | |
80795e6c NP |
571 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x300) |
572 | ||
573 | EXC_COMMON_BEGIN(data_access_common) | |
574 | /* | |
575 | * Here r13 points to the paca, r9 contains the saved CR, | |
576 | * SRR0 and SRR1 are saved in r11 and r12, | |
577 | * r9 - r13 are saved in paca->exgen. | |
578 | */ | |
579 | mfspr r10,SPRN_DAR | |
580 | std r10,PACA_EXGEN+EX_DAR(r13) | |
581 | mfspr r10,SPRN_DSISR | |
582 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
583 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) | |
584 | RECONCILE_IRQ_STATE(r10, r11) | |
585 | ld r12,_MSR(r1) | |
586 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
587 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
588 | li r5,0x300 | |
589 | std r3,_DAR(r1) | |
590 | std r4,_DSISR(r1) | |
591 | BEGIN_MMU_FTR_SECTION | |
592 | b do_hash_page /* Try to handle as hpte fault */ | |
593 | MMU_FTR_SECTION_ELSE | |
594 | b handle_page_fault | |
595 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
596 | ||
0ebc4cda | 597 | |
1a6822d1 | 598 | EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80) |
48e7b769 | 599 | EXCEPTION_PROLOG(PACA_EXSLB, data_access_slb_common, EXC_STD, KVMTEST_PR, 0x380); |
1a6822d1 | 600 | EXC_REAL_END(data_access_slb, 0x380, 0x80) |
0ebc4cda | 601 | |
1a6822d1 | 602 | EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80) |
48e7b769 | 603 | EXCEPTION_RELON_PROLOG(PACA_EXSLB, data_access_slb_common, EXC_STD, NOTEST, 0x380); |
1a6822d1 | 604 | EXC_VIRT_END(data_access_slb, 0x4380, 0x80) |
48e7b769 | 605 | |
2b9af6e4 NP |
606 | TRAMP_KVM_SKIP(PACA_EXSLB, 0x380) |
607 | ||
48e7b769 NP |
608 | EXC_COMMON_BEGIN(data_access_slb_common) |
609 | mfspr r10,SPRN_DAR | |
610 | std r10,PACA_EXSLB+EX_DAR(r13) | |
611 | EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB) | |
612 | ld r4,PACA_EXSLB+EX_DAR(r13) | |
613 | std r4,_DAR(r1) | |
614 | addi r3,r1,STACK_FRAME_OVERHEAD | |
615 | bl do_slb_fault | |
616 | cmpdi r3,0 | |
617 | bne- 1f | |
618 | b fast_exception_return | |
619 | 1: /* Error case */ | |
620 | std r3,RESULT(r1) | |
621 | bl save_nvgprs | |
622 | RECONCILE_IRQ_STATE(r10, r11) | |
623 | ld r4,_DAR(r1) | |
624 | ld r5,RESULT(r1) | |
625 | addi r3,r1,STACK_FRAME_OVERHEAD | |
626 | bl do_bad_slb_fault | |
627 | b ret_from_except | |
628 | ||
2b9af6e4 | 629 | |
1a6822d1 NP |
630 | EXC_REAL(instruction_access, 0x400, 0x80) |
631 | EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400) | |
27ce77df NP |
632 | TRAMP_KVM(PACA_EXGEN, 0x400) |
633 | ||
634 | EXC_COMMON_BEGIN(instruction_access_common) | |
635 | EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) | |
636 | RECONCILE_IRQ_STATE(r10, r11) | |
637 | ld r12,_MSR(r1) | |
638 | ld r3,_NIP(r1) | |
475b581f | 639 | andis. r4,r12,DSISR_SRR1_MATCH_64S@h |
27ce77df NP |
640 | li r5,0x400 |
641 | std r3,_DAR(r1) | |
642 | std r4,_DSISR(r1) | |
643 | BEGIN_MMU_FTR_SECTION | |
644 | b do_hash_page /* Try to handle as hpte fault */ | |
645 | MMU_FTR_SECTION_ELSE | |
646 | b handle_page_fault | |
647 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
648 | ||
0ebc4cda | 649 | |
1a6822d1 | 650 | EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80) |
48e7b769 | 651 | EXCEPTION_PROLOG(PACA_EXSLB, instruction_access_slb_common, EXC_STD, KVMTEST_PR, 0x480); |
1a6822d1 | 652 | EXC_REAL_END(instruction_access_slb, 0x480, 0x80) |
0ebc4cda | 653 | |
1a6822d1 | 654 | EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80) |
48e7b769 | 655 | EXCEPTION_RELON_PROLOG(PACA_EXSLB, instruction_access_slb_common, EXC_STD, NOTEST, 0x480); |
1a6822d1 | 656 | EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80) |
54be0b9c | 657 | |
48e7b769 | 658 | TRAMP_KVM(PACA_EXSLB, 0x480) |
54be0b9c | 659 | |
48e7b769 NP |
660 | EXC_COMMON_BEGIN(instruction_access_slb_common) |
661 | EXCEPTION_PROLOG_COMMON(0x480, PACA_EXSLB) | |
662 | ld r4,_NIP(r1) | |
663 | addi r3,r1,STACK_FRAME_OVERHEAD | |
664 | bl do_slb_fault | |
665 | cmpdi r3,0 | |
666 | bne- 1f | |
667 | b fast_exception_return | |
668 | 1: /* Error case */ | |
669 | std r3,RESULT(r1) | |
8d04631a | 670 | bl save_nvgprs |
8d04631a | 671 | RECONCILE_IRQ_STATE(r10, r11) |
48e7b769 NP |
672 | ld r4,_NIP(r1) |
673 | ld r5,RESULT(r1) | |
674 | addi r3,r1,STACK_FRAME_OVERHEAD | |
675 | bl do_bad_slb_fault | |
8d04631a NP |
676 | b ret_from_except |
677 | ||
48e7b769 | 678 | |
1a6822d1 | 679 | EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100) |
b3e6b5df | 680 | .globl hardware_interrupt_hv; |
b3e6b5df | 681 | hardware_interrupt_hv: |
a5d4f3ad | 682 | BEGIN_FTR_SECTION |
0b924de4 | 683 | MASKABLE_EXCEPTION_HV(0x500, hardware_interrupt_common, IRQS_DISABLED) |
de56a948 | 684 | FTR_SECTION_ELSE |
0b924de4 | 685 | MASKABLE_EXCEPTION(0x500, hardware_interrupt_common, IRQS_DISABLED) |
969391c5 | 686 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
1a6822d1 | 687 | EXC_REAL_END(hardware_interrupt, 0x500, 0x100) |
da2bc464 | 688 | |
1a6822d1 | 689 | EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100) |
c138e588 NP |
690 | .globl hardware_interrupt_relon_hv; |
691 | hardware_interrupt_relon_hv: | |
692 | BEGIN_FTR_SECTION | |
0b924de4 ME |
693 | MASKABLE_RELON_EXCEPTION_HV(0x500, hardware_interrupt_common, |
694 | IRQS_DISABLED) | |
c138e588 | 695 | FTR_SECTION_ELSE |
0a55c241 | 696 | __MASKABLE_RELON_EXCEPTION(0x500, hardware_interrupt_common, |
0b924de4 | 697 | EXC_STD, SOFTEN_TEST_PR, IRQS_DISABLED) |
c138e588 | 698 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
1a6822d1 | 699 | EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100) |
c138e588 | 700 | |
7ede5317 NP |
701 | TRAMP_KVM(PACA_EXGEN, 0x500) |
702 | TRAMP_KVM_HV(PACA_EXGEN, 0x500) | |
c138e588 NP |
703 | EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) |
704 | ||
705 | ||
1a6822d1 NP |
706 | EXC_REAL(alignment, 0x600, 0x100) |
707 | EXC_VIRT(alignment, 0x4600, 0x100, 0x600) | |
da2bc464 | 708 | TRAMP_KVM(PACA_EXGEN, 0x600) |
f9aa6714 NP |
709 | EXC_COMMON_BEGIN(alignment_common) |
710 | mfspr r10,SPRN_DAR | |
711 | std r10,PACA_EXGEN+EX_DAR(r13) | |
712 | mfspr r10,SPRN_DSISR | |
713 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
714 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) | |
715 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
716 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
717 | std r3,_DAR(r1) | |
718 | std r4,_DSISR(r1) | |
719 | bl save_nvgprs | |
720 | RECONCILE_IRQ_STATE(r10, r11) | |
721 | addi r3,r1,STACK_FRAME_OVERHEAD | |
722 | bl alignment_exception | |
723 | b ret_from_except | |
724 | ||
da2bc464 | 725 | |
1a6822d1 NP |
726 | EXC_REAL(program_check, 0x700, 0x100) |
727 | EXC_VIRT(program_check, 0x4700, 0x100, 0x700) | |
da2bc464 | 728 | TRAMP_KVM(PACA_EXGEN, 0x700) |
11e87346 | 729 | EXC_COMMON_BEGIN(program_check_common) |
265e60a1 CB |
730 | /* |
731 | * It's possible to receive a TM Bad Thing type program check with | |
732 | * userspace register values (in particular r1), but with SRR1 reporting | |
733 | * that we came from the kernel. Normally that would confuse the bad | |
734 | * stack logic, and we would report a bad kernel stack pointer. Instead | |
735 | * we switch to the emergency stack if we're taking a TM Bad Thing from | |
736 | * the kernel. | |
737 | */ | |
738 | li r10,MSR_PR /* Build a mask of MSR_PR .. */ | |
739 | oris r10,r10,0x200000@h /* .. and SRR1_PROGTM */ | |
740 | and r10,r10,r12 /* Mask SRR1 with that. */ | |
741 | srdi r10,r10,8 /* Shift it so we can compare */ | |
742 | cmpldi r10,(0x200000 >> 8) /* .. with an immediate. */ | |
743 | bne 1f /* If != go to normal path. */ | |
744 | ||
745 | /* SRR1 had PR=0 and SRR1_PROGTM=1, so use the emergency stack */ | |
746 | andi. r10,r12,MSR_PR; /* Set CR0 correctly for label */ | |
747 | /* 3 in EXCEPTION_PROLOG_COMMON */ | |
748 | mr r10,r1 /* Save r1 */ | |
749 | ld r1,PACAEMERGSP(r13) /* Use emergency stack */ | |
750 | subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
751 | b 3f /* Jump into the macro !! */ | |
752 | 1: EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) | |
11e87346 NP |
753 | bl save_nvgprs |
754 | RECONCILE_IRQ_STATE(r10, r11) | |
755 | addi r3,r1,STACK_FRAME_OVERHEAD | |
756 | bl program_check_exception | |
757 | b ret_from_except | |
758 | ||
b01c8b54 | 759 | |
1a6822d1 NP |
760 | EXC_REAL(fp_unavailable, 0x800, 0x100) |
761 | EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800) | |
da2bc464 | 762 | TRAMP_KVM(PACA_EXGEN, 0x800) |
c78d9b97 NP |
763 | EXC_COMMON_BEGIN(fp_unavailable_common) |
764 | EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) | |
765 | bne 1f /* if from user, just load it up */ | |
766 | bl save_nvgprs | |
767 | RECONCILE_IRQ_STATE(r10, r11) | |
768 | addi r3,r1,STACK_FRAME_OVERHEAD | |
769 | bl kernel_fp_unavailable_exception | |
770 | BUG_OPCODE | |
771 | 1: | |
772 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
773 | BEGIN_FTR_SECTION | |
774 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
775 | * transaction), go do TM stuff | |
776 | */ | |
777 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
778 | bne- 2f | |
779 | END_FTR_SECTION_IFSET(CPU_FTR_TM) | |
780 | #endif | |
781 | bl load_up_fpu | |
782 | b fast_exception_return | |
783 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
784 | 2: /* User process was in a transaction */ | |
785 | bl save_nvgprs | |
786 | RECONCILE_IRQ_STATE(r10, r11) | |
787 | addi r3,r1,STACK_FRAME_OVERHEAD | |
788 | bl fp_unavailable_tm | |
789 | b ret_from_except | |
790 | #endif | |
791 | ||
a5d4f3ad | 792 | |
a048a07d | 793 | EXC_REAL_OOL_MASKABLE(decrementer, 0x900, 0x80, IRQS_DISABLED) |
f14e953b | 794 | EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900, IRQS_DISABLED) |
39c0da57 NP |
795 | TRAMP_KVM(PACA_EXGEN, 0x900) |
796 | EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) | |
797 | ||
a485c709 | 798 | |
1a6822d1 NP |
799 | EXC_REAL_HV(hdecrementer, 0x980, 0x80) |
800 | EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980) | |
facc6d74 NP |
801 | TRAMP_KVM_HV(PACA_EXGEN, 0x980) |
802 | EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) | |
803 | ||
a5d4f3ad | 804 | |
f14e953b MS |
805 | EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100, IRQS_DISABLED) |
806 | EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00, IRQS_DISABLED) | |
da2bc464 | 807 | TRAMP_KVM(PACA_EXGEN, 0xa00) |
ca243163 NP |
808 | #ifdef CONFIG_PPC_DOORBELL |
809 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) | |
810 | #else | |
811 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) | |
812 | #endif | |
813 | ||
0ebc4cda | 814 | |
1a6822d1 NP |
815 | EXC_REAL(trap_0b, 0xb00, 0x100) |
816 | EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00) | |
da2bc464 | 817 | TRAMP_KVM(PACA_EXGEN, 0xb00) |
341215dc NP |
818 | EXC_COMMON(trap_0b_common, 0xb00, unknown_exception) |
819 | ||
acd7d8ce NP |
820 | /* |
821 | * system call / hypercall (0xc00, 0x4c00) | |
822 | * | |
823 | * The system call exception is invoked with "sc 0" and does not alter HV bit. | |
824 | * There is support for kernel code to invoke system calls but there are no | |
825 | * in-tree users. | |
826 | * | |
827 | * The hypercall is invoked with "sc 1" and sets HV=1. | |
828 | * | |
829 | * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to | |
830 | * 0x4c00 virtual mode. | |
831 | * | |
832 | * Call convention: | |
833 | * | |
834 | * syscall register convention is in Documentation/powerpc/syscall64-abi.txt | |
835 | * | |
836 | * For hypercalls, the register convention is as follows: | |
837 | * r0 volatile | |
838 | * r1-2 nonvolatile | |
839 | * r3 volatile parameter and return value for status | |
840 | * r4-r10 volatile input and output value | |
841 | * r11 volatile hypercall number and output value | |
76fc0cfc | 842 | * r12 volatile input and output value |
acd7d8ce NP |
843 | * r13-r31 nonvolatile |
844 | * LR nonvolatile | |
845 | * CTR volatile | |
846 | * XER volatile | |
847 | * CR0-1 CR5-7 volatile | |
848 | * CR2-4 nonvolatile | |
849 | * Other registers nonvolatile | |
850 | * | |
851 | * The intersection of volatile registers that don't contain possible | |
76fc0cfc NP |
852 | * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry |
853 | * without saving, though xer is not a good idea to use, as hardware may | |
854 | * interpret some bits so it may be costly to change them. | |
acd7d8ce | 855 | */ |
bc355125 | 856 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
acd7d8ce NP |
857 | /* |
858 | * There is a little bit of juggling to get syscall and hcall | |
76fc0cfc NP |
859 | * working well. Save r13 in ctr to avoid using SPRG scratch |
860 | * register. | |
acd7d8ce NP |
861 | * |
862 | * Userspace syscalls have already saved the PPR, hcalls must save | |
863 | * it before setting HMT_MEDIUM. | |
864 | */ | |
bc355125 | 865 | #define SYSCALL_KVMTEST \ |
76fc0cfc | 866 | mtctr r13; \ |
bc355125 | 867 | GET_PACA(r13); \ |
76fc0cfc | 868 | std r10,PACA_EXGEN+EX_R10(r13); \ |
a048a07d | 869 | INTERRUPT_TO_KERNEL; \ |
acd7d8ce | 870 | KVMTEST_PR(0xc00); /* uses r10, branch to do_kvm_0xc00_system_call */ \ |
bc355125 | 871 | HMT_MEDIUM; \ |
76fc0cfc | 872 | mfctr r9; |
bc355125 PM |
873 | |
874 | #else | |
875 | #define SYSCALL_KVMTEST \ | |
acd7d8ce NP |
876 | HMT_MEDIUM; \ |
877 | mr r9,r13; \ | |
a048a07d NP |
878 | GET_PACA(r13); \ |
879 | INTERRUPT_TO_KERNEL; | |
bc355125 PM |
880 | #endif |
881 | ||
fb479e44 NP |
882 | #define LOAD_SYSCALL_HANDLER(reg) \ |
883 | __LOAD_HANDLER(reg, system_call_common) | |
d807ad37 | 884 | |
acd7d8ce NP |
885 | /* |
886 | * After SYSCALL_KVMTEST, we reach here with PACA in r13, r13 in r9, | |
887 | * and HMT_MEDIUM. | |
888 | */ | |
889 | #define SYSCALL_REAL \ | |
890 | mfspr r11,SPRN_SRR0 ; \ | |
d807ad37 NP |
891 | mfspr r12,SPRN_SRR1 ; \ |
892 | LOAD_SYSCALL_HANDLER(r10) ; \ | |
893 | mtspr SPRN_SRR0,r10 ; \ | |
894 | ld r10,PACAKMSR(r13) ; \ | |
895 | mtspr SPRN_SRR1,r10 ; \ | |
222f20f1 | 896 | RFI_TO_KERNEL ; \ |
d807ad37 NP |
897 | b . ; /* prevent speculative execution */ |
898 | ||
727f1361 | 899 | #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH |
5c2511bf ME |
900 | #define SYSCALL_FASTENDIAN_TEST \ |
901 | BEGIN_FTR_SECTION \ | |
902 | cmpdi r0,0x1ebe ; \ | |
903 | beq- 1f ; \ | |
904 | END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ | |
905 | ||
acd7d8ce | 906 | #define SYSCALL_FASTENDIAN \ |
d807ad37 NP |
907 | /* Fast LE/BE switch system call */ \ |
908 | 1: mfspr r12,SPRN_SRR1 ; \ | |
909 | xori r12,r12,MSR_LE ; \ | |
910 | mtspr SPRN_SRR1,r12 ; \ | |
acd7d8ce | 911 | mr r13,r9 ; \ |
222f20f1 | 912 | RFI_TO_USER ; /* return to userspace */ \ |
d807ad37 | 913 | b . ; /* prevent speculative execution */ |
727f1361 ME |
914 | #else |
915 | #define SYSCALL_FASTENDIAN_TEST | |
916 | #define SYSCALL_FASTENDIAN | |
917 | #endif /* CONFIG_PPC_FAST_ENDIAN_SWITCH */ | |
d807ad37 NP |
918 | |
919 | #if defined(CONFIG_RELOCATABLE) | |
920 | /* | |
921 | * We can't branch directly so we do it via the CTR which | |
922 | * is volatile across system calls. | |
923 | */ | |
acd7d8ce NP |
924 | #define SYSCALL_VIRT \ |
925 | LOAD_SYSCALL_HANDLER(r10) ; \ | |
926 | mtctr r10 ; \ | |
927 | mfspr r11,SPRN_SRR0 ; \ | |
d807ad37 NP |
928 | mfspr r12,SPRN_SRR1 ; \ |
929 | li r10,MSR_RI ; \ | |
930 | mtmsrd r10,1 ; \ | |
931 | bctr ; | |
932 | #else | |
933 | /* We can branch directly */ | |
acd7d8ce NP |
934 | #define SYSCALL_VIRT \ |
935 | mfspr r11,SPRN_SRR0 ; \ | |
d807ad37 NP |
936 | mfspr r12,SPRN_SRR1 ; \ |
937 | li r10,MSR_RI ; \ | |
938 | mtmsrd r10,1 ; /* Set RI (EE=0) */ \ | |
939 | b system_call_common ; | |
940 | #endif | |
941 | ||
1a6822d1 | 942 | EXC_REAL_BEGIN(system_call, 0xc00, 0x100) |
acd7d8ce NP |
943 | SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */ |
944 | SYSCALL_FASTENDIAN_TEST | |
945 | SYSCALL_REAL | |
946 | SYSCALL_FASTENDIAN | |
1a6822d1 | 947 | EXC_REAL_END(system_call, 0xc00, 0x100) |
da2bc464 | 948 | |
1a6822d1 | 949 | EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100) |
acd7d8ce NP |
950 | SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */ |
951 | SYSCALL_FASTENDIAN_TEST | |
952 | SYSCALL_VIRT | |
953 | SYSCALL_FASTENDIAN | |
1a6822d1 | 954 | EXC_VIRT_END(system_call, 0x4c00, 0x100) |
d807ad37 | 955 | |
acd7d8ce NP |
956 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
957 | /* | |
958 | * This is a hcall, so register convention is as above, with these | |
959 | * differences: | |
960 | * r13 = PACA | |
76fc0cfc NP |
961 | * ctr = orig r13 |
962 | * orig r10 saved in PACA | |
acd7d8ce NP |
963 | */ |
964 | TRAMP_KVM_BEGIN(do_kvm_0xc00) | |
965 | /* | |
966 | * Save the PPR (on systems that support it) before changing to | |
967 | * HMT_MEDIUM. That allows the KVM code to save that value into the | |
968 | * guest state (it is the guest's PPR value). | |
969 | */ | |
76fc0cfc | 970 | OPT_GET_SPR(r10, SPRN_PPR, CPU_FTR_HAS_PPR) |
acd7d8ce | 971 | HMT_MEDIUM |
76fc0cfc | 972 | OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r10, CPU_FTR_HAS_PPR) |
acd7d8ce | 973 | mfctr r10 |
76fc0cfc | 974 | SET_SCRATCH0(r10) |
acd7d8ce NP |
975 | std r9,PACA_EXGEN+EX_R9(r13) |
976 | mfcr r9 | |
acd7d8ce NP |
977 | KVM_HANDLER(PACA_EXGEN, EXC_STD, 0xc00) |
978 | #endif | |
da2bc464 | 979 | |
d807ad37 | 980 | |
1a6822d1 NP |
981 | EXC_REAL(single_step, 0xd00, 0x100) |
982 | EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00) | |
da2bc464 | 983 | TRAMP_KVM(PACA_EXGEN, 0xd00) |
bc6675c6 | 984 | EXC_COMMON(single_step_common, 0xd00, single_step_exception) |
b01c8b54 | 985 | |
1a6822d1 | 986 | EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20) |
da0e7e62 | 987 | EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00) |
f5c32c1d NP |
988 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) |
989 | EXC_COMMON_BEGIN(h_data_storage_common) | |
990 | mfspr r10,SPRN_HDAR | |
991 | std r10,PACA_EXGEN+EX_DAR(r13) | |
992 | mfspr r10,SPRN_HDSISR | |
993 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
994 | EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) | |
995 | bl save_nvgprs | |
996 | RECONCILE_IRQ_STATE(r10, r11) | |
997 | addi r3,r1,STACK_FRAME_OVERHEAD | |
d7b45615 SJS |
998 | BEGIN_MMU_FTR_SECTION |
999 | ld r4,PACA_EXGEN+EX_DAR(r13) | |
1000 | lwz r5,PACA_EXGEN+EX_DSISR(r13) | |
1001 | std r4,_DAR(r1) | |
1002 | std r5,_DSISR(r1) | |
1003 | li r5,SIGSEGV | |
1004 | bl bad_page_fault | |
1005 | MMU_FTR_SECTION_ELSE | |
f5c32c1d | 1006 | bl unknown_exception |
d7b45615 | 1007 | ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX) |
f5c32c1d | 1008 | b ret_from_except |
f5c32c1d | 1009 | |
1707dd16 | 1010 | |
1a6822d1 | 1011 | EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20) |
da0e7e62 | 1012 | EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20) |
82517cab NP |
1013 | TRAMP_KVM_HV(PACA_EXGEN, 0xe20) |
1014 | EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) | |
1015 | ||
1707dd16 | 1016 | |
1a6822d1 NP |
1017 | EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20) |
1018 | EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40) | |
031b4026 NP |
1019 | TRAMP_KVM_HV(PACA_EXGEN, 0xe40) |
1020 | EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) | |
1021 | ||
1707dd16 | 1022 | |
e0319829 NP |
1023 | /* |
1024 | * hmi_exception trampoline is a special case. It jumps to hmi_exception_early | |
1025 | * first, and then eventaully from there to the trampoline to get into virtual | |
1026 | * mode. | |
1027 | */ | |
1a6822d1 | 1028 | __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early) |
f14e953b | 1029 | __TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60, IRQS_DISABLED) |
1a6822d1 | 1030 | EXC_VIRT_NONE(0x4e60, 0x20) |
62f9b03b NP |
1031 | TRAMP_KVM_HV(PACA_EXGEN, 0xe60) |
1032 | TRAMP_REAL_BEGIN(hmi_exception_early) | |
1033 | EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60) | |
a4087a4d NP |
1034 | mr r10,r1 /* Save r1 */ |
1035 | ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */ | |
62f9b03b | 1036 | subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ |
62f9b03b | 1037 | mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ |
a4087a4d NP |
1038 | mfspr r12,SPRN_HSRR1 /* Save HSRR1 */ |
1039 | EXCEPTION_PROLOG_COMMON_1() | |
62f9b03b NP |
1040 | EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) |
1041 | EXCEPTION_PROLOG_COMMON_3(0xe60) | |
1042 | addi r3,r1,STACK_FRAME_OVERHEAD | |
505a314f | 1043 | BRANCH_LINK_TO_FAR(DOTSYM(hmi_exception_realmode)) /* Function call ABI */ |
5080332c MN |
1044 | cmpdi cr0,r3,0 |
1045 | ||
62f9b03b NP |
1046 | /* Windup the stack. */ |
1047 | /* Move original HSRR0 and HSRR1 into the respective regs */ | |
1048 | ld r9,_MSR(r1) | |
1049 | mtspr SPRN_HSRR1,r9 | |
1050 | ld r3,_NIP(r1) | |
1051 | mtspr SPRN_HSRR0,r3 | |
1052 | ld r9,_CTR(r1) | |
1053 | mtctr r9 | |
1054 | ld r9,_XER(r1) | |
1055 | mtxer r9 | |
1056 | ld r9,_LINK(r1) | |
1057 | mtlr r9 | |
1058 | REST_GPR(0, r1) | |
1059 | REST_8GPRS(2, r1) | |
1060 | REST_GPR(10, r1) | |
1061 | ld r11,_CCR(r1) | |
5080332c MN |
1062 | REST_2GPRS(12, r1) |
1063 | bne 1f | |
62f9b03b NP |
1064 | mtcr r11 |
1065 | REST_GPR(11, r1) | |
5080332c | 1066 | ld r1,GPR1(r1) |
222f20f1 | 1067 | HRFI_TO_USER_OR_KERNEL |
5080332c MN |
1068 | |
1069 | 1: mtcr r11 | |
1070 | REST_GPR(11, r1) | |
62f9b03b NP |
1071 | ld r1,GPR1(r1) |
1072 | ||
1073 | /* | |
1074 | * Go to virtual mode and pull the HMI event information from | |
1075 | * firmware. | |
1076 | */ | |
1077 | .globl hmi_exception_after_realmode | |
1078 | hmi_exception_after_realmode: | |
1079 | SET_SCRATCH0(r13) | |
1080 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
1081 | b tramp_real_hmi_exception | |
1082 | ||
5080332c MN |
1083 | EXC_COMMON_BEGIN(hmi_exception_common) |
1084 | EXCEPTION_COMMON(PACA_EXGEN, 0xe60, hmi_exception_common, handle_hmi_exception, | |
1085 | ret_from_except, FINISH_NAP;ADD_NVGPRS;ADD_RECONCILE;RUNLATCH_ON) | |
1707dd16 | 1086 | |
f14e953b MS |
1087 | EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20, IRQS_DISABLED) |
1088 | EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80, IRQS_DISABLED) | |
9bcb81bf NP |
1089 | TRAMP_KVM_HV(PACA_EXGEN, 0xe80) |
1090 | #ifdef CONFIG_PPC_DOORBELL | |
1091 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) | |
1092 | #else | |
1093 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) | |
1094 | #endif | |
1095 | ||
0ebc4cda | 1096 | |
f14e953b MS |
1097 | EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20, IRQS_DISABLED) |
1098 | EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0, IRQS_DISABLED) | |
74408776 NP |
1099 | TRAMP_KVM_HV(PACA_EXGEN, 0xea0) |
1100 | EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) | |
1101 | ||
9baaef0a | 1102 | |
1a6822d1 NP |
1103 | EXC_REAL_NONE(0xec0, 0x20) |
1104 | EXC_VIRT_NONE(0x4ec0, 0x20) | |
1105 | EXC_REAL_NONE(0xee0, 0x20) | |
1106 | EXC_VIRT_NONE(0x4ee0, 0x20) | |
bda7fea2 | 1107 | |
0ebc4cda | 1108 | |
f442d004 MS |
1109 | EXC_REAL_OOL_MASKABLE(performance_monitor, 0xf00, 0x20, IRQS_PMI_DISABLED) |
1110 | EXC_VIRT_OOL_MASKABLE(performance_monitor, 0x4f00, 0x20, 0xf00, IRQS_PMI_DISABLED) | |
b1c7f150 NP |
1111 | TRAMP_KVM(PACA_EXGEN, 0xf00) |
1112 | EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) | |
1113 | ||
0ebc4cda | 1114 | |
1a6822d1 NP |
1115 | EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20) |
1116 | EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20) | |
d1a0ca9c NP |
1117 | TRAMP_KVM(PACA_EXGEN, 0xf20) |
1118 | EXC_COMMON_BEGIN(altivec_unavailable_common) | |
1119 | EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) | |
1120 | #ifdef CONFIG_ALTIVEC | |
1121 | BEGIN_FTR_SECTION | |
1122 | beq 1f | |
1123 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1124 | BEGIN_FTR_SECTION_NESTED(69) | |
1125 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1126 | * transaction), go do TM stuff | |
1127 | */ | |
1128 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1129 | bne- 2f | |
1130 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1131 | #endif | |
1132 | bl load_up_altivec | |
1133 | b fast_exception_return | |
1134 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1135 | 2: /* User process was in a transaction */ | |
1136 | bl save_nvgprs | |
1137 | RECONCILE_IRQ_STATE(r10, r11) | |
1138 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1139 | bl altivec_unavailable_tm | |
1140 | b ret_from_except | |
1141 | #endif | |
1142 | 1: | |
1143 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1144 | #endif | |
1145 | bl save_nvgprs | |
1146 | RECONCILE_IRQ_STATE(r10, r11) | |
1147 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1148 | bl altivec_unavailable_exception | |
1149 | b ret_from_except | |
1150 | ||
0ebc4cda | 1151 | |
1a6822d1 NP |
1152 | EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20) |
1153 | EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40) | |
792cbddd NP |
1154 | TRAMP_KVM(PACA_EXGEN, 0xf40) |
1155 | EXC_COMMON_BEGIN(vsx_unavailable_common) | |
1156 | EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) | |
1157 | #ifdef CONFIG_VSX | |
1158 | BEGIN_FTR_SECTION | |
1159 | beq 1f | |
1160 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1161 | BEGIN_FTR_SECTION_NESTED(69) | |
1162 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1163 | * transaction), go do TM stuff | |
1164 | */ | |
1165 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1166 | bne- 2f | |
1167 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1168 | #endif | |
1169 | b load_up_vsx | |
1170 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1171 | 2: /* User process was in a transaction */ | |
1172 | bl save_nvgprs | |
1173 | RECONCILE_IRQ_STATE(r10, r11) | |
1174 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1175 | bl vsx_unavailable_tm | |
1176 | b ret_from_except | |
1177 | #endif | |
1178 | 1: | |
1179 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
1180 | #endif | |
1181 | bl save_nvgprs | |
1182 | RECONCILE_IRQ_STATE(r10, r11) | |
1183 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1184 | bl vsx_unavailable_exception | |
1185 | b ret_from_except | |
1186 | ||
da2bc464 | 1187 | |
1a6822d1 NP |
1188 | EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20) |
1189 | EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60) | |
1134713c NP |
1190 | TRAMP_KVM(PACA_EXGEN, 0xf60) |
1191 | EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) | |
1192 | ||
da2bc464 | 1193 | |
1a6822d1 NP |
1194 | EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20) |
1195 | EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80) | |
14b0072c NP |
1196 | TRAMP_KVM_HV(PACA_EXGEN, 0xf80) |
1197 | EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) | |
1198 | ||
da2bc464 | 1199 | |
1a6822d1 NP |
1200 | EXC_REAL_NONE(0xfa0, 0x20) |
1201 | EXC_VIRT_NONE(0x4fa0, 0x20) | |
1202 | EXC_REAL_NONE(0xfc0, 0x20) | |
1203 | EXC_VIRT_NONE(0x4fc0, 0x20) | |
1204 | EXC_REAL_NONE(0xfe0, 0x20) | |
1205 | EXC_VIRT_NONE(0x4fe0, 0x20) | |
1206 | ||
1207 | EXC_REAL_NONE(0x1000, 0x100) | |
1208 | EXC_VIRT_NONE(0x5000, 0x100) | |
1209 | EXC_REAL_NONE(0x1100, 0x100) | |
1210 | EXC_VIRT_NONE(0x5100, 0x100) | |
d0c0c9a1 | 1211 | |
0ebc4cda | 1212 | #ifdef CONFIG_CBE_RAS |
1a6822d1 NP |
1213 | EXC_REAL_HV(cbe_system_error, 0x1200, 0x100) |
1214 | EXC_VIRT_NONE(0x5200, 0x100) | |
da2bc464 | 1215 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) |
ff1b3206 | 1216 | EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) |
da2bc464 | 1217 | #else /* CONFIG_CBE_RAS */ |
1a6822d1 NP |
1218 | EXC_REAL_NONE(0x1200, 0x100) |
1219 | EXC_VIRT_NONE(0x5200, 0x100) | |
da2bc464 | 1220 | #endif |
b01c8b54 | 1221 | |
ff1b3206 | 1222 | |
1a6822d1 NP |
1223 | EXC_REAL(instruction_breakpoint, 0x1300, 0x100) |
1224 | EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300) | |
da2bc464 | 1225 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) |
4e96dbbf NP |
1226 | EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) |
1227 | ||
1a6822d1 NP |
1228 | EXC_REAL_NONE(0x1400, 0x100) |
1229 | EXC_VIRT_NONE(0x5400, 0x100) | |
da2bc464 | 1230 | |
1a6822d1 | 1231 | EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100) |
b92a66a6 | 1232 | mtspr SPRN_SPRG_HSCRATCH0,r13 |
1707dd16 | 1233 | EXCEPTION_PROLOG_0(PACA_EXGEN) |
630573c1 | 1234 | EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500) |
b92a66a6 MN |
1235 | |
1236 | #ifdef CONFIG_PPC_DENORMALISATION | |
1237 | mfspr r10,SPRN_HSRR1 | |
afcf0095 | 1238 | andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ |
afcf0095 NP |
1239 | bne+ denorm_assist |
1240 | #endif | |
1e9b4507 | 1241 | |
4bb3c7a0 | 1242 | KVMTEST_HV(0x1500) |
cb58a4a4 | 1243 | EXCEPTION_PROLOG_2(denorm_common, EXC_HV) |
1a6822d1 | 1244 | EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100) |
a74599a5 | 1245 | |
d7e89849 | 1246 | #ifdef CONFIG_PPC_DENORMALISATION |
1a6822d1 | 1247 | EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100) |
d7e89849 | 1248 | b exc_real_0x1500_denorm_exception_hv |
1a6822d1 | 1249 | EXC_VIRT_END(denorm_exception, 0x5500, 0x100) |
d7e89849 | 1250 | #else |
1a6822d1 | 1251 | EXC_VIRT_NONE(0x5500, 0x100) |
afcf0095 NP |
1252 | #endif |
1253 | ||
4bb3c7a0 | 1254 | TRAMP_KVM_HV(PACA_EXGEN, 0x1500) |
b01c8b54 | 1255 | |
b92a66a6 | 1256 | #ifdef CONFIG_PPC_DENORMALISATION |
da2bc464 | 1257 | TRAMP_REAL_BEGIN(denorm_assist) |
b92a66a6 MN |
1258 | BEGIN_FTR_SECTION |
1259 | /* | |
1260 | * To denormalise we need to move a copy of the register to itself. | |
1261 | * For POWER6 do that here for all FP regs. | |
1262 | */ | |
1263 | mfmsr r10 | |
1264 | ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) | |
1265 | xori r10,r10,(MSR_FE0|MSR_FE1) | |
1266 | mtmsrd r10 | |
1267 | sync | |
d7c67fb1 MN |
1268 | |
1269 | #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1 | |
1270 | #define FMR4(n) FMR2(n) ; FMR2(n+2) | |
1271 | #define FMR8(n) FMR4(n) ; FMR4(n+4) | |
1272 | #define FMR16(n) FMR8(n) ; FMR8(n+8) | |
1273 | #define FMR32(n) FMR16(n) ; FMR16(n+16) | |
1274 | FMR32(0) | |
1275 | ||
b92a66a6 MN |
1276 | FTR_SECTION_ELSE |
1277 | /* | |
1278 | * To denormalise we need to move a copy of the register to itself. | |
1279 | * For POWER7 do that here for the first 32 VSX registers only. | |
1280 | */ | |
1281 | mfmsr r10 | |
1282 | oris r10,r10,MSR_VSX@h | |
1283 | mtmsrd r10 | |
1284 | sync | |
d7c67fb1 MN |
1285 | |
1286 | #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1) | |
1287 | #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2) | |
1288 | #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4) | |
1289 | #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8) | |
1290 | #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16) | |
1291 | XVCPSGNDP32(0) | |
1292 | ||
b92a66a6 | 1293 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) |
fb0fce3e MN |
1294 | |
1295 | BEGIN_FTR_SECTION | |
1296 | b denorm_done | |
1297 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
1298 | /* | |
1299 | * To denormalise we need to move a copy of the register to itself. | |
1300 | * For POWER8 we need to do that for all 64 VSX registers | |
1301 | */ | |
1302 | XVCPSGNDP32(32) | |
1303 | denorm_done: | |
f14040bc MN |
1304 | mfspr r11,SPRN_HSRR0 |
1305 | subi r11,r11,4 | |
b92a66a6 MN |
1306 | mtspr SPRN_HSRR0,r11 |
1307 | mtcrf 0x80,r9 | |
1308 | ld r9,PACA_EXGEN+EX_R9(r13) | |
44e9309f | 1309 | RESTORE_PPR_PACA(PACA_EXGEN, r10) |
630573c1 PM |
1310 | BEGIN_FTR_SECTION |
1311 | ld r10,PACA_EXGEN+EX_CFAR(r13) | |
1312 | mtspr SPRN_CFAR,r10 | |
1313 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
b92a66a6 MN |
1314 | ld r10,PACA_EXGEN+EX_R10(r13) |
1315 | ld r11,PACA_EXGEN+EX_R11(r13) | |
1316 | ld r12,PACA_EXGEN+EX_R12(r13) | |
1317 | ld r13,PACA_EXGEN+EX_R13(r13) | |
222f20f1 | 1318 | HRFI_TO_UNKNOWN |
b92a66a6 MN |
1319 | b . |
1320 | #endif | |
1321 | ||
872e2ae4 | 1322 | EXC_COMMON(denorm_common, 0x1500, unknown_exception) |
d7e89849 NP |
1323 | |
1324 | ||
1325 | #ifdef CONFIG_CBE_RAS | |
1a6822d1 NP |
1326 | EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100) |
1327 | EXC_VIRT_NONE(0x5600, 0x100) | |
d7e89849 | 1328 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) |
69a79344 | 1329 | EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) |
d7e89849 | 1330 | #else /* CONFIG_CBE_RAS */ |
1a6822d1 NP |
1331 | EXC_REAL_NONE(0x1600, 0x100) |
1332 | EXC_VIRT_NONE(0x5600, 0x100) | |
d7e89849 NP |
1333 | #endif |
1334 | ||
69a79344 | 1335 | |
1a6822d1 NP |
1336 | EXC_REAL(altivec_assist, 0x1700, 0x100) |
1337 | EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700) | |
d7e89849 | 1338 | TRAMP_KVM(PACA_EXGEN, 0x1700) |
b51c079e NP |
1339 | #ifdef CONFIG_ALTIVEC |
1340 | EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) | |
1341 | #else | |
1342 | EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) | |
1343 | #endif | |
1344 | ||
d7e89849 NP |
1345 | |
1346 | #ifdef CONFIG_CBE_RAS | |
1a6822d1 NP |
1347 | EXC_REAL_HV(cbe_thermal, 0x1800, 0x100) |
1348 | EXC_VIRT_NONE(0x5800, 0x100) | |
d7e89849 | 1349 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) |
3965f8ab | 1350 | EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) |
d7e89849 | 1351 | #else /* CONFIG_CBE_RAS */ |
1a6822d1 NP |
1352 | EXC_REAL_NONE(0x1800, 0x100) |
1353 | EXC_VIRT_NONE(0x5800, 0x100) | |
d7e89849 NP |
1354 | #endif |
1355 | ||
75eb767e | 1356 | #ifdef CONFIG_PPC_WATCHDOG |
2104180a NP |
1357 | |
1358 | #define MASKED_DEC_HANDLER_LABEL 3f | |
1359 | ||
1360 | #define MASKED_DEC_HANDLER(_H) \ | |
1361 | 3: /* soft-nmi */ \ | |
1362 | std r12,PACA_EXGEN+EX_R12(r13); \ | |
1363 | GET_SCRATCH0(r10); \ | |
1364 | std r10,PACA_EXGEN+EX_R13(r13); \ | |
cb58a4a4 | 1365 | EXCEPTION_PROLOG_2(soft_nmi_common, _H) |
2104180a | 1366 | |
cc491f1d NP |
1367 | /* |
1368 | * Branch to soft_nmi_interrupt using the emergency stack. The emergency | |
1369 | * stack is one that is usable by maskable interrupts so long as MSR_EE | |
1370 | * remains off. It is used for recovery when something has corrupted the | |
1371 | * normal kernel stack, for example. The "soft NMI" must not use the process | |
1372 | * stack because we want irq disabled sections to avoid touching the stack | |
1373 | * at all (other than PMU interrupts), so use the emergency stack for this, | |
1374 | * and run it entirely with interrupts hard disabled. | |
1375 | */ | |
2104180a NP |
1376 | EXC_COMMON_BEGIN(soft_nmi_common) |
1377 | mr r10,r1 | |
1378 | ld r1,PACAEMERGSP(r13) | |
2104180a NP |
1379 | subi r1,r1,INT_FRAME_SIZE |
1380 | EXCEPTION_COMMON_NORET_STACK(PACA_EXGEN, 0x900, | |
1381 | system_reset, soft_nmi_interrupt, | |
1382 | ADD_NVGPRS;ADD_RECONCILE) | |
1383 | b ret_from_except | |
1384 | ||
75eb767e | 1385 | #else /* CONFIG_PPC_WATCHDOG */ |
2104180a NP |
1386 | #define MASKED_DEC_HANDLER_LABEL 2f /* normal return */ |
1387 | #define MASKED_DEC_HANDLER(_H) | |
75eb767e | 1388 | #endif /* CONFIG_PPC_WATCHDOG */ |
d7e89849 | 1389 | |
0ebc4cda | 1390 | /* |
fe9e1d54 IM |
1391 | * An interrupt came in while soft-disabled. We set paca->irq_happened, then: |
1392 | * - If it was a decrementer interrupt, we bump the dec to max and and return. | |
1393 | * - If it was a doorbell we return immediately since doorbells are edge | |
1394 | * triggered and won't automatically refire. | |
0869b6fd MS |
1395 | * - If it was a HMI we return immediately since we handled it in realmode |
1396 | * and it won't refire. | |
6cc3f91b | 1397 | * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return. |
fe9e1d54 | 1398 | * This is called with r10 containing the value to OR to the paca field. |
0ebc4cda | 1399 | */ |
7230c564 BH |
1400 | #define MASKED_INTERRUPT(_H) \ |
1401 | masked_##_H##interrupt: \ | |
1402 | std r11,PACA_EXGEN+EX_R11(r13); \ | |
1403 | lbz r11,PACAIRQHAPPENED(r13); \ | |
1404 | or r11,r11,r10; \ | |
1405 | stb r11,PACAIRQHAPPENED(r13); \ | |
fe9e1d54 IM |
1406 | cmpwi r10,PACA_IRQ_DEC; \ |
1407 | bne 1f; \ | |
7230c564 BH |
1408 | lis r10,0x7fff; \ |
1409 | ori r10,r10,0xffff; \ | |
1410 | mtspr SPRN_DEC,r10; \ | |
2104180a | 1411 | b MASKED_DEC_HANDLER_LABEL; \ |
6cc3f91b NP |
1412 | 1: andi. r10,r10,PACA_IRQ_MUST_HARD_MASK; \ |
1413 | beq 2f; \ | |
fe9e1d54 | 1414 | mfspr r10,SPRN_##_H##SRR1; \ |
6e9a2f6e | 1415 | xori r10,r10,MSR_EE; /* clear MSR_EE */ \ |
7230c564 | 1416 | mtspr SPRN_##_H##SRR1,r10; \ |
9b81c021 NP |
1417 | ori r11,r11,PACA_IRQ_HARD_DIS; \ |
1418 | stb r11,PACAIRQHAPPENED(r13); \ | |
1419 | 2: /* done */ \ | |
1420 | mtcrf 0x80,r9; \ | |
7b08729c | 1421 | std r1,PACAR1(r13); \ |
7230c564 BH |
1422 | ld r9,PACA_EXGEN+EX_R9(r13); \ |
1423 | ld r10,PACA_EXGEN+EX_R10(r13); \ | |
1424 | ld r11,PACA_EXGEN+EX_R11(r13); \ | |
c05f0be8 | 1425 | /* returns to kernel where r13 must be set up, so don't restore it */ \ |
222f20f1 | 1426 | ##_H##RFI_TO_KERNEL; \ |
2104180a NP |
1427 | b .; \ |
1428 | MASKED_DEC_HANDLER(_H) | |
57f26649 | 1429 | |
a048a07d NP |
1430 | TRAMP_REAL_BEGIN(stf_barrier_fallback) |
1431 | std r9,PACA_EXRFI+EX_R9(r13) | |
1432 | std r10,PACA_EXRFI+EX_R10(r13) | |
1433 | sync | |
1434 | ld r9,PACA_EXRFI+EX_R9(r13) | |
1435 | ld r10,PACA_EXRFI+EX_R10(r13) | |
1436 | ori 31,31,0 | |
1437 | .rept 14 | |
1438 | b 1f | |
1439 | 1: | |
1440 | .endr | |
1441 | blr | |
1442 | ||
aa8a5e00 ME |
1443 | TRAMP_REAL_BEGIN(rfi_flush_fallback) |
1444 | SET_SCRATCH0(r13); | |
1445 | GET_PACA(r13); | |
78ee9946 ME |
1446 | std r1,PACA_EXRFI+EX_R12(r13) |
1447 | ld r1,PACAKSAVE(r13) | |
aa8a5e00 ME |
1448 | std r9,PACA_EXRFI+EX_R9(r13) |
1449 | std r10,PACA_EXRFI+EX_R10(r13) | |
1450 | std r11,PACA_EXRFI+EX_R11(r13) | |
aa8a5e00 ME |
1451 | mfctr r9 |
1452 | ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) | |
bdcb1aef NP |
1453 | ld r11,PACA_L1D_FLUSH_SIZE(r13) |
1454 | srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ | |
aa8a5e00 | 1455 | mtctr r11 |
15a3204d | 1456 | DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ |
aa8a5e00 ME |
1457 | |
1458 | /* order ld/st prior to dcbt stop all streams with flushing */ | |
1459 | sync | |
bdcb1aef NP |
1460 | |
1461 | /* | |
1462 | * The load adresses are at staggered offsets within cachelines, | |
1463 | * which suits some pipelines better (on others it should not | |
1464 | * hurt). | |
1465 | */ | |
1466 | 1: | |
1467 | ld r11,(0x80 + 8)*0(r10) | |
1468 | ld r11,(0x80 + 8)*1(r10) | |
1469 | ld r11,(0x80 + 8)*2(r10) | |
1470 | ld r11,(0x80 + 8)*3(r10) | |
1471 | ld r11,(0x80 + 8)*4(r10) | |
1472 | ld r11,(0x80 + 8)*5(r10) | |
1473 | ld r11,(0x80 + 8)*6(r10) | |
1474 | ld r11,(0x80 + 8)*7(r10) | |
1475 | addi r10,r10,0x80*8 | |
aa8a5e00 ME |
1476 | bdnz 1b |
1477 | ||
1478 | mtctr r9 | |
1479 | ld r9,PACA_EXRFI+EX_R9(r13) | |
1480 | ld r10,PACA_EXRFI+EX_R10(r13) | |
1481 | ld r11,PACA_EXRFI+EX_R11(r13) | |
78ee9946 | 1482 | ld r1,PACA_EXRFI+EX_R12(r13) |
aa8a5e00 ME |
1483 | GET_SCRATCH0(r13); |
1484 | rfid | |
1485 | ||
1486 | TRAMP_REAL_BEGIN(hrfi_flush_fallback) | |
1487 | SET_SCRATCH0(r13); | |
1488 | GET_PACA(r13); | |
78ee9946 ME |
1489 | std r1,PACA_EXRFI+EX_R12(r13) |
1490 | ld r1,PACAKSAVE(r13) | |
aa8a5e00 ME |
1491 | std r9,PACA_EXRFI+EX_R9(r13) |
1492 | std r10,PACA_EXRFI+EX_R10(r13) | |
1493 | std r11,PACA_EXRFI+EX_R11(r13) | |
aa8a5e00 ME |
1494 | mfctr r9 |
1495 | ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) | |
bdcb1aef NP |
1496 | ld r11,PACA_L1D_FLUSH_SIZE(r13) |
1497 | srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ | |
aa8a5e00 | 1498 | mtctr r11 |
15a3204d | 1499 | DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ |
aa8a5e00 ME |
1500 | |
1501 | /* order ld/st prior to dcbt stop all streams with flushing */ | |
1502 | sync | |
bdcb1aef NP |
1503 | |
1504 | /* | |
1505 | * The load adresses are at staggered offsets within cachelines, | |
1506 | * which suits some pipelines better (on others it should not | |
1507 | * hurt). | |
1508 | */ | |
1509 | 1: | |
1510 | ld r11,(0x80 + 8)*0(r10) | |
1511 | ld r11,(0x80 + 8)*1(r10) | |
1512 | ld r11,(0x80 + 8)*2(r10) | |
1513 | ld r11,(0x80 + 8)*3(r10) | |
1514 | ld r11,(0x80 + 8)*4(r10) | |
1515 | ld r11,(0x80 + 8)*5(r10) | |
1516 | ld r11,(0x80 + 8)*6(r10) | |
1517 | ld r11,(0x80 + 8)*7(r10) | |
1518 | addi r10,r10,0x80*8 | |
aa8a5e00 ME |
1519 | bdnz 1b |
1520 | ||
1521 | mtctr r9 | |
1522 | ld r9,PACA_EXRFI+EX_R9(r13) | |
1523 | ld r10,PACA_EXRFI+EX_R10(r13) | |
1524 | ld r11,PACA_EXRFI+EX_R11(r13) | |
78ee9946 | 1525 | ld r1,PACA_EXRFI+EX_R12(r13) |
aa8a5e00 ME |
1526 | GET_SCRATCH0(r13); |
1527 | hrfid | |
1528 | ||
57f26649 NP |
1529 | /* |
1530 | * Real mode exceptions actually use this too, but alternate | |
1531 | * instruction code patches (which end up in the common .text area) | |
1532 | * cannot reach these if they are put there. | |
1533 | */ | |
1534 | USE_FIXED_SECTION(virt_trampolines) | |
7230c564 BH |
1535 | MASKED_INTERRUPT() |
1536 | MASKED_INTERRUPT(H) | |
0ebc4cda | 1537 | |
4f6c11db | 1538 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
da2bc464 | 1539 | TRAMP_REAL_BEGIN(kvmppc_skip_interrupt) |
4f6c11db PM |
1540 | /* |
1541 | * Here all GPRs are unchanged from when the interrupt happened | |
1542 | * except for r13, which is saved in SPRG_SCRATCH0. | |
1543 | */ | |
1544 | mfspr r13, SPRN_SRR0 | |
1545 | addi r13, r13, 4 | |
1546 | mtspr SPRN_SRR0, r13 | |
1547 | GET_SCRATCH0(r13) | |
222f20f1 | 1548 | RFI_TO_KERNEL |
4f6c11db PM |
1549 | b . |
1550 | ||
da2bc464 | 1551 | TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) |
4f6c11db PM |
1552 | /* |
1553 | * Here all GPRs are unchanged from when the interrupt happened | |
1554 | * except for r13, which is saved in SPRG_SCRATCH0. | |
1555 | */ | |
1556 | mfspr r13, SPRN_HSRR0 | |
1557 | addi r13, r13, 4 | |
1558 | mtspr SPRN_HSRR0, r13 | |
1559 | GET_SCRATCH0(r13) | |
222f20f1 | 1560 | HRFI_TO_KERNEL |
4f6c11db PM |
1561 | b . |
1562 | #endif | |
1563 | ||
0ebc4cda | 1564 | /* |
057b6d7e HB |
1565 | * Ensure that any handlers that get invoked from the exception prologs |
1566 | * above are below the first 64KB (0x10000) of the kernel image because | |
1567 | * the prologs assemble the addresses of these handlers using the | |
1568 | * LOAD_HANDLER macro, which uses an ori instruction. | |
0ebc4cda BH |
1569 | */ |
1570 | ||
1571 | /*** Common interrupt handlers ***/ | |
1572 | ||
0ebc4cda | 1573 | |
c1fb6816 MN |
1574 | /* |
1575 | * Relocation-on interrupts: A subset of the interrupts can be delivered | |
1576 | * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering | |
1577 | * it. Addresses are the same as the original interrupt addresses, but | |
1578 | * offset by 0xc000000000004000. | |
1579 | * It's impossible to receive interrupts below 0x300 via this mechanism. | |
1580 | * KVM: None of these traps are from the guest ; anything that escalated | |
1581 | * to HV=1 from HV=0 is delivered via real mode handlers. | |
1582 | */ | |
1583 | ||
1584 | /* | |
1585 | * This uses the standard macro, since the original 0x300 vector | |
1586 | * only has extra guff for STAB-based processors -- which never | |
1587 | * come here. | |
1588 | */ | |
da2bc464 | 1589 | |
57f26649 | 1590 | EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) |
b1576fec | 1591 | b __ppc64_runlatch_on |
fe1952fc | 1592 | |
57f26649 | 1593 | USE_FIXED_SECTION(virt_trampolines) |
8ed8ab40 HB |
1594 | /* |
1595 | * The __end_interrupts marker must be past the out-of-line (OOL) | |
1596 | * handlers, so that they are copied to real address 0x100 when running | |
1597 | * a relocatable kernel. This ensures they can be reached from the short | |
1598 | * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch | |
1599 | * directly, without using LOAD_HANDLER(). | |
1600 | */ | |
1601 | .align 7 | |
1602 | .globl __end_interrupts | |
1603 | __end_interrupts: | |
57f26649 | 1604 | DEFINE_FIXED_SYMBOL(__end_interrupts) |
61383407 | 1605 | |
087aa036 | 1606 | #ifdef CONFIG_PPC_970_NAP |
7c8cb4b5 | 1607 | EXC_COMMON_BEGIN(power4_fixup_nap) |
087aa036 CG |
1608 | andc r9,r9,r10 |
1609 | std r9,TI_LOCAL_FLAGS(r11) | |
1610 | ld r10,_LINK(r1) /* make idle task do the */ | |
1611 | std r10,_NIP(r1) /* equivalent of a blr */ | |
1612 | blr | |
1613 | #endif | |
1614 | ||
57f26649 NP |
1615 | CLOSE_FIXED_SECTION(real_vectors); |
1616 | CLOSE_FIXED_SECTION(real_trampolines); | |
1617 | CLOSE_FIXED_SECTION(virt_vectors); | |
1618 | CLOSE_FIXED_SECTION(virt_trampolines); | |
1619 | ||
1620 | USE_TEXT_SECTION() | |
1621 | ||
0ebc4cda BH |
1622 | /* |
1623 | * Hash table stuff | |
1624 | */ | |
f4329f2e | 1625 | .balign IFETCH_ALIGN_BYTES |
6a3bab90 | 1626 | do_hash_page: |
4e003747 | 1627 | #ifdef CONFIG_PPC_BOOK3S_64 |
e6c2a479 | 1628 | lis r0,(DSISR_BAD_FAULT_64S | DSISR_DABRMATCH | DSISR_KEYFAULT)@h |
398a719d BH |
1629 | ori r0,r0,DSISR_BAD_FAULT_64S@l |
1630 | and. r0,r4,r0 /* weird error? */ | |
0ebc4cda | 1631 | bne- handle_page_fault /* if not, try to insert a HPTE */ |
9778b696 | 1632 | CURRENT_THREAD_INFO(r11, r1) |
9c1e1052 PM |
1633 | lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ |
1634 | andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ | |
1635 | bne 77f /* then don't call hash_page now */ | |
0ebc4cda BH |
1636 | |
1637 | /* | |
1638 | * r3 contains the faulting address | |
106713a1 | 1639 | * r4 msr |
0ebc4cda | 1640 | * r5 contains the trap number |
aefa5688 | 1641 | * r6 contains dsisr |
0ebc4cda | 1642 | * |
7230c564 | 1643 | * at return r3 = 0 for success, 1 for page fault, negative for error |
0ebc4cda | 1644 | */ |
106713a1 | 1645 | mr r4,r12 |
aefa5688 | 1646 | ld r6,_DSISR(r1) |
106713a1 AK |
1647 | bl __hash_page /* build HPTE if possible */ |
1648 | cmpdi r3,0 /* see if __hash_page succeeded */ | |
0ebc4cda | 1649 | |
7230c564 | 1650 | /* Success */ |
0ebc4cda | 1651 | beq fast_exc_return_irq /* Return from exception on success */ |
0ebc4cda | 1652 | |
7230c564 BH |
1653 | /* Error */ |
1654 | blt- 13f | |
d89ba535 NR |
1655 | |
1656 | /* Reload DSISR into r4 for the DABR check below */ | |
1657 | ld r4,_DSISR(r1) | |
4e003747 | 1658 | #endif /* CONFIG_PPC_BOOK3S_64 */ |
9c7cc234 | 1659 | |
0ebc4cda BH |
1660 | /* Here we have a page fault that hash_page can't handle. */ |
1661 | handle_page_fault: | |
d89ba535 NR |
1662 | 11: andis. r0,r4,DSISR_DABRMATCH@h |
1663 | bne- handle_dabr_fault | |
1664 | ld r4,_DAR(r1) | |
0ebc4cda BH |
1665 | ld r5,_DSISR(r1) |
1666 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec | 1667 | bl do_page_fault |
0ebc4cda | 1668 | cmpdi r3,0 |
a546498f | 1669 | beq+ 12f |
b1576fec | 1670 | bl save_nvgprs |
0ebc4cda BH |
1671 | mr r5,r3 |
1672 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1673 | lwz r4,_DAR(r1) | |
b1576fec AB |
1674 | bl bad_page_fault |
1675 | b ret_from_except | |
0ebc4cda | 1676 | |
a546498f BH |
1677 | /* We have a data breakpoint exception - handle it */ |
1678 | handle_dabr_fault: | |
b1576fec | 1679 | bl save_nvgprs |
a546498f BH |
1680 | ld r4,_DAR(r1) |
1681 | ld r5,_DSISR(r1) | |
1682 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec AB |
1683 | bl do_break |
1684 | 12: b ret_from_except_lite | |
a546498f | 1685 | |
0ebc4cda | 1686 | |
4e003747 | 1687 | #ifdef CONFIG_PPC_BOOK3S_64 |
0ebc4cda BH |
1688 | /* We have a page fault that hash_page could handle but HV refused |
1689 | * the PTE insertion | |
1690 | */ | |
b1576fec | 1691 | 13: bl save_nvgprs |
0ebc4cda BH |
1692 | mr r5,r3 |
1693 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1694 | ld r4,_DAR(r1) | |
b1576fec AB |
1695 | bl low_hash_fault |
1696 | b ret_from_except | |
caca285e | 1697 | #endif |
0ebc4cda | 1698 | |
9c1e1052 PM |
1699 | /* |
1700 | * We come here as a result of a DSI at a point where we don't want | |
1701 | * to call hash_page, such as when we are accessing memory (possibly | |
1702 | * user memory) inside a PMU interrupt that occurred while interrupts | |
1703 | * were soft-disabled. We want to invoke the exception handler for | |
1704 | * the access, or panic if there isn't a handler. | |
1705 | */ | |
b1576fec | 1706 | 77: bl save_nvgprs |
9c1e1052 PM |
1707 | mr r4,r3 |
1708 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1709 | li r5,SIGSEGV | |
b1576fec AB |
1710 | bl bad_page_fault |
1711 | b ret_from_except | |
4e2bf01b ME |
1712 | |
1713 | /* | |
1714 | * Here we have detected that the kernel stack pointer is bad. | |
1715 | * R9 contains the saved CR, r13 points to the paca, | |
1716 | * r10 contains the (bad) kernel stack pointer, | |
1717 | * r11 and r12 contain the saved SRR0 and SRR1. | |
1718 | * We switch to using an emergency stack, save the registers there, | |
1719 | * and call kernel_bad_stack(), which panics. | |
1720 | */ | |
1721 | bad_stack: | |
1722 | ld r1,PACAEMERGSP(r13) | |
1723 | subi r1,r1,64+INT_FRAME_SIZE | |
1724 | std r9,_CCR(r1) | |
1725 | std r10,GPR1(r1) | |
1726 | std r11,_NIP(r1) | |
1727 | std r12,_MSR(r1) | |
1728 | mfspr r11,SPRN_DAR | |
1729 | mfspr r12,SPRN_DSISR | |
1730 | std r11,_DAR(r1) | |
1731 | std r12,_DSISR(r1) | |
1732 | mflr r10 | |
1733 | mfctr r11 | |
1734 | mfxer r12 | |
1735 | std r10,_LINK(r1) | |
1736 | std r11,_CTR(r1) | |
1737 | std r12,_XER(r1) | |
1738 | SAVE_GPR(0,r1) | |
1739 | SAVE_GPR(2,r1) | |
1740 | ld r10,EX_R3(r3) | |
1741 | std r10,GPR3(r1) | |
1742 | SAVE_GPR(4,r1) | |
1743 | SAVE_4GPRS(5,r1) | |
1744 | ld r9,EX_R9(r3) | |
1745 | ld r10,EX_R10(r3) | |
1746 | SAVE_2GPRS(9,r1) | |
1747 | ld r9,EX_R11(r3) | |
1748 | ld r10,EX_R12(r3) | |
1749 | ld r11,EX_R13(r3) | |
1750 | std r9,GPR11(r1) | |
1751 | std r10,GPR12(r1) | |
1752 | std r11,GPR13(r1) | |
1753 | BEGIN_FTR_SECTION | |
1754 | ld r10,EX_CFAR(r3) | |
1755 | std r10,ORIG_GPR3(r1) | |
1756 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
1757 | SAVE_8GPRS(14,r1) | |
1758 | SAVE_10GPRS(22,r1) | |
1759 | lhz r12,PACA_TRAP_SAVE(r13) | |
1760 | std r12,_TRAP(r1) | |
1761 | addi r11,r1,INT_FRAME_SIZE | |
1762 | std r11,0(r1) | |
1763 | li r12,0 | |
1764 | std r12,0(r11) | |
1765 | ld r2,PACATOC(r13) | |
1766 | ld r11,exception_marker@toc(r2) | |
1767 | std r12,RESULT(r1) | |
1768 | std r11,STACK_FRAME_OVERHEAD-16(r1) | |
1769 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
1770 | bl kernel_bad_stack | |
1771 | b 1b | |
15770a13 | 1772 | _ASM_NOKPROBE_SYMBOL(bad_stack); |
0f0c6ca1 | 1773 | |
a9af97aa NP |
1774 | /* |
1775 | * When doorbell is triggered from system reset wakeup, the message is | |
1776 | * not cleared, so it would fire again when EE is enabled. | |
1777 | * | |
1778 | * When coming from local_irq_enable, there may be the same problem if | |
1779 | * we were hard disabled. | |
1780 | * | |
1781 | * Execute msgclr to clear pending exceptions before handling it. | |
1782 | */ | |
1783 | h_doorbell_common_msgclr: | |
1784 | LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) | |
1785 | PPC_MSGCLR(3) | |
1786 | b h_doorbell_common | |
1787 | ||
1788 | doorbell_super_common_msgclr: | |
1789 | LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) | |
1790 | PPC_MSGCLRP(3) | |
1791 | b doorbell_super_common | |
1792 | ||
0f0c6ca1 NP |
1793 | /* |
1794 | * Called from arch_local_irq_enable when an interrupt needs | |
1795 | * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate | |
1796 | * which kind of interrupt. MSR:EE is already off. We generate a | |
1797 | * stackframe like if a real interrupt had happened. | |
1798 | * | |
1799 | * Note: While MSR:EE is off, we need to make sure that _MSR | |
1800 | * in the generated frame has EE set to 1 or the exception | |
1801 | * handler will not properly re-enable them. | |
b48bbb82 NP |
1802 | * |
1803 | * Note that we don't specify LR as the NIP (return address) for | |
1804 | * the interrupt because that would unbalance the return branch | |
1805 | * predictor. | |
0f0c6ca1 NP |
1806 | */ |
1807 | _GLOBAL(__replay_interrupt) | |
1808 | /* We are going to jump to the exception common code which | |
1809 | * will retrieve various register values from the PACA which | |
1810 | * we don't give a damn about, so we don't bother storing them. | |
1811 | */ | |
1812 | mfmsr r12 | |
3e23a12b | 1813 | LOAD_REG_ADDR(r11, replay_interrupt_return) |
0f0c6ca1 NP |
1814 | mfcr r9 |
1815 | ori r12,r12,MSR_EE | |
1816 | cmpwi r3,0x900 | |
1817 | beq decrementer_common | |
1818 | cmpwi r3,0x500 | |
e6c1203d NP |
1819 | BEGIN_FTR_SECTION |
1820 | beq h_virt_irq_common | |
1821 | FTR_SECTION_ELSE | |
0f0c6ca1 | 1822 | beq hardware_interrupt_common |
e6c1203d | 1823 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_300) |
f442d004 MS |
1824 | cmpwi r3,0xf00 |
1825 | beq performance_monitor_common | |
0f0c6ca1 | 1826 | BEGIN_FTR_SECTION |
d6f73fc6 | 1827 | cmpwi r3,0xa00 |
a9af97aa | 1828 | beq h_doorbell_common_msgclr |
0f0c6ca1 NP |
1829 | cmpwi r3,0xe60 |
1830 | beq hmi_exception_common | |
1831 | FTR_SECTION_ELSE | |
1832 | cmpwi r3,0xa00 | |
a9af97aa | 1833 | beq doorbell_super_common_msgclr |
0f0c6ca1 | 1834 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
3e23a12b | 1835 | replay_interrupt_return: |
0f0c6ca1 | 1836 | blr |
b48bbb82 | 1837 | |
15770a13 | 1838 | _ASM_NOKPROBE_SYMBOL(__replay_interrupt) |