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powerpc/fsl-booke64: Add support for Debug Level exception handler
[linux-2.6-block.git] / arch / powerpc / kernel / exceptions-64e.S
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2d27cfd3
BH		 1/*
2 * Boot code and exception vectors for Book3E processors
3 *
4 * Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/threads.h>
13#include <asm/reg.h>
14#include <asm/page.h>
15#include <asm/ppc_asm.h>
16#include <asm/asm-offsets.h>
17#include <asm/cputable.h>
18#include <asm/setup.h>
19#include <asm/thread_info.h>
a0496d45 20#include <asm/reg_a2.h>
2d27cfd3
BH		 21#include <asm/exception-64e.h>
22#include <asm/bug.h>
23#include <asm/irqflags.h>
24#include <asm/ptrace.h>
25#include <asm/ppc-opcode.h>
26#include <asm/mmu.h>
27
28/* XXX This will ultimately add space for a special exception save
29 * structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
30 * when taking special interrupts. For now we don't support that,
31 * special interrupts from within a non-standard level will probably
32 * blow you up
33 */
34#define SPECIAL_EXC_FRAME_SIZE INT_FRAME_SIZE
35
36/* Exception prolog code for all exceptions */
37#define EXCEPTION_PROLOG(n, type, addition) \
38 mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \
39 mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \
40 std r10,PACA_EX##type+EX_R10(r13); \
41 std r11,PACA_EX##type+EX_R11(r13); \
42 mfcr r10; /* save CR */ \
43 addition; /* additional code for that exc. */ \
44 std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
45 stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
46 mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
47 type##_SET_KSTACK; /* get special stack if necessary */\
48 andi. r10,r11,MSR_PR; /* save stack pointer */ \
49 beq 1f; /* branch around if supervisor */ \
50 ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\
511: cmpdi cr1,r1,0; /* check if SP makes sense */ \
52 bge- cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \
53 mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */
54
55/* Exception type-specific macros */
56#define GEN_SET_KSTACK \
57 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */
58#define SPRN_GEN_SRR0 SPRN_SRR0
59#define SPRN_GEN_SRR1 SPRN_SRR1
60
61#define CRIT_SET_KSTACK \
62 ld r1,PACA_CRIT_STACK(r13); \
63 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
64#define SPRN_CRIT_SRR0 SPRN_CSRR0
65#define SPRN_CRIT_SRR1 SPRN_CSRR1
66
67#define DBG_SET_KSTACK \
68 ld r1,PACA_DBG_STACK(r13); \
69 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
70#define SPRN_DBG_SRR0 SPRN_DSRR0
71#define SPRN_DBG_SRR1 SPRN_DSRR1
72
73#define MC_SET_KSTACK \
74 ld r1,PACA_MC_STACK(r13); \
75 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
76#define SPRN_MC_SRR0 SPRN_MCSRR0
77#define SPRN_MC_SRR1 SPRN_MCSRR1
78
79#define NORMAL_EXCEPTION_PROLOG(n, addition) \
80 EXCEPTION_PROLOG(n, GEN, addition##_GEN)
81
82#define CRIT_EXCEPTION_PROLOG(n, addition) \
83 EXCEPTION_PROLOG(n, CRIT, addition##_CRIT)
84
85#define DBG_EXCEPTION_PROLOG(n, addition) \
86 EXCEPTION_PROLOG(n, DBG, addition##_DBG)
87
88#define MC_EXCEPTION_PROLOG(n, addition) \
89 EXCEPTION_PROLOG(n, MC, addition##_MC)
90
91
92/* Variants of the "addition" argument for the prolog
93 */
94#define PROLOG_ADDITION_NONE_GEN
95#define PROLOG_ADDITION_NONE_CRIT
96#define PROLOG_ADDITION_NONE_DBG
97#define PROLOG_ADDITION_NONE_MC
98
99#define PROLOG_ADDITION_MASKABLE_GEN \
100 lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
101 cmpwi cr0,r11,0; /* yes -> go out of line */ \
102 beq masked_interrupt_book3e;
103
104#define PROLOG_ADDITION_2REGS_GEN \
105 std r14,PACA_EXGEN+EX_R14(r13); \
106 std r15,PACA_EXGEN+EX_R15(r13)
107
108#define PROLOG_ADDITION_1REG_GEN \
109 std r14,PACA_EXGEN+EX_R14(r13);
110
111#define PROLOG_ADDITION_2REGS_CRIT \
112 std r14,PACA_EXCRIT+EX_R14(r13); \
113 std r15,PACA_EXCRIT+EX_R15(r13)
114
115#define PROLOG_ADDITION_2REGS_DBG \
116 std r14,PACA_EXDBG+EX_R14(r13); \
117 std r15,PACA_EXDBG+EX_R15(r13)
118
119#define PROLOG_ADDITION_2REGS_MC \
120 std r14,PACA_EXMC+EX_R14(r13); \
121 std r15,PACA_EXMC+EX_R15(r13)
122
123/* Core exception code for all exceptions except TLB misses.
124 * XXX: Needs to make SPRN_SPRG_GEN depend on exception type
125 */
126#define EXCEPTION_COMMON(n, excf, ints) \
127 std r0,GPR0(r1); /* save r0 in stackframe */ \
128 std r2,GPR2(r1); /* save r2 in stackframe */ \
129 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
130 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
131 std r9,GPR9(r1); /* save r9 in stackframe */ \
132 std r10,_NIP(r1); /* save SRR0 to stackframe */ \
133 std r11,_MSR(r1); /* save SRR1 to stackframe */ \
134 ACCOUNT_CPU_USER_ENTRY(r10,r11);/* accounting (uses cr0+eq) */ \
135 ld r3,excf+EX_R10(r13); /* get back r10 */ \
136 ld r4,excf+EX_R11(r13); /* get back r11 */ \
137 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 */ \
138 std r12,GPR12(r1); /* save r12 in stackframe */ \
139 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
140 mflr r6; /* save LR in stackframe */ \
141 mfctr r7; /* save CTR in stackframe */ \
142 mfspr r8,SPRN_XER; /* save XER in stackframe */ \
143 ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \
144 lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \
145 lbz r11,PACASOFTIRQEN(r13); /* get current IRQ softe */ \
146 ld r12,exception_marker@toc(r2); \
147 li r0,0; \
148 std r3,GPR10(r1); /* save r10 to stackframe */ \
149 std r4,GPR11(r1); /* save r11 to stackframe */ \
150 std r5,GPR13(r1); /* save it to stackframe */ \
151 std r6,_LINK(r1); \
152 std r7,_CTR(r1); \
153 std r8,_XER(r1); \
154 li r3,(n)+1; /* indicate partial regs in trap */ \
155 std r9,0(r1); /* store stack frame back link */ \
156 std r10,_CCR(r1); /* store orig CR in stackframe */ \
157 std r9,GPR1(r1); /* store stack frame back link */ \
158 std r11,SOFTE(r1); /* and save it to stackframe */ \
159 std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \
160 std r3,_TRAP(r1); /* set trap number */ \
161 std r0,RESULT(r1); /* clear regs->result */ \
162 ints;
163
164/* Variants for the "ints" argument */
165#define INTS_KEEP
166#define INTS_DISABLE_SOFT \
167 stb r0,PACASOFTIRQEN(r13); /* mark interrupts soft-disabled */ \
168 TRACE_DISABLE_INTS;
169#define INTS_DISABLE_HARD \
170 stb r0,PACAHARDIRQEN(r13); /* and hard disabled */
171#define INTS_DISABLE_ALL \
172 INTS_DISABLE_SOFT \
173 INTS_DISABLE_HARD
174
175/* This is called by exceptions that used INTS_KEEP (that is did not clear
176 * neither soft nor hard IRQ indicators in the PACA. This will restore MSR:EE
177 * to it's previous value
178 *
179 * XXX In the long run, we may want to open-code it in order to separate the
180 * load from the wrtee, thus limiting the latency caused by the dependency
181 * but at this point, I'll favor code clarity until we have a near to final
182 * implementation
183 */
184#define INTS_RESTORE_HARD \
185 ld r11,_MSR(r1); \
186 wrtee r11;
187
188/* XXX FIXME: Restore r14/r15 when necessary */
189#define BAD_STACK_TRAMPOLINE(n) \
190exc_##n##_bad_stack: \
191 li r1,(n); /* get exception number */ \
192 sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \
193 b bad_stack_book3e; /* bad stack error */
194
ff82c319
BH		 195/* WARNING: If you change the layout of this stub, make sure you chcek
196 * the debug exception handler which handles single stepping
197 * into exceptions from userspace, and the MM code in
198 * arch/powerpc/mm/tlb_nohash.c which patches the branch here
199 * and would need to be updated if that branch is moved
200 */
2d27cfd3
BH		 201#define EXCEPTION_STUB(loc, label) \
202 . = interrupt_base_book3e + loc; \
203 nop; /* To make debug interrupts happy */ \
204 b exc_##label##_book3e;
205
206#define ACK_NONE(r)
207#define ACK_DEC(r) \
208 lis r,TSR_DIS@h; \
209 mtspr SPRN_TSR,r
210#define ACK_FIT(r) \
211 lis r,TSR_FIS@h; \
212 mtspr SPRN_TSR,r
213
34d97e07
BH		 214/* Used by asynchronous interrupt that may happen in the idle loop.
215 *
216 * This check if the thread was in the idle loop, and if yes, returns
217 * to the caller rather than the PC. This is to avoid a race if
218 * interrupts happen before the wait instruction.
219 */
220#define CHECK_NAPPING() \
221 clrrdi r11,r1,THREAD_SHIFT; \
222 ld r10,TI_LOCAL_FLAGS(r11); \
223 andi. r9,r10,_TLF_NAPPING; \
224 beq+ 1f; \
225 ld r8,_LINK(r1); \
226 rlwinm r7,r10,0,~_TLF_NAPPING; \
227 std r8,_NIP(r1); \
228 std r7,TI_LOCAL_FLAGS(r11); \
2291:
230
231
2d27cfd3
BH		 232#define MASKABLE_EXCEPTION(trapnum, label, hdlr, ack) \
233 START_EXCEPTION(label); \
234 NORMAL_EXCEPTION_PROLOG(trapnum, PROLOG_ADDITION_MASKABLE) \
235 EXCEPTION_COMMON(trapnum, PACA_EXGEN, INTS_DISABLE_ALL) \
236 ack(r8); \
34d97e07 237 CHECK_NAPPING(); \
2d27cfd3
BH		 238 addi r3,r1,STACK_FRAME_OVERHEAD; \
239 bl hdlr; \
240 b .ret_from_except_lite;
241
242/* This value is used to mark exception frames on the stack. */
243 .section ".toc","aw"
244exception_marker:
245 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
246
247
248/*
249 * And here we have the exception vectors !
250 */
251
252 .text
253 .balign 0x1000
254 .globl interrupt_base_book3e
255interrupt_base_book3e: /* fake trap */
2d27cfd3
BH		 256 EXCEPTION_STUB(0x000, machine_check) /* 0x0200 */
257 EXCEPTION_STUB(0x020, critical_input) /* 0x0580 */
258 EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */
259 EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */
260 EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */
261 EXCEPTION_STUB(0x0a0, external_input) /* 0x0500 */
262 EXCEPTION_STUB(0x0c0, alignment) /* 0x0600 */
263 EXCEPTION_STUB(0x0e0, program) /* 0x0700 */
264 EXCEPTION_STUB(0x100, fp_unavailable) /* 0x0800 */
265 EXCEPTION_STUB(0x120, system_call) /* 0x0c00 */
266 EXCEPTION_STUB(0x140, ap_unavailable) /* 0x0f20 */
267 EXCEPTION_STUB(0x160, decrementer) /* 0x0900 */
268 EXCEPTION_STUB(0x180, fixed_interval) /* 0x0980 */
269 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */
270 EXCEPTION_STUB(0x1c0, data_tlb_miss)
271 EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
89c81797
BH		 272 EXCEPTION_STUB(0x280, doorbell)
273 EXCEPTION_STUB(0x2a0, doorbell_crit)
2d27cfd3 274
2d27cfd3
BH		 275 .globl interrupt_end_book3e
276interrupt_end_book3e:
277
278/* Critical Input Interrupt */
279 START_EXCEPTION(critical_input);
280 CRIT_EXCEPTION_PROLOG(0x100, PROLOG_ADDITION_NONE)
281// EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE_ALL)
282// bl special_reg_save_crit
34d97e07 283// CHECK_NAPPING();
2d27cfd3
BH		 284// addi r3,r1,STACK_FRAME_OVERHEAD
285// bl .critical_exception
286// b ret_from_crit_except
287 b .
288
289/* Machine Check Interrupt */
290 START_EXCEPTION(machine_check);
291 CRIT_EXCEPTION_PROLOG(0x200, PROLOG_ADDITION_NONE)
292// EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE_ALL)
293// bl special_reg_save_mc
294// addi r3,r1,STACK_FRAME_OVERHEAD
34d97e07 295// CHECK_NAPPING();
2d27cfd3
BH		 296// bl .machine_check_exception
297// b ret_from_mc_except
298 b .
299
300/* Data Storage Interrupt */
301 START_EXCEPTION(data_storage)
302 NORMAL_EXCEPTION_PROLOG(0x300, PROLOG_ADDITION_2REGS)
303 mfspr r14,SPRN_DEAR
304 mfspr r15,SPRN_ESR
305 EXCEPTION_COMMON(0x300, PACA_EXGEN, INTS_KEEP)
306 b storage_fault_common
307
308/* Instruction Storage Interrupt */
309 START_EXCEPTION(instruction_storage);
310 NORMAL_EXCEPTION_PROLOG(0x400, PROLOG_ADDITION_2REGS)
311 li r15,0
312 mr r14,r10
313 EXCEPTION_COMMON(0x400, PACA_EXGEN, INTS_KEEP)
314 b storage_fault_common
315
316/* External Input Interrupt */
317 MASKABLE_EXCEPTION(0x500, external_input, .do_IRQ, ACK_NONE)
318
319/* Alignment */
320 START_EXCEPTION(alignment);
321 NORMAL_EXCEPTION_PROLOG(0x600, PROLOG_ADDITION_2REGS)
322 mfspr r14,SPRN_DEAR
323 mfspr r15,SPRN_ESR
324 EXCEPTION_COMMON(0x600, PACA_EXGEN, INTS_KEEP)
325 b alignment_more /* no room, go out of line */
326
327/* Program Interrupt */
328 START_EXCEPTION(program);
329 NORMAL_EXCEPTION_PROLOG(0x700, PROLOG_ADDITION_1REG)
330 mfspr r14,SPRN_ESR
331 EXCEPTION_COMMON(0x700, PACA_EXGEN, INTS_DISABLE_SOFT)
332 std r14,_DSISR(r1)
333 addi r3,r1,STACK_FRAME_OVERHEAD
334 ld r14,PACA_EXGEN+EX_R14(r13)
335 bl .save_nvgprs
336 INTS_RESTORE_HARD
337 bl .program_check_exception
338 b .ret_from_except
339
340/* Floating Point Unavailable Interrupt */
341 START_EXCEPTION(fp_unavailable);
342 NORMAL_EXCEPTION_PROLOG(0x800, PROLOG_ADDITION_NONE)
343 /* we can probably do a shorter exception entry for that one... */
344 EXCEPTION_COMMON(0x800, PACA_EXGEN, INTS_KEEP)
345 bne 1f /* if from user, just load it up */
346 bl .save_nvgprs
347 addi r3,r1,STACK_FRAME_OVERHEAD
348 INTS_RESTORE_HARD
349 bl .kernel_fp_unavailable_exception
350 BUG_OPCODE
3511: ld r12,_MSR(r1)
352 bl .load_up_fpu
353 b fast_exception_return
354
355/* Decrementer Interrupt */
356 MASKABLE_EXCEPTION(0x900, decrementer, .timer_interrupt, ACK_DEC)
357
358/* Fixed Interval Timer Interrupt */
359 MASKABLE_EXCEPTION(0x980, fixed_interval, .unknown_exception, ACK_FIT)
360
361/* Watchdog Timer Interrupt */
362 START_EXCEPTION(watchdog);
363 CRIT_EXCEPTION_PROLOG(0x9f0, PROLOG_ADDITION_NONE)
364// EXCEPTION_COMMON(0x9f0, PACA_EXCRIT, INTS_DISABLE_ALL)
365// bl special_reg_save_crit
34d97e07 366// CHECK_NAPPING();
2d27cfd3
BH		 367// addi r3,r1,STACK_FRAME_OVERHEAD
368// bl .unknown_exception
369// b ret_from_crit_except
370 b .
371
372/* System Call Interrupt */
373 START_EXCEPTION(system_call)
374 mr r9,r13 /* keep a copy of userland r13 */
375 mfspr r11,SPRN_SRR0 /* get return address */
376 mfspr r12,SPRN_SRR1 /* get previous MSR */
377 mfspr r13,SPRN_SPRG_PACA /* get our PACA */
378 b system_call_common
379
25985edc 380/* Auxiliary Processor Unavailable Interrupt */
2d27cfd3
BH		 381 START_EXCEPTION(ap_unavailable);
382 NORMAL_EXCEPTION_PROLOG(0xf20, PROLOG_ADDITION_NONE)
383 EXCEPTION_COMMON(0xf20, PACA_EXGEN, INTS_KEEP)
384 addi r3,r1,STACK_FRAME_OVERHEAD
385 bl .save_nvgprs
386 INTS_RESTORE_HARD
387 bl .unknown_exception
388 b .ret_from_except
389
390/* Debug exception as a critical interrupt*/
391 START_EXCEPTION(debug_crit);
392 CRIT_EXCEPTION_PROLOG(0xd00, PROLOG_ADDITION_2REGS)
393
394 /*
395 * If there is a single step or branch-taken exception in an
396 * exception entry sequence, it was probably meant to apply to
397 * the code where the exception occurred (since exception entry
398 * doesn't turn off DE automatically). We simulate the effect
399 * of turning off DE on entry to an exception handler by turning
400 * off DE in the CSRR1 value and clearing the debug status.
401 */
402
403 mfspr r14,SPRN_DBSR /* check single-step/branch taken */
404 andis. r15,r14,DBSR_IC@h
405 beq+ 1f
406
407 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
408 LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e)
409 cmpld cr0,r10,r14
410 cmpld cr1,r10,r15
411 blt+ cr0,1f
412 bge+ cr1,1f
413
414 /* here it looks like we got an inappropriate debug exception. */
415 lis r14,DBSR_IC@h /* clear the IC event */
416 rlwinm r11,r11,0,~MSR_DE /* clear DE in the CSRR1 value */
417 mtspr SPRN_DBSR,r14
418 mtspr SPRN_CSRR1,r11
419 lwz r10,PACA_EXCRIT+EX_CR(r13) /* restore registers */
420 ld r1,PACA_EXCRIT+EX_R1(r13)
421 ld r14,PACA_EXCRIT+EX_R14(r13)
422 ld r15,PACA_EXCRIT+EX_R15(r13)
423 mtcr r10
424 ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */
425 ld r11,PACA_EXCRIT+EX_R11(r13)
426 mfspr r13,SPRN_SPRG_CRIT_SCRATCH
427 rfci
428
429 /* Normal debug exception */
430 /* XXX We only handle coming from userspace for now since we can't
431 * quite save properly an interrupted kernel state yet
432 */
4331: andi. r14,r11,MSR_PR; /* check for userspace again */
434 beq kernel_dbg_exc; /* if from kernel mode */
435
436 /* Now we mash up things to make it look like we are coming on a
437 * normal exception
438 */
439 mfspr r15,SPRN_SPRG_CRIT_SCRATCH
440 mtspr SPRN_SPRG_GEN_SCRATCH,r15
441 mfspr r14,SPRN_DBSR
442 EXCEPTION_COMMON(0xd00, PACA_EXCRIT, INTS_DISABLE_ALL)
443 std r14,_DSISR(r1)
444 addi r3,r1,STACK_FRAME_OVERHEAD
445 mr r4,r14
446 ld r14,PACA_EXCRIT+EX_R14(r13)
447 ld r15,PACA_EXCRIT+EX_R15(r13)
448 bl .save_nvgprs
449 bl .DebugException
450 b .ret_from_except
451
452kernel_dbg_exc:
453 b . /* NYI */
454
d36b4c4f
KG		 455/* Debug exception as a debug interrupt*/
456 START_EXCEPTION(debug_debug);
457 DBG_EXCEPTION_PROLOG(0xd00, PROLOG_ADDITION_2REGS)
458
459 /*
460 * If there is a single step or branch-taken exception in an
461 * exception entry sequence, it was probably meant to apply to
462 * the code where the exception occurred (since exception entry
463 * doesn't turn off DE automatically). We simulate the effect
464 * of turning off DE on entry to an exception handler by turning
465 * off DE in the DSRR1 value and clearing the debug status.
466 */
467
468 mfspr r14,SPRN_DBSR /* check single-step/branch taken */
469 andis. r15,r14,DBSR_IC@h
470 beq+ 1f
471
472 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
473 LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e)
474 cmpld cr0,r10,r14
475 cmpld cr1,r10,r15
476 blt+ cr0,1f
477 bge+ cr1,1f
478
479 /* here it looks like we got an inappropriate debug exception. */
480 lis r14,DBSR_IC@h /* clear the IC event */
481 rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */
482 mtspr SPRN_DBSR,r14
483 mtspr SPRN_DSRR1,r11
484 lwz r10,PACA_EXDBG+EX_CR(r13) /* restore registers */
485 ld r1,PACA_EXDBG+EX_R1(r13)
486 ld r14,PACA_EXDBG+EX_R14(r13)
487 ld r15,PACA_EXDBG+EX_R15(r13)
488 mtcr r10
489 ld r10,PACA_EXDBG+EX_R10(r13) /* restore registers */
490 ld r11,PACA_EXDBG+EX_R11(r13)
491 mfspr r13,SPRN_SPRG_DBG_SCRATCH
492 rfdi
493
494 /* Normal debug exception */
495 /* XXX We only handle coming from userspace for now since we can't
496 * quite save properly an interrupted kernel state yet
497 */
4981: andi. r14,r11,MSR_PR; /* check for userspace again */
499 beq kernel_dbg_exc; /* if from kernel mode */
500
501 /* Now we mash up things to make it look like we are coming on a
502 * normal exception
503 */
504 mfspr r15,SPRN_SPRG_DBG_SCRATCH
505 mtspr SPRN_SPRG_GEN_SCRATCH,r15
506 mfspr r14,SPRN_DBSR
507 EXCEPTION_COMMON(0xd00, PACA_EXDBG, INTS_DISABLE_ALL)
508 std r14,_DSISR(r1)
509 addi r3,r1,STACK_FRAME_OVERHEAD
510 mr r4,r14
511 ld r14,PACA_EXDBG+EX_R14(r13)
512 ld r15,PACA_EXDBG+EX_R15(r13)
513 bl .save_nvgprs
514 bl .DebugException
515 b .ret_from_except
516
89c81797
BH		 517/* Doorbell interrupt */
518 MASKABLE_EXCEPTION(0x2070, doorbell, .doorbell_exception, ACK_NONE)
519
520/* Doorbell critical Interrupt */
521 START_EXCEPTION(doorbell_crit);
522 CRIT_EXCEPTION_PROLOG(0x2080, PROLOG_ADDITION_NONE)
523// EXCEPTION_COMMON(0x2080, PACA_EXCRIT, INTS_DISABLE_ALL)
524// bl special_reg_save_crit
34d97e07 525// CHECK_NAPPING();
89c81797
BH		 526// addi r3,r1,STACK_FRAME_OVERHEAD
527// bl .doorbell_critical_exception
528// b ret_from_crit_except
529 b .
530
2d27cfd3
BH		 531
532/*
533 * An interrupt came in while soft-disabled; clear EE in SRR1,
534 * clear paca->hard_enabled and return.
535 */
536masked_interrupt_book3e:
537 mtcr r10
538 stb r11,PACAHARDIRQEN(r13)
539 mfspr r10,SPRN_SRR1
540 rldicl r11,r10,48,1 /* clear MSR_EE */
541 rotldi r10,r11,16
542 mtspr SPRN_SRR1,r10
543 ld r10,PACA_EXGEN+EX_R10(r13); /* restore registers */
544 ld r11,PACA_EXGEN+EX_R11(r13);
545 mfspr r13,SPRN_SPRG_GEN_SCRATCH;
546 rfi
547 b .
548
549/*
550 * This is called from 0x300 and 0x400 handlers after the prologs with
551 * r14 and r15 containing the fault address and error code, with the
552 * original values stashed away in the PACA
553 */
554storage_fault_common:
555 std r14,_DAR(r1)
556 std r15,_DSISR(r1)
557 addi r3,r1,STACK_FRAME_OVERHEAD
558 mr r4,r14
559 mr r5,r15
560 ld r14,PACA_EXGEN+EX_R14(r13)
561 ld r15,PACA_EXGEN+EX_R15(r13)
562 INTS_RESTORE_HARD
563 bl .do_page_fault
564 cmpdi r3,0
565 bne- 1f
566 b .ret_from_except_lite
5671: bl .save_nvgprs
568 mr r5,r3
569 addi r3,r1,STACK_FRAME_OVERHEAD
570 ld r4,_DAR(r1)
571 bl .bad_page_fault
572 b .ret_from_except
573
574/*
575 * Alignment exception doesn't fit entirely in the 0x100 bytes so it
576 * continues here.
577 */
578alignment_more:
579 std r14,_DAR(r1)
580 std r15,_DSISR(r1)
581 addi r3,r1,STACK_FRAME_OVERHEAD
582 ld r14,PACA_EXGEN+EX_R14(r13)
583 ld r15,PACA_EXGEN+EX_R15(r13)
584 bl .save_nvgprs
585 INTS_RESTORE_HARD
586 bl .alignment_exception
587 b .ret_from_except
588
589/*
590 * We branch here from entry_64.S for the last stage of the exception
591 * return code path. MSR:EE is expected to be off at that point
592 */
593_GLOBAL(exception_return_book3e)
594 b 1f
595
596/* This is the return from load_up_fpu fast path which could do with
597 * less GPR restores in fact, but for now we have a single return path
598 */
599 .globl fast_exception_return
600fast_exception_return:
601 wrteei 0
6021: mr r0,r13
603 ld r10,_MSR(r1)
604 REST_4GPRS(2, r1)
605 andi. r6,r10,MSR_PR
606 REST_2GPRS(6, r1)
607 beq 1f
608 ACCOUNT_CPU_USER_EXIT(r10, r11)
609 ld r0,GPR13(r1)
610
6111: stdcx. r0,0,r1 /* to clear the reservation */
612
613 ld r8,_CCR(r1)
614 ld r9,_LINK(r1)
615 ld r10,_CTR(r1)
616 ld r11,_XER(r1)
617 mtcr r8
618 mtlr r9
619 mtctr r10
620 mtxer r11
621 REST_2GPRS(8, r1)
622 ld r10,GPR10(r1)
623 ld r11,GPR11(r1)
624 ld r12,GPR12(r1)
625 mtspr SPRN_SPRG_GEN_SCRATCH,r0
626
627 std r10,PACA_EXGEN+EX_R10(r13);
628 std r11,PACA_EXGEN+EX_R11(r13);
629 ld r10,_NIP(r1)
630 ld r11,_MSR(r1)
631 ld r0,GPR0(r1)
632 ld r1,GPR1(r1)
633 mtspr SPRN_SRR0,r10
634 mtspr SPRN_SRR1,r11
635 ld r10,PACA_EXGEN+EX_R10(r13)
636 ld r11,PACA_EXGEN+EX_R11(r13)
637 mfspr r13,SPRN_SPRG_GEN_SCRATCH
638 rfi
639
640/*
641 * Trampolines used when spotting a bad kernel stack pointer in
642 * the exception entry code.
643 *
644 * TODO: move some bits like SRR0 read to trampoline, pass PACA
645 * index around, etc... to handle crit & mcheck
646 */
647BAD_STACK_TRAMPOLINE(0x000)
648BAD_STACK_TRAMPOLINE(0x100)
649BAD_STACK_TRAMPOLINE(0x200)
650BAD_STACK_TRAMPOLINE(0x300)
651BAD_STACK_TRAMPOLINE(0x400)
652BAD_STACK_TRAMPOLINE(0x500)
653BAD_STACK_TRAMPOLINE(0x600)
654BAD_STACK_TRAMPOLINE(0x700)
655BAD_STACK_TRAMPOLINE(0x800)
656BAD_STACK_TRAMPOLINE(0x900)
657BAD_STACK_TRAMPOLINE(0x980)
658BAD_STACK_TRAMPOLINE(0x9f0)
659BAD_STACK_TRAMPOLINE(0xa00)
660BAD_STACK_TRAMPOLINE(0xb00)
661BAD_STACK_TRAMPOLINE(0xc00)
662BAD_STACK_TRAMPOLINE(0xd00)
663BAD_STACK_TRAMPOLINE(0xe00)
664BAD_STACK_TRAMPOLINE(0xf00)
665BAD_STACK_TRAMPOLINE(0xf20)
89c81797
BH		 666BAD_STACK_TRAMPOLINE(0x2070)
667BAD_STACK_TRAMPOLINE(0x2080)
2d27cfd3
BH		 668
669 .globl bad_stack_book3e
670bad_stack_book3e:
671 /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */
672 mfspr r10,SPRN_SRR0; /* read SRR0 before touching stack */
673 ld r1,PACAEMERGSP(r13)
674 subi r1,r1,64+INT_FRAME_SIZE
675 std r10,_NIP(r1)
676 std r11,_MSR(r1)
677 ld r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */
678 lwz r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */
679 std r10,GPR1(r1)
680 std r11,_CCR(r1)
681 mfspr r10,SPRN_DEAR
682 mfspr r11,SPRN_ESR
683 std r10,_DAR(r1)
684 std r11,_DSISR(r1)
685 std r0,GPR0(r1); /* save r0 in stackframe */ \
686 std r2,GPR2(r1); /* save r2 in stackframe */ \
687 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
688 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
689 std r9,GPR9(r1); /* save r9 in stackframe */ \
690 ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \
691 ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \
692 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \
693 std r3,GPR10(r1); /* save r10 to stackframe */ \
694 std r4,GPR11(r1); /* save r11 to stackframe */ \
695 std r12,GPR12(r1); /* save r12 in stackframe */ \
696 std r5,GPR13(r1); /* save it to stackframe */ \
697 mflr r10
698 mfctr r11
699 mfxer r12
700 std r10,_LINK(r1)
701 std r11,_CTR(r1)
702 std r12,_XER(r1)
703 SAVE_10GPRS(14,r1)
704 SAVE_8GPRS(24,r1)
705 lhz r12,PACA_TRAP_SAVE(r13)
706 std r12,_TRAP(r1)
707 addi r11,r1,INT_FRAME_SIZE
708 std r11,0(r1)
709 li r12,0
710 std r12,0(r11)
711 ld r2,PACATOC(r13)
7121: addi r3,r1,STACK_FRAME_OVERHEAD
713 bl .kernel_bad_stack
714 b 1b
715
716/*
717 * Setup the initial TLB for a core. This current implementation
718 * assume that whatever we are running off will not conflict with
719 * the new mapping at PAGE_OFFSET.
2d27cfd3
BH		 720 */
721_GLOBAL(initial_tlb_book3e)
722
bb1af71e
KG		 723 /* Look for the first TLB with IPROT set */
724 mfspr r4,SPRN_TLB0CFG
725 andi. r3,r4,TLBnCFG_IPROT
726 lis r3,MAS0_TLBSEL(0)@h
727 bne found_iprot
728
729 mfspr r4,SPRN_TLB1CFG
730 andi. r3,r4,TLBnCFG_IPROT
731 lis r3,MAS0_TLBSEL(1)@h
732 bne found_iprot
733
734 mfspr r4,SPRN_TLB2CFG
735 andi. r3,r4,TLBnCFG_IPROT
736 lis r3,MAS0_TLBSEL(2)@h
737 bne found_iprot
738
739 lis r3,MAS0_TLBSEL(3)@h
740 mfspr r4,SPRN_TLB3CFG
741 /* fall through */
742
743found_iprot:
744 andi. r5,r4,TLBnCFG_HES
745 bne have_hes
746
747 mflr r8 /* save LR */
748/* 1. Find the index of the entry we're executing in
749 *
750 * r3 = MAS0_TLBSEL (for the iprot array)
751 * r4 = SPRN_TLBnCFG
752 */
753 bl invstr /* Find our address */
754invstr: mflr r6 /* Make it accessible */
755 mfmsr r7
756 rlwinm r5,r7,27,31,31 /* extract MSR[IS] */
757 mfspr r7,SPRN_PID
758 slwi r7,r7,16
759 or r7,r7,r5
760 mtspr SPRN_MAS6,r7
761 tlbsx 0,r6 /* search MSR[IS], SPID=PID */
762
763 mfspr r3,SPRN_MAS0
764 rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */
765
766 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
767 oris r7,r7,MAS1_IPROT@h
768 mtspr SPRN_MAS1,r7
769 tlbwe
770
771/* 2. Invalidate all entries except the entry we're executing in
772 *
773 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
774 * r4 = SPRN_TLBnCFG
775 * r5 = ESEL of entry we are running in
776 */
777 andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */
778 li r6,0 /* Set Entry counter to 0 */
7791: mr r7,r3 /* Set MAS0(TLBSEL) */
780 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
781 mtspr SPRN_MAS0,r7
782 tlbre
783 mfspr r7,SPRN_MAS1
784 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
785 cmpw r5,r6
786 beq skpinv /* Dont update the current execution TLB */
787 mtspr SPRN_MAS1,r7
788 tlbwe
789 isync
790skpinv: addi r6,r6,1 /* Increment */
791 cmpw r6,r4 /* Are we done? */
792 bne 1b /* If not, repeat */
793
794 /* Invalidate all TLBs */
795 PPC_TLBILX_ALL(0,0)
796 sync
797 isync
798
799/* 3. Setup a temp mapping and jump to it
800 *
801 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
802 * r5 = ESEL of entry we are running in
803 */
804 andi. r7,r5,0x1 /* Find an entry not used and is non-zero */
805 addi r7,r7,0x1
806 mr r4,r3 /* Set MAS0(TLBSEL) = 1 */
807 mtspr SPRN_MAS0,r4
808 tlbre
809
810 rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */
811 mtspr SPRN_MAS0,r4
812
813 mfspr r7,SPRN_MAS1
814 xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */
815 mtspr SPRN_MAS1,r6
816
817 tlbwe
818
819 mfmsr r6
820 xori r6,r6,MSR_IS
821 mtspr SPRN_SRR1,r6
822 bl 1f /* Find our address */
8231: mflr r6
824 addi r6,r6,(2f - 1b)
825 mtspr SPRN_SRR0,r6
826 rfi
8272:
828
829/* 4. Clear out PIDs & Search info
830 *
831 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
832 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
833 * r5 = MAS3
834 */
835 li r6,0
836 mtspr SPRN_MAS6,r6
837 mtspr SPRN_PID,r6
838
839/* 5. Invalidate mapping we started in
840 *
841 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
842 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
843 * r5 = MAS3
844 */
845 mtspr SPRN_MAS0,r3
846 tlbre
847 mfspr r6,SPRN_MAS1
848 rlwinm r6,r6,0,2,0 /* clear IPROT */
849 mtspr SPRN_MAS1,r6
850 tlbwe
851
852 /* Invalidate TLB1 */
853 PPC_TLBILX_ALL(0,0)
854 sync
855 isync
856
857/* The mapping only needs to be cache-coherent on SMP */
858#ifdef CONFIG_SMP
859#define M_IF_SMP MAS2_M
860#else
861#define M_IF_SMP 0
862#endif
863
864/* 6. Setup KERNELBASE mapping in TLB[0]
865 *
866 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
867 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
868 * r5 = MAS3
869 */
870 rlwinm r3,r3,0,16,3 /* clear ESEL */
871 mtspr SPRN_MAS0,r3
872 lis r6,(MAS1_VALID|MAS1_IPROT)@h
873 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
874 mtspr SPRN_MAS1,r6
875
876 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_SMP)
877 mtspr SPRN_MAS2,r6
878
879 rlwinm r5,r5,0,0,25
880 ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX
881 mtspr SPRN_MAS3,r5
882 li r5,-1
883 rlwinm r5,r5,0,0,25
884
885 tlbwe
886
887/* 7. Jump to KERNELBASE mapping
888 *
889 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
890 */
891 /* Now we branch the new virtual address mapped by this entry */
892 LOAD_REG_IMMEDIATE(r6,2f)
893 lis r7,MSR_KERNEL@h
894 ori r7,r7,MSR_KERNEL@l
895 mtspr SPRN_SRR0,r6
896 mtspr SPRN_SRR1,r7
897 rfi /* start execution out of TLB1[0] entry */
8982:
899
900/* 8. Clear out the temp mapping
901 *
902 * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in
903 */
904 mtspr SPRN_MAS0,r4
905 tlbre
906 mfspr r5,SPRN_MAS1
907 rlwinm r5,r5,0,2,0 /* clear IPROT */
908 mtspr SPRN_MAS1,r5
909 tlbwe
910
911 /* Invalidate TLB1 */
912 PPC_TLBILX_ALL(0,0)
913 sync
914 isync
915
916 /* We translate LR and return */
917 tovirt(r8,r8)
918 mtlr r8
919 blr
920
921have_hes:
2d27cfd3
BH		 922 /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the
923 * kernel linear mapping. We also set MAS8 once for all here though
924 * that will have to be made dependent on whether we are running under
925 * a hypervisor I suppose.
926 */
a1d0d98d
DG		 927
928 /* BEWARE, MAGIC
929 * This code is called as an ordinary function on the boot CPU. But to
930 * avoid duplication, this code is also used in SCOM bringup of
931 * secondary CPUs. We read the code between the initial_tlb_code_start
932 * and initial_tlb_code_end labels one instruction at a time and RAM it
933 * into the new core via SCOM. That doesn't process branches, so there
934 * must be none between those two labels. It also means if this code
935 * ever takes any parameters, the SCOM code must also be updated to
936 * provide them.
937 */
938 .globl a2_tlbinit_code_start
939a2_tlbinit_code_start:
940
1a51dde1
BH		 941 ori r11,r3,MAS0_WQ_ALLWAYS
942 oris r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */
943 mtspr SPRN_MAS0,r11
2d27cfd3
BH		 944 lis r3,(MAS1_VALID | MAS1_IPROT)@h
945 ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
946 mtspr SPRN_MAS1,r3
947 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M)
948 mtspr SPRN_MAS2,r3
949 li r3,MAS3_SR | MAS3_SW | MAS3_SX
950 mtspr SPRN_MAS7_MAS3,r3
951 li r3,0
952 mtspr SPRN_MAS8,r3
953
954 /* Write the TLB entry */
955 tlbwe
956
a1d0d98d
DG		 957 .globl a2_tlbinit_after_linear_map
958a2_tlbinit_after_linear_map:
959
2d27cfd3
BH		 960 /* Now we branch the new virtual address mapped by this entry */
961 LOAD_REG_IMMEDIATE(r3,1f)
962 mtctr r3
963 bctr
964
9651: /* We are now running at PAGE_OFFSET, clean the TLB of everything
f0aae323
JM		 966 * else (including IPROTed things left by firmware)
967 * r4 = TLBnCFG
968 * r3 = current address (more or less)
2d27cfd3 969 */
f0aae323
JM		 970
971 li r5,0
972 mtspr SPRN_MAS6,r5
973 tlbsx 0,r3
974
975 rlwinm r9,r4,0,TLBnCFG_N_ENTRY
976 rlwinm r10,r4,8,0xff
977 addi r10,r10,-1 /* Get inner loop mask */
978
979 li r3,1
980
981 mfspr r5,SPRN_MAS1
982 rlwinm r5,r5,0,(~(MAS1_VALID|MAS1_IPROT))
983
984 mfspr r6,SPRN_MAS2
985 rldicr r6,r6,0,51 /* Extract EPN */
986
987 mfspr r7,SPRN_MAS0
988 rlwinm r7,r7,0,0xffff0fff /* Clear HES and WQ */
989
990 rlwinm r8,r7,16,0xfff /* Extract ESEL */
991
9922: add r4,r3,r8
993 and r4,r4,r10
994
995 rlwimi r7,r4,16,MAS0_ESEL_MASK
996
997 mtspr SPRN_MAS0,r7
998 mtspr SPRN_MAS1,r5
999 mtspr SPRN_MAS2,r6
1000 tlbwe
1001
1002 addi r3,r3,1
1003 and. r4,r3,r10
1004
1005 bne 3f
1006 addis r6,r6,(1<<30)@h
10073:
1008 cmpw r3,r9
1009 blt 2b
1010
a1d0d98d
DG		 1011 .globl a2_tlbinit_after_iprot_flush
1012a2_tlbinit_after_iprot_flush:
1013
a0496d45
JM		 1014#ifdef CONFIG_PPC_EARLY_DEBUG_WSP
1015 /* Now establish early debug mappings if applicable */
1016 /* Restore the MAS0 we used for linear mapping load */
1017 mtspr SPRN_MAS0,r11
1018
1019 lis r3,(MAS1_VALID | MAS1_IPROT)@h
1020 ori r3,r3,(BOOK3E_PAGESZ_4K << MAS1_TSIZE_SHIFT)
1021 mtspr SPRN_MAS1,r3
1022 LOAD_REG_IMMEDIATE(r3, WSP_UART_VIRT | MAS2_I | MAS2_G)
1023 mtspr SPRN_MAS2,r3
1024 LOAD_REG_IMMEDIATE(r3, WSP_UART_PHYS | MAS3_SR | MAS3_SW)
1025 mtspr SPRN_MAS7_MAS3,r3
1026 /* re-use the MAS8 value from the linear mapping */
1027 tlbwe
1028#endif /* CONFIG_PPC_EARLY_DEBUG_WSP */
1029
2d27cfd3
BH		 1030 PPC_TLBILX(0,0,0)
1031 sync
1032 isync
1033
a1d0d98d
DG		 1034 .globl a2_tlbinit_code_end
1035a2_tlbinit_code_end:
1036
2d27cfd3
BH		 1037 /* We translate LR and return */
1038 mflr r3
1039 tovirt(r3,r3)
1040 mtlr r3
1041 blr
1042
1043/*
1044 * Main entry (boot CPU, thread 0)
1045 *
1046 * We enter here from head_64.S, possibly after the prom_init trampoline
1047 * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits
1048 * mode. Anything else is as it was left by the bootloader
1049 *
1050 * Initial requirements of this port:
1051 *
1052 * - Kernel loaded at 0 physical
1053 * - A good lump of memory mapped 0:0 by UTLB entry 0
1054 * - MSR:IS & MSR:DS set to 0
1055 *
1056 * Note that some of the above requirements will be relaxed in the future
1057 * as the kernel becomes smarter at dealing with different initial conditions
1058 * but for now you have to be careful
1059 */
1060_GLOBAL(start_initialization_book3e)
1061 mflr r28
1062
1063 /* First, we need to setup some initial TLBs to map the kernel
1064 * text, data and bss at PAGE_OFFSET. We don't have a real mode
1065 * and always use AS 0, so we just set it up to match our link
1066 * address and never use 0 based addresses.
1067 */
1068 bl .initial_tlb_book3e
1069
1070 /* Init global core bits */
1071 bl .init_core_book3e
1072
1073 /* Init per-thread bits */
1074 bl .init_thread_book3e
1075
1076 /* Return to common init code */
1077 tovirt(r28,r28)
1078 mtlr r28
1079 blr
1080
1081
1082/*
1083 * Secondary core/processor entry
1084 *
1085 * This is entered for thread 0 of a secondary core, all other threads
1086 * are expected to be stopped. It's similar to start_initialization_book3e
1087 * except that it's generally entered from the holding loop in head_64.S
1088 * after CPUs have been gathered by Open Firmware.
1089 *
1090 * We assume we are in 32 bits mode running with whatever TLB entry was
1091 * set for us by the firmware or POR engine.
1092 */
1093_GLOBAL(book3e_secondary_core_init_tlb_set)
1094 li r4,1
1095 b .generic_secondary_smp_init
1096
1097_GLOBAL(book3e_secondary_core_init)
1098 mflr r28
1099
1100 /* Do we need to setup initial TLB entry ? */
1101 cmplwi r4,0
1102 bne 2f
1103
1104 /* Setup TLB for this core */
1105 bl .initial_tlb_book3e
1106
1107 /* We can return from the above running at a different
1108 * address, so recalculate r2 (TOC)
1109 */
1110 bl .relative_toc
1111
1112 /* Init global core bits */
11132: bl .init_core_book3e
1114
1115 /* Init per-thread bits */
11163: bl .init_thread_book3e
1117
1118 /* Return to common init code at proper virtual address.
1119 *
1120 * Due to various previous assumptions, we know we entered this
1121 * function at either the final PAGE_OFFSET mapping or using a
1122 * 1:1 mapping at 0, so we don't bother doing a complicated check
1123 * here, we just ensure the return address has the right top bits.
1124 *
1125 * Note that if we ever want to be smarter about where we can be
1126 * started from, we have to be careful that by the time we reach
1127 * the code below we may already be running at a different location
1128 * than the one we were called from since initial_tlb_book3e can
1129 * have moved us already.
1130 */
1131 cmpdi cr0,r28,0
1132 blt 1f
1133 lis r3,PAGE_OFFSET@highest
1134 sldi r3,r3,32
1135 or r28,r28,r3
11361: mtlr r28
1137 blr
1138
1139_GLOBAL(book3e_secondary_thread_init)
1140 mflr r28
1141 b 3b
1142
1143_STATIC(init_core_book3e)
1144 /* Establish the interrupt vector base */
1145 LOAD_REG_IMMEDIATE(r3, interrupt_base_book3e)
1146 mtspr SPRN_IVPR,r3
1147 sync
1148 blr
1149
1150_STATIC(init_thread_book3e)
1151 lis r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h
1152 mtspr SPRN_EPCR,r3
1153
1154 /* Make sure interrupts are off */
1155 wrteei 0
1156
6c188829
KG		 1157 /* disable all timers and clear out status */
1158 li r3,0
2d27cfd3 1159 mtspr SPRN_TCR,r3
6c188829
KG		 1160 mfspr r3,SPRN_TSR
1161 mtspr SPRN_TSR,r3
2d27cfd3
BH		 1162
1163 blr
1164
4b98d9e7
KG		 1165_GLOBAL(__setup_base_ivors)
1166 SET_IVOR(0, 0x020) /* Critical Input */
1167 SET_IVOR(1, 0x000) /* Machine Check */
1168 SET_IVOR(2, 0x060) /* Data Storage */
1169 SET_IVOR(3, 0x080) /* Instruction Storage */
1170 SET_IVOR(4, 0x0a0) /* External Input */
1171 SET_IVOR(5, 0x0c0) /* Alignment */
1172 SET_IVOR(6, 0x0e0) /* Program */
1173 SET_IVOR(7, 0x100) /* FP Unavailable */
1174 SET_IVOR(8, 0x120) /* System Call */
1175 SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */
1176 SET_IVOR(10, 0x160) /* Decrementer */
1177 SET_IVOR(11, 0x180) /* Fixed Interval Timer */
1178 SET_IVOR(12, 0x1a0) /* Watchdog Timer */
1179 SET_IVOR(13, 0x1c0) /* Data TLB Error */
1180 SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
1181 SET_IVOR(15, 0x040) /* Debug */
2d27cfd3 1182
4b98d9e7 1183 sync
2d27cfd3 1184
4b98d9e7 1185 blr
Linux 6.x block layer and io_uring tree(s)