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2d27cfd3 BH |
1 | /* |
2 | * Boot code and exception vectors for Book3E processors | |
3 | * | |
4 | * Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #include <linux/threads.h> | |
13 | #include <asm/reg.h> | |
14 | #include <asm/page.h> | |
15 | #include <asm/ppc_asm.h> | |
16 | #include <asm/asm-offsets.h> | |
17 | #include <asm/cputable.h> | |
18 | #include <asm/setup.h> | |
19 | #include <asm/thread_info.h> | |
a0496d45 | 20 | #include <asm/reg_a2.h> |
2d27cfd3 BH |
21 | #include <asm/exception-64e.h> |
22 | #include <asm/bug.h> | |
23 | #include <asm/irqflags.h> | |
24 | #include <asm/ptrace.h> | |
25 | #include <asm/ppc-opcode.h> | |
26 | #include <asm/mmu.h> | |
7230c564 | 27 | #include <asm/hw_irq.h> |
fecff0f7 MC |
28 | #include <asm/kvm_asm.h> |
29 | #include <asm/kvm_booke_hv_asm.h> | |
2d27cfd3 BH |
30 | |
31 | /* XXX This will ultimately add space for a special exception save | |
32 | * structure used to save things like SRR0/SRR1, SPRGs, MAS, etc... | |
33 | * when taking special interrupts. For now we don't support that, | |
34 | * special interrupts from within a non-standard level will probably | |
35 | * blow you up | |
36 | */ | |
609af38f SW |
37 | #define SPECIAL_EXC_SRR0 0 |
38 | #define SPECIAL_EXC_SRR1 1 | |
39 | #define SPECIAL_EXC_SPRG_GEN 2 | |
40 | #define SPECIAL_EXC_SPRG_TLB 3 | |
41 | #define SPECIAL_EXC_MAS0 4 | |
42 | #define SPECIAL_EXC_MAS1 5 | |
43 | #define SPECIAL_EXC_MAS2 6 | |
44 | #define SPECIAL_EXC_MAS3 7 | |
45 | #define SPECIAL_EXC_MAS6 8 | |
46 | #define SPECIAL_EXC_MAS7 9 | |
47 | #define SPECIAL_EXC_MAS5 10 /* E.HV only */ | |
48 | #define SPECIAL_EXC_MAS8 11 /* E.HV only */ | |
49 | #define SPECIAL_EXC_IRQHAPPENED 12 | |
50 | #define SPECIAL_EXC_DEAR 13 | |
51 | #define SPECIAL_EXC_ESR 14 | |
52 | #define SPECIAL_EXC_SOFTE 15 | |
53 | #define SPECIAL_EXC_CSRR0 16 | |
54 | #define SPECIAL_EXC_CSRR1 17 | |
55 | /* must be even to keep 16-byte stack alignment */ | |
56 | #define SPECIAL_EXC_END 18 | |
57 | ||
58 | #define SPECIAL_EXC_FRAME_SIZE (INT_FRAME_SIZE + SPECIAL_EXC_END * 8) | |
59 | #define SPECIAL_EXC_FRAME_OFFS (INT_FRAME_SIZE - 288) | |
60 | ||
61 | #define SPECIAL_EXC_STORE(reg, name) \ | |
62 | std reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1) | |
63 | ||
64 | #define SPECIAL_EXC_LOAD(reg, name) \ | |
65 | ld reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1) | |
66 | ||
67 | special_reg_save: | |
68 | lbz r9,PACAIRQHAPPENED(r13) | |
69 | RECONCILE_IRQ_STATE(r3,r4) | |
2d27cfd3 | 70 | |
609af38f SW |
71 | /* |
72 | * We only need (or have stack space) to save this stuff if | |
73 | * we interrupted the kernel. | |
74 | */ | |
75 | ld r3,_MSR(r1) | |
76 | andi. r3,r3,MSR_PR | |
77 | bnelr | |
78 | ||
79 | /* Copy info into temporary exception thread info */ | |
80 | ld r11,PACAKSAVE(r13) | |
81 | CURRENT_THREAD_INFO(r11, r11) | |
82 | CURRENT_THREAD_INFO(r12, r1) | |
83 | ld r10,TI_FLAGS(r11) | |
84 | std r10,TI_FLAGS(r12) | |
85 | ld r10,TI_PREEMPT(r11) | |
86 | std r10,TI_PREEMPT(r12) | |
87 | ld r10,TI_TASK(r11) | |
88 | std r10,TI_TASK(r12) | |
89 | ||
90 | /* | |
91 | * Advance to the next TLB exception frame for handler | |
92 | * types that don't do it automatically. | |
93 | */ | |
94 | LOAD_REG_ADDR(r11,extlb_level_exc) | |
95 | lwz r12,0(r11) | |
96 | mfspr r10,SPRN_SPRG_TLB_EXFRAME | |
97 | add r10,r10,r12 | |
98 | mtspr SPRN_SPRG_TLB_EXFRAME,r10 | |
99 | ||
100 | /* | |
101 | * Save registers needed to allow nesting of certain exceptions | |
102 | * (such as TLB misses) inside special exception levels | |
103 | */ | |
104 | mfspr r10,SPRN_SRR0 | |
105 | SPECIAL_EXC_STORE(r10,SRR0) | |
106 | mfspr r10,SPRN_SRR1 | |
107 | SPECIAL_EXC_STORE(r10,SRR1) | |
108 | mfspr r10,SPRN_SPRG_GEN_SCRATCH | |
109 | SPECIAL_EXC_STORE(r10,SPRG_GEN) | |
110 | mfspr r10,SPRN_SPRG_TLB_SCRATCH | |
111 | SPECIAL_EXC_STORE(r10,SPRG_TLB) | |
112 | mfspr r10,SPRN_MAS0 | |
113 | SPECIAL_EXC_STORE(r10,MAS0) | |
114 | mfspr r10,SPRN_MAS1 | |
115 | SPECIAL_EXC_STORE(r10,MAS1) | |
116 | mfspr r10,SPRN_MAS2 | |
117 | SPECIAL_EXC_STORE(r10,MAS2) | |
118 | mfspr r10,SPRN_MAS3 | |
119 | SPECIAL_EXC_STORE(r10,MAS3) | |
120 | mfspr r10,SPRN_MAS6 | |
121 | SPECIAL_EXC_STORE(r10,MAS6) | |
122 | mfspr r10,SPRN_MAS7 | |
123 | SPECIAL_EXC_STORE(r10,MAS7) | |
124 | BEGIN_FTR_SECTION | |
125 | mfspr r10,SPRN_MAS5 | |
126 | SPECIAL_EXC_STORE(r10,MAS5) | |
127 | mfspr r10,SPRN_MAS8 | |
128 | SPECIAL_EXC_STORE(r10,MAS8) | |
129 | ||
130 | /* MAS5/8 could have inappropriate values if we interrupted KVM code */ | |
131 | li r10,0 | |
132 | mtspr SPRN_MAS5,r10 | |
133 | mtspr SPRN_MAS8,r10 | |
134 | END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) | |
135 | SPECIAL_EXC_STORE(r9,IRQHAPPENED) | |
136 | ||
137 | mfspr r10,SPRN_DEAR | |
138 | SPECIAL_EXC_STORE(r10,DEAR) | |
139 | mfspr r10,SPRN_ESR | |
140 | SPECIAL_EXC_STORE(r10,ESR) | |
141 | ||
142 | lbz r10,PACASOFTIRQEN(r13) | |
143 | SPECIAL_EXC_STORE(r10,SOFTE) | |
144 | ld r10,_NIP(r1) | |
145 | SPECIAL_EXC_STORE(r10,CSRR0) | |
146 | ld r10,_MSR(r1) | |
147 | SPECIAL_EXC_STORE(r10,CSRR1) | |
148 | ||
149 | blr | |
150 | ||
151 | ret_from_level_except: | |
152 | ld r3,_MSR(r1) | |
153 | andi. r3,r3,MSR_PR | |
154 | beq 1f | |
155 | b ret_from_except | |
156 | 1: | |
157 | ||
158 | LOAD_REG_ADDR(r11,extlb_level_exc) | |
159 | lwz r12,0(r11) | |
160 | mfspr r10,SPRN_SPRG_TLB_EXFRAME | |
161 | sub r10,r10,r12 | |
162 | mtspr SPRN_SPRG_TLB_EXFRAME,r10 | |
163 | ||
164 | /* | |
165 | * It's possible that the special level exception interrupted a | |
166 | * TLB miss handler, and inserted the same entry that the | |
167 | * interrupted handler was about to insert. On CPUs without TLB | |
168 | * write conditional, this can result in a duplicate TLB entry. | |
169 | * Wipe all non-bolted entries to be safe. | |
170 | * | |
171 | * Note that this doesn't protect against any TLB misses | |
172 | * we may take accessing the stack from here to the end of | |
173 | * the special level exception. It's not clear how we can | |
174 | * reasonably protect against that, but only CPUs with | |
175 | * neither TLB write conditional nor bolted kernel memory | |
176 | * are affected. Do any such CPUs even exist? | |
177 | */ | |
178 | PPC_TLBILX_ALL(0,R0) | |
179 | ||
180 | REST_NVGPRS(r1) | |
181 | ||
182 | SPECIAL_EXC_LOAD(r10,SRR0) | |
183 | mtspr SPRN_SRR0,r10 | |
184 | SPECIAL_EXC_LOAD(r10,SRR1) | |
185 | mtspr SPRN_SRR1,r10 | |
186 | SPECIAL_EXC_LOAD(r10,SPRG_GEN) | |
187 | mtspr SPRN_SPRG_GEN_SCRATCH,r10 | |
188 | SPECIAL_EXC_LOAD(r10,SPRG_TLB) | |
189 | mtspr SPRN_SPRG_TLB_SCRATCH,r10 | |
190 | SPECIAL_EXC_LOAD(r10,MAS0) | |
191 | mtspr SPRN_MAS0,r10 | |
192 | SPECIAL_EXC_LOAD(r10,MAS1) | |
193 | mtspr SPRN_MAS1,r10 | |
194 | SPECIAL_EXC_LOAD(r10,MAS2) | |
195 | mtspr SPRN_MAS2,r10 | |
196 | SPECIAL_EXC_LOAD(r10,MAS3) | |
197 | mtspr SPRN_MAS3,r10 | |
198 | SPECIAL_EXC_LOAD(r10,MAS6) | |
199 | mtspr SPRN_MAS6,r10 | |
200 | SPECIAL_EXC_LOAD(r10,MAS7) | |
201 | mtspr SPRN_MAS7,r10 | |
202 | BEGIN_FTR_SECTION | |
203 | SPECIAL_EXC_LOAD(r10,MAS5) | |
204 | mtspr SPRN_MAS5,r10 | |
205 | SPECIAL_EXC_LOAD(r10,MAS8) | |
206 | mtspr SPRN_MAS8,r10 | |
207 | END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) | |
208 | ||
209 | lbz r6,PACASOFTIRQEN(r13) | |
210 | ld r5,SOFTE(r1) | |
211 | ||
212 | /* Interrupts had better not already be enabled... */ | |
213 | twnei r6,0 | |
214 | ||
215 | cmpwi cr0,r5,0 | |
216 | beq 1f | |
217 | ||
218 | TRACE_ENABLE_INTS | |
219 | stb r5,PACASOFTIRQEN(r13) | |
220 | 1: | |
221 | /* | |
222 | * Restore PACAIRQHAPPENED rather than setting it based on | |
223 | * the return MSR[EE], since we could have interrupted | |
224 | * __check_irq_replay() or other inconsistent transitory | |
225 | * states that must remain that way. | |
226 | */ | |
227 | SPECIAL_EXC_LOAD(r10,IRQHAPPENED) | |
228 | stb r10,PACAIRQHAPPENED(r13) | |
229 | ||
230 | SPECIAL_EXC_LOAD(r10,DEAR) | |
231 | mtspr SPRN_DEAR,r10 | |
232 | SPECIAL_EXC_LOAD(r10,ESR) | |
233 | mtspr SPRN_ESR,r10 | |
234 | ||
235 | stdcx. r0,0,r1 /* to clear the reservation */ | |
236 | ||
237 | REST_4GPRS(2, r1) | |
238 | REST_4GPRS(6, r1) | |
239 | ||
240 | ld r10,_CTR(r1) | |
241 | ld r11,_XER(r1) | |
242 | mtctr r10 | |
243 | mtxer r11 | |
244 | ||
245 | blr | |
246 | ||
247 | .macro ret_from_level srr0 srr1 paca_ex scratch | |
248 | bl ret_from_level_except | |
249 | ||
250 | ld r10,_LINK(r1) | |
251 | ld r11,_CCR(r1) | |
252 | ld r0,GPR13(r1) | |
253 | mtlr r10 | |
254 | mtcr r11 | |
255 | ||
256 | ld r10,GPR10(r1) | |
257 | ld r11,GPR11(r1) | |
258 | ld r12,GPR12(r1) | |
259 | mtspr \scratch,r0 | |
260 | ||
261 | std r10,\paca_ex+EX_R10(r13); | |
262 | std r11,\paca_ex+EX_R11(r13); | |
263 | ld r10,_NIP(r1) | |
264 | ld r11,_MSR(r1) | |
265 | ld r0,GPR0(r1) | |
266 | ld r1,GPR1(r1) | |
267 | mtspr \srr0,r10 | |
268 | mtspr \srr1,r11 | |
269 | ld r10,\paca_ex+EX_R10(r13) | |
270 | ld r11,\paca_ex+EX_R11(r13) | |
271 | mfspr r13,\scratch | |
272 | .endm | |
273 | ||
274 | ret_from_crit_except: | |
275 | ret_from_level SPRN_CSRR0 SPRN_CSRR1 PACA_EXCRIT SPRN_SPRG_CRIT_SCRATCH | |
276 | rfci | |
19007b34 | 277 | |
609af38f SW |
278 | ret_from_mc_except: |
279 | ret_from_level SPRN_MCSRR0 SPRN_MCSRR1 PACA_EXMC SPRN_SPRG_MC_SCRATCH | |
280 | rfmci | |
19007b34 | 281 | |
2d27cfd3 | 282 | /* Exception prolog code for all exceptions */ |
fecff0f7 | 283 | #define EXCEPTION_PROLOG(n, intnum, type, addition) \ |
2d27cfd3 BH |
284 | mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \ |
285 | mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \ | |
286 | std r10,PACA_EX##type+EX_R10(r13); \ | |
287 | std r11,PACA_EX##type+EX_R11(r13); \ | |
288 | mfcr r10; /* save CR */ \ | |
fecff0f7 MC |
289 | mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \ |
290 | DO_KVM intnum,SPRN_##type##_SRR1; /* KVM hook */ \ | |
79b5c8db | 291 | stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \ |
2d27cfd3 BH |
292 | addition; /* additional code for that exc. */ \ |
293 | std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \ | |
2d27cfd3 BH |
294 | type##_SET_KSTACK; /* get special stack if necessary */\ |
295 | andi. r10,r11,MSR_PR; /* save stack pointer */ \ | |
296 | beq 1f; /* branch around if supervisor */ \ | |
297 | ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\ | |
298 | 1: cmpdi cr1,r1,0; /* check if SP makes sense */ \ | |
299 | bge- cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \ | |
300 | mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */ | |
301 | ||
302 | /* Exception type-specific macros */ | |
303 | #define GEN_SET_KSTACK \ | |
304 | subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ | |
305 | #define SPRN_GEN_SRR0 SPRN_SRR0 | |
306 | #define SPRN_GEN_SRR1 SPRN_SRR1 | |
307 | ||
5473eb1c MC |
308 | #define GDBELL_SET_KSTACK GEN_SET_KSTACK |
309 | #define SPRN_GDBELL_SRR0 SPRN_GSRR0 | |
310 | #define SPRN_GDBELL_SRR1 SPRN_GSRR1 | |
311 | ||
2d27cfd3 BH |
312 | #define CRIT_SET_KSTACK \ |
313 | ld r1,PACA_CRIT_STACK(r13); \ | |
609af38f | 314 | subi r1,r1,SPECIAL_EXC_FRAME_SIZE |
2d27cfd3 BH |
315 | #define SPRN_CRIT_SRR0 SPRN_CSRR0 |
316 | #define SPRN_CRIT_SRR1 SPRN_CSRR1 | |
317 | ||
318 | #define DBG_SET_KSTACK \ | |
319 | ld r1,PACA_DBG_STACK(r13); \ | |
609af38f | 320 | subi r1,r1,SPECIAL_EXC_FRAME_SIZE |
2d27cfd3 BH |
321 | #define SPRN_DBG_SRR0 SPRN_DSRR0 |
322 | #define SPRN_DBG_SRR1 SPRN_DSRR1 | |
323 | ||
324 | #define MC_SET_KSTACK \ | |
325 | ld r1,PACA_MC_STACK(r13); \ | |
609af38f | 326 | subi r1,r1,SPECIAL_EXC_FRAME_SIZE |
2d27cfd3 BH |
327 | #define SPRN_MC_SRR0 SPRN_MCSRR0 |
328 | #define SPRN_MC_SRR1 SPRN_MCSRR1 | |
329 | ||
fecff0f7 MC |
330 | #define NORMAL_EXCEPTION_PROLOG(n, intnum, addition) \ |
331 | EXCEPTION_PROLOG(n, intnum, GEN, addition##_GEN(n)) | |
2d27cfd3 | 332 | |
fecff0f7 MC |
333 | #define CRIT_EXCEPTION_PROLOG(n, intnum, addition) \ |
334 | EXCEPTION_PROLOG(n, intnum, CRIT, addition##_CRIT(n)) | |
2d27cfd3 | 335 | |
fecff0f7 MC |
336 | #define DBG_EXCEPTION_PROLOG(n, intnum, addition) \ |
337 | EXCEPTION_PROLOG(n, intnum, DBG, addition##_DBG(n)) | |
2d27cfd3 | 338 | |
fecff0f7 MC |
339 | #define MC_EXCEPTION_PROLOG(n, intnum, addition) \ |
340 | EXCEPTION_PROLOG(n, intnum, MC, addition##_MC(n)) | |
2d27cfd3 | 341 | |
fecff0f7 MC |
342 | #define GDBELL_EXCEPTION_PROLOG(n, intnum, addition) \ |
343 | EXCEPTION_PROLOG(n, intnum, GDBELL, addition##_GDBELL(n)) | |
2d27cfd3 BH |
344 | |
345 | /* Variants of the "addition" argument for the prolog | |
346 | */ | |
7230c564 | 347 | #define PROLOG_ADDITION_NONE_GEN(n) |
5473eb1c | 348 | #define PROLOG_ADDITION_NONE_GDBELL(n) |
7230c564 BH |
349 | #define PROLOG_ADDITION_NONE_CRIT(n) |
350 | #define PROLOG_ADDITION_NONE_DBG(n) | |
351 | #define PROLOG_ADDITION_NONE_MC(n) | |
2d27cfd3 | 352 | |
7230c564 | 353 | #define PROLOG_ADDITION_MASKABLE_GEN(n) \ |
79b5c8db MC |
354 | lbz r10,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \ |
355 | cmpwi cr0,r10,0; /* yes -> go out of line */ \ | |
7230c564 | 356 | beq masked_interrupt_book3e_##n |
2d27cfd3 | 357 | |
7230c564 | 358 | #define PROLOG_ADDITION_2REGS_GEN(n) \ |
2d27cfd3 BH |
359 | std r14,PACA_EXGEN+EX_R14(r13); \ |
360 | std r15,PACA_EXGEN+EX_R15(r13) | |
361 | ||
7230c564 | 362 | #define PROLOG_ADDITION_1REG_GEN(n) \ |
2d27cfd3 BH |
363 | std r14,PACA_EXGEN+EX_R14(r13); |
364 | ||
7230c564 | 365 | #define PROLOG_ADDITION_2REGS_CRIT(n) \ |
2d27cfd3 BH |
366 | std r14,PACA_EXCRIT+EX_R14(r13); \ |
367 | std r15,PACA_EXCRIT+EX_R15(r13) | |
368 | ||
7230c564 | 369 | #define PROLOG_ADDITION_2REGS_DBG(n) \ |
2d27cfd3 BH |
370 | std r14,PACA_EXDBG+EX_R14(r13); \ |
371 | std r15,PACA_EXDBG+EX_R15(r13) | |
372 | ||
7230c564 | 373 | #define PROLOG_ADDITION_2REGS_MC(n) \ |
2d27cfd3 BH |
374 | std r14,PACA_EXMC+EX_R14(r13); \ |
375 | std r15,PACA_EXMC+EX_R15(r13) | |
376 | ||
3d97a619 | 377 | |
31f71248 SW |
378 | /* Core exception code for all exceptions except TLB misses. */ |
379 | #define EXCEPTION_COMMON_LVL(n, scratch, excf) \ | |
7230c564 | 380 | exc_##n##_common: \ |
2d27cfd3 BH |
381 | std r0,GPR0(r1); /* save r0 in stackframe */ \ |
382 | std r2,GPR2(r1); /* save r2 in stackframe */ \ | |
383 | SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ | |
384 | SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ | |
385 | std r9,GPR9(r1); /* save r9 in stackframe */ \ | |
386 | std r10,_NIP(r1); /* save SRR0 to stackframe */ \ | |
387 | std r11,_MSR(r1); /* save SRR1 to stackframe */ \ | |
5d75b264 | 388 | beq 2f; /* if from kernel mode */ \ |
2d27cfd3 | 389 | ACCOUNT_CPU_USER_ENTRY(r10,r11);/* accounting (uses cr0+eq) */ \ |
5d75b264 | 390 | 2: ld r3,excf+EX_R10(r13); /* get back r10 */ \ |
2d27cfd3 | 391 | ld r4,excf+EX_R11(r13); /* get back r11 */ \ |
31f71248 | 392 | mfspr r5,scratch; /* get back r13 */ \ |
2d27cfd3 BH |
393 | std r12,GPR12(r1); /* save r12 in stackframe */ \ |
394 | ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ | |
395 | mflr r6; /* save LR in stackframe */ \ | |
396 | mfctr r7; /* save CTR in stackframe */ \ | |
397 | mfspr r8,SPRN_XER; /* save XER in stackframe */ \ | |
398 | ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \ | |
399 | lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \ | |
400 | lbz r11,PACASOFTIRQEN(r13); /* get current IRQ softe */ \ | |
401 | ld r12,exception_marker@toc(r2); \ | |
402 | li r0,0; \ | |
403 | std r3,GPR10(r1); /* save r10 to stackframe */ \ | |
404 | std r4,GPR11(r1); /* save r11 to stackframe */ \ | |
405 | std r5,GPR13(r1); /* save it to stackframe */ \ | |
406 | std r6,_LINK(r1); \ | |
407 | std r7,_CTR(r1); \ | |
408 | std r8,_XER(r1); \ | |
409 | li r3,(n)+1; /* indicate partial regs in trap */ \ | |
410 | std r9,0(r1); /* store stack frame back link */ \ | |
411 | std r10,_CCR(r1); /* store orig CR in stackframe */ \ | |
412 | std r9,GPR1(r1); /* store stack frame back link */ \ | |
413 | std r11,SOFTE(r1); /* and save it to stackframe */ \ | |
414 | std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \ | |
415 | std r3,_TRAP(r1); /* set trap number */ \ | |
28a3ded1 | 416 | std r0,RESULT(r1); /* clear regs->result */ |
2d27cfd3 | 417 | |
31f71248 SW |
418 | #define EXCEPTION_COMMON(n) \ |
419 | EXCEPTION_COMMON_LVL(n, SPRN_SPRG_GEN_SCRATCH, PACA_EXGEN) | |
420 | #define EXCEPTION_COMMON_CRIT(n) \ | |
421 | EXCEPTION_COMMON_LVL(n, SPRN_SPRG_CRIT_SCRATCH, PACA_EXCRIT) | |
422 | #define EXCEPTION_COMMON_MC(n) \ | |
423 | EXCEPTION_COMMON_LVL(n, SPRN_SPRG_MC_SCRATCH, PACA_EXMC) | |
424 | #define EXCEPTION_COMMON_DBG(n) \ | |
425 | EXCEPTION_COMMON_LVL(n, SPRN_SPRG_DBG_SCRATCH, PACA_EXDBG) | |
426 | ||
28a3ded1 SW |
427 | /* |
428 | * This is meant for exceptions that don't immediately hard-enable. We | |
429 | * set a bit in paca->irq_happened to ensure that a subsequent call to | |
430 | * arch_local_irq_restore() will properly hard-enable and avoid the | |
431 | * fast-path, and then reconcile irq state. | |
7230c564 | 432 | */ |
de021bb7 | 433 | #define INTS_DISABLE RECONCILE_IRQ_STATE(r3,r4) |
7230c564 | 434 | |
28a3ded1 SW |
435 | /* |
436 | * This is called by exceptions that don't use INTS_DISABLE (that did not | |
437 | * touch irq indicators in the PACA). This will restore MSR:EE to it's | |
438 | * previous value | |
2d27cfd3 BH |
439 | * |
440 | * XXX In the long run, we may want to open-code it in order to separate the | |
441 | * load from the wrtee, thus limiting the latency caused by the dependency | |
442 | * but at this point, I'll favor code clarity until we have a near to final | |
443 | * implementation | |
444 | */ | |
445 | #define INTS_RESTORE_HARD \ | |
446 | ld r11,_MSR(r1); \ | |
447 | wrtee r11; | |
448 | ||
449 | /* XXX FIXME: Restore r14/r15 when necessary */ | |
450 | #define BAD_STACK_TRAMPOLINE(n) \ | |
451 | exc_##n##_bad_stack: \ | |
452 | li r1,(n); /* get exception number */ \ | |
453 | sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \ | |
454 | b bad_stack_book3e; /* bad stack error */ | |
455 | ||
ff82c319 BH |
456 | /* WARNING: If you change the layout of this stub, make sure you chcek |
457 | * the debug exception handler which handles single stepping | |
458 | * into exceptions from userspace, and the MM code in | |
459 | * arch/powerpc/mm/tlb_nohash.c which patches the branch here | |
460 | * and would need to be updated if that branch is moved | |
461 | */ | |
2d27cfd3 BH |
462 | #define EXCEPTION_STUB(loc, label) \ |
463 | . = interrupt_base_book3e + loc; \ | |
464 | nop; /* To make debug interrupts happy */ \ | |
465 | b exc_##label##_book3e; | |
466 | ||
467 | #define ACK_NONE(r) | |
468 | #define ACK_DEC(r) \ | |
469 | lis r,TSR_DIS@h; \ | |
470 | mtspr SPRN_TSR,r | |
471 | #define ACK_FIT(r) \ | |
472 | lis r,TSR_FIS@h; \ | |
473 | mtspr SPRN_TSR,r | |
474 | ||
34d97e07 BH |
475 | /* Used by asynchronous interrupt that may happen in the idle loop. |
476 | * | |
477 | * This check if the thread was in the idle loop, and if yes, returns | |
478 | * to the caller rather than the PC. This is to avoid a race if | |
479 | * interrupts happen before the wait instruction. | |
480 | */ | |
481 | #define CHECK_NAPPING() \ | |
9778b696 | 482 | CURRENT_THREAD_INFO(r11, r1); \ |
34d97e07 BH |
483 | ld r10,TI_LOCAL_FLAGS(r11); \ |
484 | andi. r9,r10,_TLF_NAPPING; \ | |
485 | beq+ 1f; \ | |
486 | ld r8,_LINK(r1); \ | |
487 | rlwinm r7,r10,0,~_TLF_NAPPING; \ | |
488 | std r8,_NIP(r1); \ | |
489 | std r7,TI_LOCAL_FLAGS(r11); \ | |
490 | 1: | |
491 | ||
492 | ||
fecff0f7 | 493 | #define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack) \ |
2d27cfd3 | 494 | START_EXCEPTION(label); \ |
fecff0f7 | 495 | NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\ |
31f71248 | 496 | EXCEPTION_COMMON(trapnum) \ |
28a3ded1 | 497 | INTS_DISABLE; \ |
2d27cfd3 | 498 | ack(r8); \ |
34d97e07 | 499 | CHECK_NAPPING(); \ |
2d27cfd3 BH |
500 | addi r3,r1,STACK_FRAME_OVERHEAD; \ |
501 | bl hdlr; \ | |
b1576fec | 502 | b ret_from_except_lite; |
2d27cfd3 BH |
503 | |
504 | /* This value is used to mark exception frames on the stack. */ | |
505 | .section ".toc","aw" | |
506 | exception_marker: | |
507 | .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER | |
508 | ||
509 | ||
510 | /* | |
511 | * And here we have the exception vectors ! | |
512 | */ | |
513 | ||
514 | .text | |
515 | .balign 0x1000 | |
516 | .globl interrupt_base_book3e | |
517 | interrupt_base_book3e: /* fake trap */ | |
c4787d1e SW |
518 | EXCEPTION_STUB(0x000, machine_check) |
519 | EXCEPTION_STUB(0x020, critical_input) /* 0x0100 */ | |
2d27cfd3 BH |
520 | EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */ |
521 | EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */ | |
522 | EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */ | |
523 | EXCEPTION_STUB(0x0a0, external_input) /* 0x0500 */ | |
524 | EXCEPTION_STUB(0x0c0, alignment) /* 0x0600 */ | |
525 | EXCEPTION_STUB(0x0e0, program) /* 0x0700 */ | |
526 | EXCEPTION_STUB(0x100, fp_unavailable) /* 0x0800 */ | |
527 | EXCEPTION_STUB(0x120, system_call) /* 0x0c00 */ | |
528 | EXCEPTION_STUB(0x140, ap_unavailable) /* 0x0f20 */ | |
529 | EXCEPTION_STUB(0x160, decrementer) /* 0x0900 */ | |
530 | EXCEPTION_STUB(0x180, fixed_interval) /* 0x0980 */ | |
531 | EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */ | |
532 | EXCEPTION_STUB(0x1c0, data_tlb_miss) | |
533 | EXCEPTION_STUB(0x1e0, instruction_tlb_miss) | |
c4787d1e SW |
534 | EXCEPTION_STUB(0x200, altivec_unavailable) |
535 | EXCEPTION_STUB(0x220, altivec_assist) | |
3a6e9bd7 | 536 | EXCEPTION_STUB(0x260, perfmon) |
89c81797 BH |
537 | EXCEPTION_STUB(0x280, doorbell) |
538 | EXCEPTION_STUB(0x2a0, doorbell_crit) | |
3a6e9bd7 SW |
539 | EXCEPTION_STUB(0x2c0, guest_doorbell) |
540 | EXCEPTION_STUB(0x2e0, guest_doorbell_crit) | |
541 | EXCEPTION_STUB(0x300, hypercall) | |
542 | EXCEPTION_STUB(0x320, ehpriv) | |
228b1a47 | 543 | EXCEPTION_STUB(0x340, lrat_error) |
2d27cfd3 | 544 | |
68d10140 TC |
545 | .globl __end_interrupts |
546 | __end_interrupts: | |
2d27cfd3 BH |
547 | |
548 | /* Critical Input Interrupt */ | |
549 | START_EXCEPTION(critical_input); | |
fecff0f7 MC |
550 | CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL, |
551 | PROLOG_ADDITION_NONE) | |
609af38f | 552 | EXCEPTION_COMMON_CRIT(0x100) |
b1576fec | 553 | bl save_nvgprs |
609af38f SW |
554 | bl special_reg_save |
555 | CHECK_NAPPING(); | |
556 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec | 557 | bl unknown_exception |
609af38f | 558 | b ret_from_crit_except |
2d27cfd3 BH |
559 | |
560 | /* Machine Check Interrupt */ | |
561 | START_EXCEPTION(machine_check); | |
c4787d1e | 562 | MC_EXCEPTION_PROLOG(0x000, BOOKE_INTERRUPT_MACHINE_CHECK, |
fecff0f7 | 563 | PROLOG_ADDITION_NONE) |
609af38f | 564 | EXCEPTION_COMMON_MC(0x000) |
b1576fec | 565 | bl save_nvgprs |
609af38f SW |
566 | bl special_reg_save |
567 | CHECK_NAPPING(); | |
568 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec | 569 | bl machine_check_exception |
609af38f | 570 | b ret_from_mc_except |
2d27cfd3 BH |
571 | |
572 | /* Data Storage Interrupt */ | |
573 | START_EXCEPTION(data_storage) | |
fecff0f7 MC |
574 | NORMAL_EXCEPTION_PROLOG(0x300, BOOKE_INTERRUPT_DATA_STORAGE, |
575 | PROLOG_ADDITION_2REGS) | |
2d27cfd3 BH |
576 | mfspr r14,SPRN_DEAR |
577 | mfspr r15,SPRN_ESR | |
31f71248 | 578 | EXCEPTION_COMMON(0x300) |
28a3ded1 | 579 | INTS_DISABLE |
2d27cfd3 BH |
580 | b storage_fault_common |
581 | ||
582 | /* Instruction Storage Interrupt */ | |
583 | START_EXCEPTION(instruction_storage); | |
fecff0f7 MC |
584 | NORMAL_EXCEPTION_PROLOG(0x400, BOOKE_INTERRUPT_INST_STORAGE, |
585 | PROLOG_ADDITION_2REGS) | |
2d27cfd3 BH |
586 | li r15,0 |
587 | mr r14,r10 | |
31f71248 | 588 | EXCEPTION_COMMON(0x400) |
28a3ded1 | 589 | INTS_DISABLE |
2d27cfd3 BH |
590 | b storage_fault_common |
591 | ||
592 | /* External Input Interrupt */ | |
fecff0f7 | 593 | MASKABLE_EXCEPTION(0x500, BOOKE_INTERRUPT_EXTERNAL, |
35425501 | 594 | external_input, do_IRQ, ACK_NONE) |
2d27cfd3 BH |
595 | |
596 | /* Alignment */ | |
597 | START_EXCEPTION(alignment); | |
fecff0f7 MC |
598 | NORMAL_EXCEPTION_PROLOG(0x600, BOOKE_INTERRUPT_ALIGNMENT, |
599 | PROLOG_ADDITION_2REGS) | |
2d27cfd3 BH |
600 | mfspr r14,SPRN_DEAR |
601 | mfspr r15,SPRN_ESR | |
31f71248 | 602 | EXCEPTION_COMMON(0x600) |
2d27cfd3 BH |
603 | b alignment_more /* no room, go out of line */ |
604 | ||
605 | /* Program Interrupt */ | |
606 | START_EXCEPTION(program); | |
fecff0f7 MC |
607 | NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM, |
608 | PROLOG_ADDITION_1REG) | |
2d27cfd3 | 609 | mfspr r14,SPRN_ESR |
31f71248 | 610 | EXCEPTION_COMMON(0x700) |
28a3ded1 | 611 | INTS_DISABLE |
2d27cfd3 BH |
612 | std r14,_DSISR(r1) |
613 | addi r3,r1,STACK_FRAME_OVERHEAD | |
614 | ld r14,PACA_EXGEN+EX_R14(r13) | |
b1576fec AB |
615 | bl save_nvgprs |
616 | bl program_check_exception | |
617 | b ret_from_except | |
2d27cfd3 BH |
618 | |
619 | /* Floating Point Unavailable Interrupt */ | |
620 | START_EXCEPTION(fp_unavailable); | |
fecff0f7 MC |
621 | NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL, |
622 | PROLOG_ADDITION_NONE) | |
2d27cfd3 | 623 | /* we can probably do a shorter exception entry for that one... */ |
31f71248 | 624 | EXCEPTION_COMMON(0x800) |
9424fabf BH |
625 | ld r12,_MSR(r1) |
626 | andi. r0,r12,MSR_PR; | |
627 | beq- 1f | |
b1576fec | 628 | bl load_up_fpu |
9424fabf | 629 | b fast_exception_return |
7230c564 | 630 | 1: INTS_DISABLE |
b1576fec | 631 | bl save_nvgprs |
2d27cfd3 | 632 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
633 | bl kernel_fp_unavailable_exception |
634 | b ret_from_except | |
2d27cfd3 | 635 | |
cd66cc2e KG |
636 | /* Altivec Unavailable Interrupt */ |
637 | START_EXCEPTION(altivec_unavailable); | |
2b2695a8 | 638 | NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_ALTIVEC_UNAVAIL, |
cd66cc2e KG |
639 | PROLOG_ADDITION_NONE) |
640 | /* we can probably do a shorter exception entry for that one... */ | |
31f71248 | 641 | EXCEPTION_COMMON(0x200) |
cd66cc2e KG |
642 | #ifdef CONFIG_ALTIVEC |
643 | BEGIN_FTR_SECTION | |
644 | ld r12,_MSR(r1) | |
645 | andi. r0,r12,MSR_PR; | |
646 | beq- 1f | |
b1576fec | 647 | bl load_up_altivec |
cd66cc2e KG |
648 | b fast_exception_return |
649 | 1: | |
650 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
651 | #endif | |
652 | INTS_DISABLE | |
b1576fec | 653 | bl save_nvgprs |
cd66cc2e | 654 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
655 | bl altivec_unavailable_exception |
656 | b ret_from_except | |
cd66cc2e KG |
657 | |
658 | /* AltiVec Assist */ | |
659 | START_EXCEPTION(altivec_assist); | |
6b310fc5 | 660 | NORMAL_EXCEPTION_PROLOG(0x220, |
2b2695a8 | 661 | BOOKE_INTERRUPT_ALTIVEC_ASSIST, |
cd66cc2e | 662 | PROLOG_ADDITION_NONE) |
31f71248 | 663 | EXCEPTION_COMMON(0x220) |
28a3ded1 | 664 | INTS_DISABLE |
b1576fec | 665 | bl save_nvgprs |
cd66cc2e KG |
666 | addi r3,r1,STACK_FRAME_OVERHEAD |
667 | #ifdef CONFIG_ALTIVEC | |
668 | BEGIN_FTR_SECTION | |
b1576fec | 669 | bl altivec_assist_exception |
cd66cc2e KG |
670 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) |
671 | #else | |
b1576fec | 672 | bl unknown_exception |
cd66cc2e | 673 | #endif |
b1576fec | 674 | b ret_from_except |
cd66cc2e KG |
675 | |
676 | ||
2d27cfd3 | 677 | /* Decrementer Interrupt */ |
fecff0f7 | 678 | MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER, |
35425501 | 679 | decrementer, timer_interrupt, ACK_DEC) |
2d27cfd3 BH |
680 | |
681 | /* Fixed Interval Timer Interrupt */ | |
fecff0f7 | 682 | MASKABLE_EXCEPTION(0x980, BOOKE_INTERRUPT_FIT, |
35425501 | 683 | fixed_interval, unknown_exception, ACK_FIT) |
2d27cfd3 BH |
684 | |
685 | /* Watchdog Timer Interrupt */ | |
686 | START_EXCEPTION(watchdog); | |
fecff0f7 MC |
687 | CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG, |
688 | PROLOG_ADDITION_NONE) | |
609af38f | 689 | EXCEPTION_COMMON_CRIT(0x9f0) |
b1576fec | 690 | bl save_nvgprs |
609af38f SW |
691 | bl special_reg_save |
692 | CHECK_NAPPING(); | |
693 | addi r3,r1,STACK_FRAME_OVERHEAD | |
694 | #ifdef CONFIG_BOOKE_WDT | |
b1576fec | 695 | bl WatchdogException |
609af38f | 696 | #else |
b1576fec | 697 | bl unknown_exception |
609af38f SW |
698 | #endif |
699 | b ret_from_crit_except | |
2d27cfd3 BH |
700 | |
701 | /* System Call Interrupt */ | |
702 | START_EXCEPTION(system_call) | |
703 | mr r9,r13 /* keep a copy of userland r13 */ | |
704 | mfspr r11,SPRN_SRR0 /* get return address */ | |
705 | mfspr r12,SPRN_SRR1 /* get previous MSR */ | |
706 | mfspr r13,SPRN_SPRG_PACA /* get our PACA */ | |
707 | b system_call_common | |
708 | ||
25985edc | 709 | /* Auxiliary Processor Unavailable Interrupt */ |
2d27cfd3 | 710 | START_EXCEPTION(ap_unavailable); |
fecff0f7 MC |
711 | NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL, |
712 | PROLOG_ADDITION_NONE) | |
31f71248 | 713 | EXCEPTION_COMMON(0xf20) |
28a3ded1 | 714 | INTS_DISABLE |
b1576fec | 715 | bl save_nvgprs |
9f2f79e3 | 716 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
717 | bl unknown_exception |
718 | b ret_from_except | |
2d27cfd3 BH |
719 | |
720 | /* Debug exception as a critical interrupt*/ | |
721 | START_EXCEPTION(debug_crit); | |
fecff0f7 MC |
722 | CRIT_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG, |
723 | PROLOG_ADDITION_2REGS) | |
2d27cfd3 BH |
724 | |
725 | /* | |
726 | * If there is a single step or branch-taken exception in an | |
727 | * exception entry sequence, it was probably meant to apply to | |
728 | * the code where the exception occurred (since exception entry | |
729 | * doesn't turn off DE automatically). We simulate the effect | |
730 | * of turning off DE on entry to an exception handler by turning | |
731 | * off DE in the CSRR1 value and clearing the debug status. | |
732 | */ | |
733 | ||
734 | mfspr r14,SPRN_DBSR /* check single-step/branch taken */ | |
6cecf76b | 735 | andis. r15,r14,(DBSR_IC|DBSR_BT)@h |
2d27cfd3 BH |
736 | beq+ 1f |
737 | ||
738 | LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e) | |
68d10140 | 739 | LOAD_REG_IMMEDIATE(r15,__end_interrupts) |
2d27cfd3 BH |
740 | cmpld cr0,r10,r14 |
741 | cmpld cr1,r10,r15 | |
742 | blt+ cr0,1f | |
743 | bge+ cr1,1f | |
744 | ||
745 | /* here it looks like we got an inappropriate debug exception. */ | |
6cecf76b | 746 | lis r14,(DBSR_IC|DBSR_BT)@h /* clear the event */ |
2d27cfd3 BH |
747 | rlwinm r11,r11,0,~MSR_DE /* clear DE in the CSRR1 value */ |
748 | mtspr SPRN_DBSR,r14 | |
749 | mtspr SPRN_CSRR1,r11 | |
750 | lwz r10,PACA_EXCRIT+EX_CR(r13) /* restore registers */ | |
751 | ld r1,PACA_EXCRIT+EX_R1(r13) | |
752 | ld r14,PACA_EXCRIT+EX_R14(r13) | |
753 | ld r15,PACA_EXCRIT+EX_R15(r13) | |
754 | mtcr r10 | |
755 | ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */ | |
756 | ld r11,PACA_EXCRIT+EX_R11(r13) | |
9d378dfa | 757 | mfspr r13,SPRN_SPRG_CRIT_SCRATCH |
2d27cfd3 BH |
758 | rfci |
759 | ||
760 | /* Normal debug exception */ | |
761 | /* XXX We only handle coming from userspace for now since we can't | |
762 | * quite save properly an interrupted kernel state yet | |
763 | */ | |
764 | 1: andi. r14,r11,MSR_PR; /* check for userspace again */ | |
765 | beq kernel_dbg_exc; /* if from kernel mode */ | |
766 | ||
767 | /* Now we mash up things to make it look like we are coming on a | |
768 | * normal exception | |
769 | */ | |
2d27cfd3 | 770 | mfspr r14,SPRN_DBSR |
31f71248 | 771 | EXCEPTION_COMMON_CRIT(0xd00) |
2d27cfd3 BH |
772 | std r14,_DSISR(r1) |
773 | addi r3,r1,STACK_FRAME_OVERHEAD | |
774 | mr r4,r14 | |
775 | ld r14,PACA_EXCRIT+EX_R14(r13) | |
776 | ld r15,PACA_EXCRIT+EX_R15(r13) | |
b1576fec AB |
777 | bl save_nvgprs |
778 | bl DebugException | |
779 | b ret_from_except | |
2d27cfd3 BH |
780 | |
781 | kernel_dbg_exc: | |
782 | b . /* NYI */ | |
783 | ||
d36b4c4f KG |
784 | /* Debug exception as a debug interrupt*/ |
785 | START_EXCEPTION(debug_debug); | |
fecff0f7 MC |
786 | DBG_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG, |
787 | PROLOG_ADDITION_2REGS) | |
d36b4c4f KG |
788 | |
789 | /* | |
790 | * If there is a single step or branch-taken exception in an | |
791 | * exception entry sequence, it was probably meant to apply to | |
792 | * the code where the exception occurred (since exception entry | |
793 | * doesn't turn off DE automatically). We simulate the effect | |
794 | * of turning off DE on entry to an exception handler by turning | |
795 | * off DE in the DSRR1 value and clearing the debug status. | |
796 | */ | |
797 | ||
798 | mfspr r14,SPRN_DBSR /* check single-step/branch taken */ | |
6cecf76b | 799 | andis. r15,r14,(DBSR_IC|DBSR_BT)@h |
d36b4c4f KG |
800 | beq+ 1f |
801 | ||
802 | LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e) | |
68d10140 | 803 | LOAD_REG_IMMEDIATE(r15,__end_interrupts) |
d36b4c4f KG |
804 | cmpld cr0,r10,r14 |
805 | cmpld cr1,r10,r15 | |
806 | blt+ cr0,1f | |
807 | bge+ cr1,1f | |
808 | ||
809 | /* here it looks like we got an inappropriate debug exception. */ | |
6cecf76b | 810 | lis r14,(DBSR_IC|DBSR_BT)@h /* clear the event */ |
d36b4c4f KG |
811 | rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */ |
812 | mtspr SPRN_DBSR,r14 | |
813 | mtspr SPRN_DSRR1,r11 | |
814 | lwz r10,PACA_EXDBG+EX_CR(r13) /* restore registers */ | |
815 | ld r1,PACA_EXDBG+EX_R1(r13) | |
816 | ld r14,PACA_EXDBG+EX_R14(r13) | |
817 | ld r15,PACA_EXDBG+EX_R15(r13) | |
818 | mtcr r10 | |
819 | ld r10,PACA_EXDBG+EX_R10(r13) /* restore registers */ | |
820 | ld r11,PACA_EXDBG+EX_R11(r13) | |
821 | mfspr r13,SPRN_SPRG_DBG_SCRATCH | |
822 | rfdi | |
823 | ||
824 | /* Normal debug exception */ | |
825 | /* XXX We only handle coming from userspace for now since we can't | |
826 | * quite save properly an interrupted kernel state yet | |
827 | */ | |
828 | 1: andi. r14,r11,MSR_PR; /* check for userspace again */ | |
829 | beq kernel_dbg_exc; /* if from kernel mode */ | |
830 | ||
831 | /* Now we mash up things to make it look like we are coming on a | |
832 | * normal exception | |
833 | */ | |
d36b4c4f | 834 | mfspr r14,SPRN_DBSR |
31f71248 | 835 | EXCEPTION_COMMON_DBG(0xd08) |
28a3ded1 | 836 | INTS_DISABLE |
d36b4c4f KG |
837 | std r14,_DSISR(r1) |
838 | addi r3,r1,STACK_FRAME_OVERHEAD | |
839 | mr r4,r14 | |
840 | ld r14,PACA_EXDBG+EX_R14(r13) | |
841 | ld r15,PACA_EXDBG+EX_R15(r13) | |
b1576fec AB |
842 | bl save_nvgprs |
843 | bl DebugException | |
844 | b ret_from_except | |
d36b4c4f | 845 | |
7230c564 | 846 | START_EXCEPTION(perfmon); |
fecff0f7 MC |
847 | NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR, |
848 | PROLOG_ADDITION_NONE) | |
31f71248 | 849 | EXCEPTION_COMMON(0x260) |
28a3ded1 | 850 | INTS_DISABLE |
e4867336 | 851 | CHECK_NAPPING() |
3d97a619 | 852 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
853 | bl performance_monitor_exception |
854 | b ret_from_except_lite | |
89c81797 | 855 | |
7230c564 | 856 | /* Doorbell interrupt */ |
fecff0f7 | 857 | MASKABLE_EXCEPTION(0x280, BOOKE_INTERRUPT_DOORBELL, |
35425501 | 858 | doorbell, doorbell_exception, ACK_NONE) |
7230c564 | 859 | |
89c81797 BH |
860 | /* Doorbell critical Interrupt */ |
861 | START_EXCEPTION(doorbell_crit); | |
fecff0f7 MC |
862 | CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL, |
863 | PROLOG_ADDITION_NONE) | |
609af38f | 864 | EXCEPTION_COMMON_CRIT(0x2a0) |
b1576fec | 865 | bl save_nvgprs |
609af38f SW |
866 | bl special_reg_save |
867 | CHECK_NAPPING(); | |
868 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec | 869 | bl unknown_exception |
609af38f | 870 | b ret_from_crit_except |
89c81797 | 871 | |
5473eb1c MC |
872 | /* |
873 | * Guest doorbell interrupt | |
874 | * This general exception use GSRRx save/restore registers | |
875 | */ | |
876 | START_EXCEPTION(guest_doorbell); | |
fecff0f7 MC |
877 | GDBELL_EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL, |
878 | PROLOG_ADDITION_NONE) | |
31f71248 | 879 | EXCEPTION_COMMON(0x2c0) |
5473eb1c | 880 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec | 881 | bl save_nvgprs |
5473eb1c | 882 | INTS_RESTORE_HARD |
b1576fec AB |
883 | bl unknown_exception |
884 | b ret_from_except | |
3a6e9bd7 | 885 | |
7230c564 BH |
886 | /* Guest Doorbell critical Interrupt */ |
887 | START_EXCEPTION(guest_doorbell_crit); | |
fecff0f7 MC |
888 | CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT, |
889 | PROLOG_ADDITION_NONE) | |
609af38f | 890 | EXCEPTION_COMMON_CRIT(0x2e0) |
b1576fec | 891 | bl save_nvgprs |
609af38f SW |
892 | bl special_reg_save |
893 | CHECK_NAPPING(); | |
894 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec | 895 | bl unknown_exception |
609af38f | 896 | b ret_from_crit_except |
7230c564 BH |
897 | |
898 | /* Hypervisor call */ | |
899 | START_EXCEPTION(hypercall); | |
fecff0f7 MC |
900 | NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL, |
901 | PROLOG_ADDITION_NONE) | |
31f71248 | 902 | EXCEPTION_COMMON(0x310) |
7230c564 | 903 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec | 904 | bl save_nvgprs |
7230c564 | 905 | INTS_RESTORE_HARD |
b1576fec AB |
906 | bl unknown_exception |
907 | b ret_from_except | |
7230c564 BH |
908 | |
909 | /* Embedded Hypervisor priviledged */ | |
910 | START_EXCEPTION(ehpriv); | |
fecff0f7 MC |
911 | NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV, |
912 | PROLOG_ADDITION_NONE) | |
31f71248 | 913 | EXCEPTION_COMMON(0x320) |
7230c564 | 914 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec | 915 | bl save_nvgprs |
7230c564 | 916 | INTS_RESTORE_HARD |
b1576fec AB |
917 | bl unknown_exception |
918 | b ret_from_except | |
2d27cfd3 | 919 | |
228b1a47 MC |
920 | /* LRAT Error interrupt */ |
921 | START_EXCEPTION(lrat_error); | |
922 | NORMAL_EXCEPTION_PROLOG(0x340, BOOKE_INTERRUPT_LRAT_ERROR, | |
923 | PROLOG_ADDITION_NONE) | |
31f71248 | 924 | EXCEPTION_COMMON(0x340) |
228b1a47 MC |
925 | addi r3,r1,STACK_FRAME_OVERHEAD |
926 | bl .save_nvgprs | |
927 | INTS_RESTORE_HARD | |
928 | bl .unknown_exception | |
929 | b .ret_from_except | |
930 | ||
2d27cfd3 | 931 | /* |
7230c564 BH |
932 | * An interrupt came in while soft-disabled; We mark paca->irq_happened |
933 | * accordingly and if the interrupt is level sensitive, we hard disable | |
2d27cfd3 | 934 | */ |
3d97a619 | 935 | |
79b5c8db MC |
936 | .macro masked_interrupt_book3e paca_irq full_mask |
937 | lbz r10,PACAIRQHAPPENED(r13) | |
938 | ori r10,r10,\paca_irq | |
939 | stb r10,PACAIRQHAPPENED(r13) | |
940 | ||
941 | .if \full_mask == 1 | |
942 | rldicl r10,r11,48,1 /* clear MSR_EE */ | |
943 | rotldi r11,r10,16 | |
944 | mtspr SPRN_SRR1,r11 | |
945 | .endif | |
946 | ||
947 | lwz r11,PACA_EXGEN+EX_CR(r13) | |
948 | mtcr r11 | |
949 | ld r10,PACA_EXGEN+EX_R10(r13) | |
950 | ld r11,PACA_EXGEN+EX_R11(r13) | |
951 | mfspr r13,SPRN_SPRG_GEN_SCRATCH | |
952 | rfi | |
953 | b . | |
954 | .endm | |
955 | ||
7230c564 | 956 | masked_interrupt_book3e_0x500: |
79b5c8db MC |
957 | // XXX When adding support for EPR, use PACA_IRQ_EE_EDGE |
958 | masked_interrupt_book3e PACA_IRQ_EE 1 | |
7230c564 BH |
959 | |
960 | masked_interrupt_book3e_0x900: | |
79b5c8db MC |
961 | ACK_DEC(r10); |
962 | masked_interrupt_book3e PACA_IRQ_DEC 0 | |
963 | ||
7230c564 | 964 | masked_interrupt_book3e_0x980: |
79b5c8db MC |
965 | ACK_FIT(r10); |
966 | masked_interrupt_book3e PACA_IRQ_DEC 0 | |
967 | ||
7230c564 BH |
968 | masked_interrupt_book3e_0x280: |
969 | masked_interrupt_book3e_0x2c0: | |
79b5c8db | 970 | masked_interrupt_book3e PACA_IRQ_DBELL 0 |
7230c564 | 971 | |
7230c564 BH |
972 | /* |
973 | * Called from arch_local_irq_enable when an interrupt needs | |
974 | * to be resent. r3 contains either 0x500,0x900,0x260 or 0x280 | |
975 | * to indicate the kind of interrupt. MSR:EE is already off. | |
976 | * We generate a stackframe like if a real interrupt had happened. | |
977 | * | |
978 | * Note: While MSR:EE is off, we need to make sure that _MSR | |
979 | * in the generated frame has EE set to 1 or the exception | |
980 | * handler will not properly re-enable them. | |
981 | */ | |
982 | _GLOBAL(__replay_interrupt) | |
983 | /* We are going to jump to the exception common code which | |
984 | * will retrieve various register values from the PACA which | |
985 | * we don't give a damn about. | |
986 | */ | |
987 | mflr r10 | |
988 | mfmsr r11 | |
989 | mfcr r4 | |
990 | mtspr SPRN_SPRG_GEN_SCRATCH,r13; | |
991 | std r1,PACA_EXGEN+EX_R1(r13); | |
992 | stw r4,PACA_EXGEN+EX_CR(r13); | |
993 | ori r11,r11,MSR_EE | |
994 | subi r1,r1,INT_FRAME_SIZE; | |
995 | cmpwi cr0,r3,0x500 | |
996 | beq exc_0x500_common | |
997 | cmpwi cr0,r3,0x900 | |
998 | beq exc_0x900_common | |
999 | cmpwi cr0,r3,0x280 | |
1000 | beq exc_0x280_common | |
1001 | blr | |
1002 | ||
2d27cfd3 BH |
1003 | |
1004 | /* | |
1005 | * This is called from 0x300 and 0x400 handlers after the prologs with | |
1006 | * r14 and r15 containing the fault address and error code, with the | |
1007 | * original values stashed away in the PACA | |
1008 | */ | |
1009 | storage_fault_common: | |
1010 | std r14,_DAR(r1) | |
1011 | std r15,_DSISR(r1) | |
1012 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1013 | mr r4,r14 | |
1014 | mr r5,r15 | |
1015 | ld r14,PACA_EXGEN+EX_R14(r13) | |
1016 | ld r15,PACA_EXGEN+EX_R15(r13) | |
b1576fec | 1017 | bl do_page_fault |
2d27cfd3 BH |
1018 | cmpdi r3,0 |
1019 | bne- 1f | |
b1576fec AB |
1020 | b ret_from_except_lite |
1021 | 1: bl save_nvgprs | |
2d27cfd3 BH |
1022 | mr r5,r3 |
1023 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1024 | ld r4,_DAR(r1) | |
b1576fec AB |
1025 | bl bad_page_fault |
1026 | b ret_from_except | |
2d27cfd3 BH |
1027 | |
1028 | /* | |
1029 | * Alignment exception doesn't fit entirely in the 0x100 bytes so it | |
1030 | * continues here. | |
1031 | */ | |
1032 | alignment_more: | |
1033 | std r14,_DAR(r1) | |
1034 | std r15,_DSISR(r1) | |
1035 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1036 | ld r14,PACA_EXGEN+EX_R14(r13) | |
1037 | ld r15,PACA_EXGEN+EX_R15(r13) | |
b1576fec | 1038 | bl save_nvgprs |
2d27cfd3 | 1039 | INTS_RESTORE_HARD |
b1576fec AB |
1040 | bl alignment_exception |
1041 | b ret_from_except | |
2d27cfd3 BH |
1042 | |
1043 | /* | |
1044 | * We branch here from entry_64.S for the last stage of the exception | |
1045 | * return code path. MSR:EE is expected to be off at that point | |
1046 | */ | |
1047 | _GLOBAL(exception_return_book3e) | |
1048 | b 1f | |
1049 | ||
1050 | /* This is the return from load_up_fpu fast path which could do with | |
1051 | * less GPR restores in fact, but for now we have a single return path | |
1052 | */ | |
1053 | .globl fast_exception_return | |
1054 | fast_exception_return: | |
1055 | wrteei 0 | |
1056 | 1: mr r0,r13 | |
1057 | ld r10,_MSR(r1) | |
1058 | REST_4GPRS(2, r1) | |
1059 | andi. r6,r10,MSR_PR | |
1060 | REST_2GPRS(6, r1) | |
1061 | beq 1f | |
1062 | ACCOUNT_CPU_USER_EXIT(r10, r11) | |
1063 | ld r0,GPR13(r1) | |
1064 | ||
1065 | 1: stdcx. r0,0,r1 /* to clear the reservation */ | |
1066 | ||
1067 | ld r8,_CCR(r1) | |
1068 | ld r9,_LINK(r1) | |
1069 | ld r10,_CTR(r1) | |
1070 | ld r11,_XER(r1) | |
1071 | mtcr r8 | |
1072 | mtlr r9 | |
1073 | mtctr r10 | |
1074 | mtxer r11 | |
1075 | REST_2GPRS(8, r1) | |
1076 | ld r10,GPR10(r1) | |
1077 | ld r11,GPR11(r1) | |
1078 | ld r12,GPR12(r1) | |
1079 | mtspr SPRN_SPRG_GEN_SCRATCH,r0 | |
1080 | ||
1081 | std r10,PACA_EXGEN+EX_R10(r13); | |
1082 | std r11,PACA_EXGEN+EX_R11(r13); | |
1083 | ld r10,_NIP(r1) | |
1084 | ld r11,_MSR(r1) | |
1085 | ld r0,GPR0(r1) | |
1086 | ld r1,GPR1(r1) | |
1087 | mtspr SPRN_SRR0,r10 | |
1088 | mtspr SPRN_SRR1,r11 | |
1089 | ld r10,PACA_EXGEN+EX_R10(r13) | |
1090 | ld r11,PACA_EXGEN+EX_R11(r13) | |
1091 | mfspr r13,SPRN_SPRG_GEN_SCRATCH | |
1092 | rfi | |
1093 | ||
1094 | /* | |
1095 | * Trampolines used when spotting a bad kernel stack pointer in | |
1096 | * the exception entry code. | |
1097 | * | |
1098 | * TODO: move some bits like SRR0 read to trampoline, pass PACA | |
1099 | * index around, etc... to handle crit & mcheck | |
1100 | */ | |
1101 | BAD_STACK_TRAMPOLINE(0x000) | |
1102 | BAD_STACK_TRAMPOLINE(0x100) | |
1103 | BAD_STACK_TRAMPOLINE(0x200) | |
cd66cc2e | 1104 | BAD_STACK_TRAMPOLINE(0x220) |
3a6e9bd7 | 1105 | BAD_STACK_TRAMPOLINE(0x260) |
7230c564 BH |
1106 | BAD_STACK_TRAMPOLINE(0x280) |
1107 | BAD_STACK_TRAMPOLINE(0x2a0) | |
3a6e9bd7 SW |
1108 | BAD_STACK_TRAMPOLINE(0x2c0) |
1109 | BAD_STACK_TRAMPOLINE(0x2e0) | |
2d27cfd3 | 1110 | BAD_STACK_TRAMPOLINE(0x300) |
3a6e9bd7 SW |
1111 | BAD_STACK_TRAMPOLINE(0x310) |
1112 | BAD_STACK_TRAMPOLINE(0x320) | |
228b1a47 | 1113 | BAD_STACK_TRAMPOLINE(0x340) |
2d27cfd3 BH |
1114 | BAD_STACK_TRAMPOLINE(0x400) |
1115 | BAD_STACK_TRAMPOLINE(0x500) | |
1116 | BAD_STACK_TRAMPOLINE(0x600) | |
1117 | BAD_STACK_TRAMPOLINE(0x700) | |
1118 | BAD_STACK_TRAMPOLINE(0x800) | |
1119 | BAD_STACK_TRAMPOLINE(0x900) | |
1120 | BAD_STACK_TRAMPOLINE(0x980) | |
1121 | BAD_STACK_TRAMPOLINE(0x9f0) | |
1122 | BAD_STACK_TRAMPOLINE(0xa00) | |
1123 | BAD_STACK_TRAMPOLINE(0xb00) | |
1124 | BAD_STACK_TRAMPOLINE(0xc00) | |
1125 | BAD_STACK_TRAMPOLINE(0xd00) | |
7230c564 | 1126 | BAD_STACK_TRAMPOLINE(0xd08) |
2d27cfd3 BH |
1127 | BAD_STACK_TRAMPOLINE(0xe00) |
1128 | BAD_STACK_TRAMPOLINE(0xf00) | |
1129 | BAD_STACK_TRAMPOLINE(0xf20) | |
1130 | ||
1131 | .globl bad_stack_book3e | |
1132 | bad_stack_book3e: | |
1133 | /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */ | |
1134 | mfspr r10,SPRN_SRR0; /* read SRR0 before touching stack */ | |
1135 | ld r1,PACAEMERGSP(r13) | |
1136 | subi r1,r1,64+INT_FRAME_SIZE | |
1137 | std r10,_NIP(r1) | |
1138 | std r11,_MSR(r1) | |
1139 | ld r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */ | |
1140 | lwz r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */ | |
1141 | std r10,GPR1(r1) | |
1142 | std r11,_CCR(r1) | |
1143 | mfspr r10,SPRN_DEAR | |
1144 | mfspr r11,SPRN_ESR | |
1145 | std r10,_DAR(r1) | |
1146 | std r11,_DSISR(r1) | |
1147 | std r0,GPR0(r1); /* save r0 in stackframe */ \ | |
1148 | std r2,GPR2(r1); /* save r2 in stackframe */ \ | |
1149 | SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ | |
1150 | SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ | |
1151 | std r9,GPR9(r1); /* save r9 in stackframe */ \ | |
1152 | ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \ | |
1153 | ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \ | |
1154 | mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \ | |
1155 | std r3,GPR10(r1); /* save r10 to stackframe */ \ | |
1156 | std r4,GPR11(r1); /* save r11 to stackframe */ \ | |
1157 | std r12,GPR12(r1); /* save r12 in stackframe */ \ | |
1158 | std r5,GPR13(r1); /* save it to stackframe */ \ | |
1159 | mflr r10 | |
1160 | mfctr r11 | |
1161 | mfxer r12 | |
1162 | std r10,_LINK(r1) | |
1163 | std r11,_CTR(r1) | |
1164 | std r12,_XER(r1) | |
1165 | SAVE_10GPRS(14,r1) | |
1166 | SAVE_8GPRS(24,r1) | |
1167 | lhz r12,PACA_TRAP_SAVE(r13) | |
1168 | std r12,_TRAP(r1) | |
1169 | addi r11,r1,INT_FRAME_SIZE | |
1170 | std r11,0(r1) | |
1171 | li r12,0 | |
1172 | std r12,0(r11) | |
1173 | ld r2,PACATOC(r13) | |
1174 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec | 1175 | bl kernel_bad_stack |
2d27cfd3 BH |
1176 | b 1b |
1177 | ||
1178 | /* | |
1179 | * Setup the initial TLB for a core. This current implementation | |
1180 | * assume that whatever we are running off will not conflict with | |
1181 | * the new mapping at PAGE_OFFSET. | |
2d27cfd3 BH |
1182 | */ |
1183 | _GLOBAL(initial_tlb_book3e) | |
1184 | ||
bb1af71e KG |
1185 | /* Look for the first TLB with IPROT set */ |
1186 | mfspr r4,SPRN_TLB0CFG | |
1187 | andi. r3,r4,TLBnCFG_IPROT | |
1188 | lis r3,MAS0_TLBSEL(0)@h | |
1189 | bne found_iprot | |
1190 | ||
1191 | mfspr r4,SPRN_TLB1CFG | |
1192 | andi. r3,r4,TLBnCFG_IPROT | |
1193 | lis r3,MAS0_TLBSEL(1)@h | |
1194 | bne found_iprot | |
1195 | ||
1196 | mfspr r4,SPRN_TLB2CFG | |
1197 | andi. r3,r4,TLBnCFG_IPROT | |
1198 | lis r3,MAS0_TLBSEL(2)@h | |
1199 | bne found_iprot | |
1200 | ||
1201 | lis r3,MAS0_TLBSEL(3)@h | |
1202 | mfspr r4,SPRN_TLB3CFG | |
1203 | /* fall through */ | |
1204 | ||
1205 | found_iprot: | |
1206 | andi. r5,r4,TLBnCFG_HES | |
1207 | bne have_hes | |
1208 | ||
1209 | mflr r8 /* save LR */ | |
1210 | /* 1. Find the index of the entry we're executing in | |
1211 | * | |
1212 | * r3 = MAS0_TLBSEL (for the iprot array) | |
1213 | * r4 = SPRN_TLBnCFG | |
1214 | */ | |
1215 | bl invstr /* Find our address */ | |
1216 | invstr: mflr r6 /* Make it accessible */ | |
1217 | mfmsr r7 | |
1218 | rlwinm r5,r7,27,31,31 /* extract MSR[IS] */ | |
1219 | mfspr r7,SPRN_PID | |
1220 | slwi r7,r7,16 | |
1221 | or r7,r7,r5 | |
1222 | mtspr SPRN_MAS6,r7 | |
1223 | tlbsx 0,r6 /* search MSR[IS], SPID=PID */ | |
1224 | ||
1225 | mfspr r3,SPRN_MAS0 | |
1226 | rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */ | |
1227 | ||
1228 | mfspr r7,SPRN_MAS1 /* Insure IPROT set */ | |
1229 | oris r7,r7,MAS1_IPROT@h | |
1230 | mtspr SPRN_MAS1,r7 | |
1231 | tlbwe | |
1232 | ||
1233 | /* 2. Invalidate all entries except the entry we're executing in | |
1234 | * | |
1235 | * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in | |
1236 | * r4 = SPRN_TLBnCFG | |
1237 | * r5 = ESEL of entry we are running in | |
1238 | */ | |
1239 | andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */ | |
1240 | li r6,0 /* Set Entry counter to 0 */ | |
1241 | 1: mr r7,r3 /* Set MAS0(TLBSEL) */ | |
1242 | rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */ | |
1243 | mtspr SPRN_MAS0,r7 | |
1244 | tlbre | |
1245 | mfspr r7,SPRN_MAS1 | |
1246 | rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */ | |
1247 | cmpw r5,r6 | |
1248 | beq skpinv /* Dont update the current execution TLB */ | |
1249 | mtspr SPRN_MAS1,r7 | |
1250 | tlbwe | |
1251 | isync | |
1252 | skpinv: addi r6,r6,1 /* Increment */ | |
1253 | cmpw r6,r4 /* Are we done? */ | |
1254 | bne 1b /* If not, repeat */ | |
1255 | ||
1256 | /* Invalidate all TLBs */ | |
962cffbd | 1257 | PPC_TLBILX_ALL(0,R0) |
bb1af71e KG |
1258 | sync |
1259 | isync | |
1260 | ||
1261 | /* 3. Setup a temp mapping and jump to it | |
1262 | * | |
1263 | * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in | |
1264 | * r5 = ESEL of entry we are running in | |
1265 | */ | |
1266 | andi. r7,r5,0x1 /* Find an entry not used and is non-zero */ | |
1267 | addi r7,r7,0x1 | |
1268 | mr r4,r3 /* Set MAS0(TLBSEL) = 1 */ | |
1269 | mtspr SPRN_MAS0,r4 | |
1270 | tlbre | |
1271 | ||
1272 | rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */ | |
1273 | mtspr SPRN_MAS0,r4 | |
1274 | ||
1275 | mfspr r7,SPRN_MAS1 | |
1276 | xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */ | |
1277 | mtspr SPRN_MAS1,r6 | |
1278 | ||
1279 | tlbwe | |
1280 | ||
1281 | mfmsr r6 | |
1282 | xori r6,r6,MSR_IS | |
1283 | mtspr SPRN_SRR1,r6 | |
1284 | bl 1f /* Find our address */ | |
1285 | 1: mflr r6 | |
1286 | addi r6,r6,(2f - 1b) | |
1287 | mtspr SPRN_SRR0,r6 | |
1288 | rfi | |
1289 | 2: | |
1290 | ||
1291 | /* 4. Clear out PIDs & Search info | |
1292 | * | |
1293 | * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in | |
1294 | * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping | |
1295 | * r5 = MAS3 | |
1296 | */ | |
1297 | li r6,0 | |
1298 | mtspr SPRN_MAS6,r6 | |
1299 | mtspr SPRN_PID,r6 | |
1300 | ||
1301 | /* 5. Invalidate mapping we started in | |
1302 | * | |
1303 | * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in | |
1304 | * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping | |
1305 | * r5 = MAS3 | |
1306 | */ | |
1307 | mtspr SPRN_MAS0,r3 | |
1308 | tlbre | |
1309 | mfspr r6,SPRN_MAS1 | |
ed2ddc56 | 1310 | rlwinm r6,r6,0,2,31 /* clear IPROT and VALID */ |
bb1af71e KG |
1311 | mtspr SPRN_MAS1,r6 |
1312 | tlbwe | |
bb1af71e KG |
1313 | sync |
1314 | isync | |
1315 | ||
c6023202 SW |
1316 | /* |
1317 | * The mapping only needs to be cache-coherent on SMP, except on | |
1318 | * Freescale e500mc derivatives where it's also needed for coherent DMA. | |
1319 | */ | |
1320 | #if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC) | |
1321 | #define M_IF_NEEDED MAS2_M | |
bb1af71e | 1322 | #else |
c6023202 | 1323 | #define M_IF_NEEDED 0 |
bb1af71e KG |
1324 | #endif |
1325 | ||
1326 | /* 6. Setup KERNELBASE mapping in TLB[0] | |
1327 | * | |
1328 | * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in | |
1329 | * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping | |
1330 | * r5 = MAS3 | |
1331 | */ | |
1332 | rlwinm r3,r3,0,16,3 /* clear ESEL */ | |
1333 | mtspr SPRN_MAS0,r3 | |
1334 | lis r6,(MAS1_VALID|MAS1_IPROT)@h | |
1335 | ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l | |
1336 | mtspr SPRN_MAS1,r6 | |
1337 | ||
c6023202 | 1338 | LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_NEEDED) |
bb1af71e KG |
1339 | mtspr SPRN_MAS2,r6 |
1340 | ||
1341 | rlwinm r5,r5,0,0,25 | |
1342 | ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX | |
1343 | mtspr SPRN_MAS3,r5 | |
1344 | li r5,-1 | |
1345 | rlwinm r5,r5,0,0,25 | |
1346 | ||
1347 | tlbwe | |
1348 | ||
1349 | /* 7. Jump to KERNELBASE mapping | |
1350 | * | |
1351 | * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping | |
1352 | */ | |
1353 | /* Now we branch the new virtual address mapped by this entry */ | |
1cb6e064 TC |
1354 | bl 1f /* Find our address */ |
1355 | 1: mflr r6 | |
1356 | addi r6,r6,(2f - 1b) | |
1357 | tovirt(r6,r6) | |
bb1af71e KG |
1358 | lis r7,MSR_KERNEL@h |
1359 | ori r7,r7,MSR_KERNEL@l | |
1360 | mtspr SPRN_SRR0,r6 | |
1361 | mtspr SPRN_SRR1,r7 | |
1362 | rfi /* start execution out of TLB1[0] entry */ | |
1363 | 2: | |
1364 | ||
1365 | /* 8. Clear out the temp mapping | |
1366 | * | |
1367 | * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in | |
1368 | */ | |
1369 | mtspr SPRN_MAS0,r4 | |
1370 | tlbre | |
1371 | mfspr r5,SPRN_MAS1 | |
ed2ddc56 | 1372 | rlwinm r5,r5,0,2,31 /* clear IPROT and VALID */ |
bb1af71e KG |
1373 | mtspr SPRN_MAS1,r5 |
1374 | tlbwe | |
bb1af71e KG |
1375 | sync |
1376 | isync | |
1377 | ||
1378 | /* We translate LR and return */ | |
1379 | tovirt(r8,r8) | |
1380 | mtlr r8 | |
1381 | blr | |
1382 | ||
1383 | have_hes: | |
2d27cfd3 BH |
1384 | /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the |
1385 | * kernel linear mapping. We also set MAS8 once for all here though | |
1386 | * that will have to be made dependent on whether we are running under | |
1387 | * a hypervisor I suppose. | |
1388 | */ | |
a1d0d98d DG |
1389 | |
1390 | /* BEWARE, MAGIC | |
1391 | * This code is called as an ordinary function on the boot CPU. But to | |
1392 | * avoid duplication, this code is also used in SCOM bringup of | |
1393 | * secondary CPUs. We read the code between the initial_tlb_code_start | |
1394 | * and initial_tlb_code_end labels one instruction at a time and RAM it | |
1395 | * into the new core via SCOM. That doesn't process branches, so there | |
1396 | * must be none between those two labels. It also means if this code | |
1397 | * ever takes any parameters, the SCOM code must also be updated to | |
1398 | * provide them. | |
1399 | */ | |
1400 | .globl a2_tlbinit_code_start | |
1401 | a2_tlbinit_code_start: | |
1402 | ||
1a51dde1 BH |
1403 | ori r11,r3,MAS0_WQ_ALLWAYS |
1404 | oris r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */ | |
1405 | mtspr SPRN_MAS0,r11 | |
2d27cfd3 BH |
1406 | lis r3,(MAS1_VALID | MAS1_IPROT)@h |
1407 | ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT | |
1408 | mtspr SPRN_MAS1,r3 | |
1409 | LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M) | |
1410 | mtspr SPRN_MAS2,r3 | |
1411 | li r3,MAS3_SR | MAS3_SW | MAS3_SX | |
1412 | mtspr SPRN_MAS7_MAS3,r3 | |
1413 | li r3,0 | |
1414 | mtspr SPRN_MAS8,r3 | |
1415 | ||
1416 | /* Write the TLB entry */ | |
1417 | tlbwe | |
1418 | ||
a1d0d98d DG |
1419 | .globl a2_tlbinit_after_linear_map |
1420 | a2_tlbinit_after_linear_map: | |
1421 | ||
2d27cfd3 BH |
1422 | /* Now we branch the new virtual address mapped by this entry */ |
1423 | LOAD_REG_IMMEDIATE(r3,1f) | |
1424 | mtctr r3 | |
1425 | bctr | |
1426 | ||
1427 | 1: /* We are now running at PAGE_OFFSET, clean the TLB of everything | |
f0aae323 JM |
1428 | * else (including IPROTed things left by firmware) |
1429 | * r4 = TLBnCFG | |
1430 | * r3 = current address (more or less) | |
2d27cfd3 | 1431 | */ |
f0aae323 JM |
1432 | |
1433 | li r5,0 | |
1434 | mtspr SPRN_MAS6,r5 | |
1435 | tlbsx 0,r3 | |
1436 | ||
1437 | rlwinm r9,r4,0,TLBnCFG_N_ENTRY | |
1438 | rlwinm r10,r4,8,0xff | |
1439 | addi r10,r10,-1 /* Get inner loop mask */ | |
1440 | ||
1441 | li r3,1 | |
1442 | ||
1443 | mfspr r5,SPRN_MAS1 | |
1444 | rlwinm r5,r5,0,(~(MAS1_VALID|MAS1_IPROT)) | |
1445 | ||
1446 | mfspr r6,SPRN_MAS2 | |
1447 | rldicr r6,r6,0,51 /* Extract EPN */ | |
1448 | ||
1449 | mfspr r7,SPRN_MAS0 | |
1450 | rlwinm r7,r7,0,0xffff0fff /* Clear HES and WQ */ | |
1451 | ||
1452 | rlwinm r8,r7,16,0xfff /* Extract ESEL */ | |
1453 | ||
1454 | 2: add r4,r3,r8 | |
1455 | and r4,r4,r10 | |
1456 | ||
1457 | rlwimi r7,r4,16,MAS0_ESEL_MASK | |
1458 | ||
1459 | mtspr SPRN_MAS0,r7 | |
1460 | mtspr SPRN_MAS1,r5 | |
1461 | mtspr SPRN_MAS2,r6 | |
1462 | tlbwe | |
1463 | ||
1464 | addi r3,r3,1 | |
1465 | and. r4,r3,r10 | |
1466 | ||
1467 | bne 3f | |
1468 | addis r6,r6,(1<<30)@h | |
1469 | 3: | |
1470 | cmpw r3,r9 | |
1471 | blt 2b | |
1472 | ||
a1d0d98d DG |
1473 | .globl a2_tlbinit_after_iprot_flush |
1474 | a2_tlbinit_after_iprot_flush: | |
1475 | ||
962cffbd | 1476 | PPC_TLBILX(0,0,R0) |
2d27cfd3 BH |
1477 | sync |
1478 | isync | |
1479 | ||
a1d0d98d DG |
1480 | .globl a2_tlbinit_code_end |
1481 | a2_tlbinit_code_end: | |
1482 | ||
2d27cfd3 BH |
1483 | /* We translate LR and return */ |
1484 | mflr r3 | |
1485 | tovirt(r3,r3) | |
1486 | mtlr r3 | |
1487 | blr | |
1488 | ||
1489 | /* | |
1490 | * Main entry (boot CPU, thread 0) | |
1491 | * | |
1492 | * We enter here from head_64.S, possibly after the prom_init trampoline | |
1493 | * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits | |
1494 | * mode. Anything else is as it was left by the bootloader | |
1495 | * | |
1496 | * Initial requirements of this port: | |
1497 | * | |
1498 | * - Kernel loaded at 0 physical | |
1499 | * - A good lump of memory mapped 0:0 by UTLB entry 0 | |
1500 | * - MSR:IS & MSR:DS set to 0 | |
1501 | * | |
1502 | * Note that some of the above requirements will be relaxed in the future | |
1503 | * as the kernel becomes smarter at dealing with different initial conditions | |
1504 | * but for now you have to be careful | |
1505 | */ | |
1506 | _GLOBAL(start_initialization_book3e) | |
1507 | mflr r28 | |
1508 | ||
1509 | /* First, we need to setup some initial TLBs to map the kernel | |
1510 | * text, data and bss at PAGE_OFFSET. We don't have a real mode | |
1511 | * and always use AS 0, so we just set it up to match our link | |
1512 | * address and never use 0 based addresses. | |
1513 | */ | |
b1576fec | 1514 | bl initial_tlb_book3e |
2d27cfd3 BH |
1515 | |
1516 | /* Init global core bits */ | |
b1576fec | 1517 | bl init_core_book3e |
2d27cfd3 BH |
1518 | |
1519 | /* Init per-thread bits */ | |
b1576fec | 1520 | bl init_thread_book3e |
2d27cfd3 BH |
1521 | |
1522 | /* Return to common init code */ | |
1523 | tovirt(r28,r28) | |
1524 | mtlr r28 | |
1525 | blr | |
1526 | ||
1527 | ||
1528 | /* | |
1529 | * Secondary core/processor entry | |
1530 | * | |
1531 | * This is entered for thread 0 of a secondary core, all other threads | |
1532 | * are expected to be stopped. It's similar to start_initialization_book3e | |
1533 | * except that it's generally entered from the holding loop in head_64.S | |
1534 | * after CPUs have been gathered by Open Firmware. | |
1535 | * | |
1536 | * We assume we are in 32 bits mode running with whatever TLB entry was | |
1537 | * set for us by the firmware or POR engine. | |
1538 | */ | |
1539 | _GLOBAL(book3e_secondary_core_init_tlb_set) | |
1540 | li r4,1 | |
b1576fec | 1541 | b generic_secondary_smp_init |
2d27cfd3 BH |
1542 | |
1543 | _GLOBAL(book3e_secondary_core_init) | |
1544 | mflr r28 | |
1545 | ||
1546 | /* Do we need to setup initial TLB entry ? */ | |
1547 | cmplwi r4,0 | |
1548 | bne 2f | |
1549 | ||
1550 | /* Setup TLB for this core */ | |
b1576fec | 1551 | bl initial_tlb_book3e |
2d27cfd3 BH |
1552 | |
1553 | /* We can return from the above running at a different | |
1554 | * address, so recalculate r2 (TOC) | |
1555 | */ | |
b1576fec | 1556 | bl relative_toc |
2d27cfd3 BH |
1557 | |
1558 | /* Init global core bits */ | |
b1576fec | 1559 | 2: bl init_core_book3e |
2d27cfd3 BH |
1560 | |
1561 | /* Init per-thread bits */ | |
b1576fec | 1562 | 3: bl init_thread_book3e |
2d27cfd3 BH |
1563 | |
1564 | /* Return to common init code at proper virtual address. | |
1565 | * | |
1566 | * Due to various previous assumptions, we know we entered this | |
1567 | * function at either the final PAGE_OFFSET mapping or using a | |
1568 | * 1:1 mapping at 0, so we don't bother doing a complicated check | |
1569 | * here, we just ensure the return address has the right top bits. | |
1570 | * | |
1571 | * Note that if we ever want to be smarter about where we can be | |
1572 | * started from, we have to be careful that by the time we reach | |
1573 | * the code below we may already be running at a different location | |
1574 | * than the one we were called from since initial_tlb_book3e can | |
1575 | * have moved us already. | |
1576 | */ | |
1577 | cmpdi cr0,r28,0 | |
1578 | blt 1f | |
1579 | lis r3,PAGE_OFFSET@highest | |
1580 | sldi r3,r3,32 | |
1581 | or r28,r28,r3 | |
1582 | 1: mtlr r28 | |
1583 | blr | |
1584 | ||
1585 | _GLOBAL(book3e_secondary_thread_init) | |
1586 | mflr r28 | |
1587 | b 3b | |
1588 | ||
1cb6e064 | 1589 | .globl init_core_book3e |
6a3bab90 | 1590 | init_core_book3e: |
2d27cfd3 | 1591 | /* Establish the interrupt vector base */ |
1cb6e064 TC |
1592 | tovirt(r2,r2) |
1593 | LOAD_REG_ADDR(r3, interrupt_base_book3e) | |
2d27cfd3 BH |
1594 | mtspr SPRN_IVPR,r3 |
1595 | sync | |
1596 | blr | |
1597 | ||
6a3bab90 | 1598 | init_thread_book3e: |
2d27cfd3 BH |
1599 | lis r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h |
1600 | mtspr SPRN_EPCR,r3 | |
1601 | ||
1602 | /* Make sure interrupts are off */ | |
1603 | wrteei 0 | |
1604 | ||
6c188829 KG |
1605 | /* disable all timers and clear out status */ |
1606 | li r3,0 | |
2d27cfd3 | 1607 | mtspr SPRN_TCR,r3 |
6c188829 KG |
1608 | mfspr r3,SPRN_TSR |
1609 | mtspr SPRN_TSR,r3 | |
2d27cfd3 BH |
1610 | |
1611 | blr | |
1612 | ||
4b98d9e7 KG |
1613 | _GLOBAL(__setup_base_ivors) |
1614 | SET_IVOR(0, 0x020) /* Critical Input */ | |
1615 | SET_IVOR(1, 0x000) /* Machine Check */ | |
1616 | SET_IVOR(2, 0x060) /* Data Storage */ | |
1617 | SET_IVOR(3, 0x080) /* Instruction Storage */ | |
1618 | SET_IVOR(4, 0x0a0) /* External Input */ | |
1619 | SET_IVOR(5, 0x0c0) /* Alignment */ | |
1620 | SET_IVOR(6, 0x0e0) /* Program */ | |
1621 | SET_IVOR(7, 0x100) /* FP Unavailable */ | |
1622 | SET_IVOR(8, 0x120) /* System Call */ | |
1623 | SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */ | |
1624 | SET_IVOR(10, 0x160) /* Decrementer */ | |
1625 | SET_IVOR(11, 0x180) /* Fixed Interval Timer */ | |
1626 | SET_IVOR(12, 0x1a0) /* Watchdog Timer */ | |
1627 | SET_IVOR(13, 0x1c0) /* Data TLB Error */ | |
1628 | SET_IVOR(14, 0x1e0) /* Instruction TLB Error */ | |
1629 | SET_IVOR(15, 0x040) /* Debug */ | |
2d27cfd3 | 1630 | |
4b98d9e7 | 1631 | sync |
2d27cfd3 | 1632 | |
4b98d9e7 | 1633 | blr |
3a6e9bd7 | 1634 | |
cd66cc2e KG |
1635 | _GLOBAL(setup_altivec_ivors) |
1636 | SET_IVOR(32, 0x200) /* AltiVec Unavailable */ | |
1637 | SET_IVOR(33, 0x220) /* AltiVec Assist */ | |
1638 | blr | |
1639 | ||
3a6e9bd7 SW |
1640 | _GLOBAL(setup_perfmon_ivor) |
1641 | SET_IVOR(35, 0x260) /* Performance Monitor */ | |
1642 | blr | |
1643 | ||
1644 | _GLOBAL(setup_doorbell_ivors) | |
1645 | SET_IVOR(36, 0x280) /* Processor Doorbell */ | |
1646 | SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */ | |
3a6e9bd7 SW |
1647 | blr |
1648 | ||
1649 | _GLOBAL(setup_ehv_ivors) | |
3a6e9bd7 SW |
1650 | SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */ |
1651 | SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */ | |
0778407f VS |
1652 | SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */ |
1653 | SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */ | |
3a6e9bd7 | 1654 | blr |
228b1a47 MC |
1655 | |
1656 | _GLOBAL(setup_lrat_ivor) | |
1657 | SET_IVOR(42, 0x340) /* LRAT Error */ | |
1658 | blr |