Commit | Line | Data |
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9994a338 | 1 | /* |
9994a338 PM |
2 | * PowerPC version |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP | |
5 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
6 | * Adapted for Power Macintosh by Paul Mackerras. | |
7 | * Low-level exception handlers and MMU support | |
8 | * rewritten by Paul Mackerras. | |
9 | * Copyright (C) 1996 Paul Mackerras. | |
10 | * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net). | |
11 | * | |
12 | * This file contains the system call entry code, context switch | |
13 | * code, and exception/interrupt return code for PowerPC. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version | |
18 | * 2 of the License, or (at your option) any later version. | |
19 | */ | |
20 | ||
9994a338 PM |
21 | #include <linux/errno.h> |
22 | #include <asm/unistd.h> | |
23 | #include <asm/processor.h> | |
24 | #include <asm/page.h> | |
25 | #include <asm/mmu.h> | |
26 | #include <asm/thread_info.h> | |
27 | #include <asm/ppc_asm.h> | |
28 | #include <asm/asm-offsets.h> | |
29 | #include <asm/cputable.h> | |
3f639ee8 | 30 | #include <asm/firmware.h> |
007d88d0 | 31 | #include <asm/bug.h> |
ec2b36b9 | 32 | #include <asm/ptrace.h> |
945feb17 | 33 | #include <asm/irqflags.h> |
395a59d0 | 34 | #include <asm/ftrace.h> |
9994a338 PM |
35 | |
36 | /* | |
37 | * System calls. | |
38 | */ | |
39 | .section ".toc","aw" | |
40 | .SYS_CALL_TABLE: | |
41 | .tc .sys_call_table[TC],.sys_call_table | |
42 | ||
43 | /* This value is used to mark exception frames on the stack. */ | |
44 | exception_marker: | |
ec2b36b9 | 45 | .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER |
9994a338 PM |
46 | |
47 | .section ".text" | |
48 | .align 7 | |
49 | ||
50 | #undef SHOW_SYSCALLS | |
51 | ||
52 | .globl system_call_common | |
53 | system_call_common: | |
54 | andi. r10,r12,MSR_PR | |
55 | mr r10,r1 | |
56 | addi r1,r1,-INT_FRAME_SIZE | |
57 | beq- 1f | |
58 | ld r1,PACAKSAVE(r13) | |
59 | 1: std r10,0(r1) | |
60 | std r11,_NIP(r1) | |
61 | std r12,_MSR(r1) | |
62 | std r0,GPR0(r1) | |
63 | std r10,GPR1(r1) | |
c6622f63 | 64 | ACCOUNT_CPU_USER_ENTRY(r10, r11) |
ab598b66 PM |
65 | /* |
66 | * This "crclr so" clears CR0.SO, which is the error indication on | |
67 | * return from this system call. There must be no cmp instruction | |
68 | * between it and the "mfcr r9" below, otherwise if XER.SO is set, | |
69 | * CR0.SO will get set, causing all system calls to appear to fail. | |
70 | */ | |
71 | crclr so | |
9994a338 PM |
72 | std r2,GPR2(r1) |
73 | std r3,GPR3(r1) | |
74 | std r4,GPR4(r1) | |
75 | std r5,GPR5(r1) | |
76 | std r6,GPR6(r1) | |
77 | std r7,GPR7(r1) | |
78 | std r8,GPR8(r1) | |
79 | li r11,0 | |
80 | std r11,GPR9(r1) | |
81 | std r11,GPR10(r1) | |
82 | std r11,GPR11(r1) | |
83 | std r11,GPR12(r1) | |
84 | std r9,GPR13(r1) | |
9994a338 PM |
85 | mfcr r9 |
86 | mflr r10 | |
87 | li r11,0xc01 | |
88 | std r9,_CCR(r1) | |
89 | std r10,_LINK(r1) | |
90 | std r11,_TRAP(r1) | |
91 | mfxer r9 | |
92 | mfctr r10 | |
93 | std r9,_XER(r1) | |
94 | std r10,_CTR(r1) | |
95 | std r3,ORIG_GPR3(r1) | |
96 | ld r2,PACATOC(r13) | |
97 | addi r9,r1,STACK_FRAME_OVERHEAD | |
98 | ld r11,exception_marker@toc(r2) | |
99 | std r11,-16(r9) /* "regshere" marker */ | |
945feb17 BH |
100 | #ifdef CONFIG_TRACE_IRQFLAGS |
101 | bl .trace_hardirqs_on | |
102 | REST_GPR(0,r1) | |
103 | REST_4GPRS(3,r1) | |
104 | REST_2GPRS(7,r1) | |
105 | addi r9,r1,STACK_FRAME_OVERHEAD | |
106 | ld r12,_MSR(r1) | |
107 | #endif /* CONFIG_TRACE_IRQFLAGS */ | |
d04c56f7 PM |
108 | li r10,1 |
109 | stb r10,PACASOFTIRQEN(r13) | |
110 | stb r10,PACAHARDIRQEN(r13) | |
111 | std r10,SOFTE(r1) | |
9994a338 | 112 | #ifdef CONFIG_PPC_ISERIES |
3f639ee8 | 113 | BEGIN_FW_FTR_SECTION |
9994a338 PM |
114 | /* Hack for handling interrupts when soft-enabling on iSeries */ |
115 | cmpdi cr1,r0,0x5555 /* syscall 0x5555 */ | |
116 | andi. r10,r12,MSR_PR /* from kernel */ | |
117 | crand 4*cr0+eq,4*cr1+eq,4*cr0+eq | |
c705677e SR |
118 | bne 2f |
119 | b hardware_interrupt_entry | |
120 | 2: | |
3f639ee8 | 121 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) |
945feb17 | 122 | #endif /* CONFIG_PPC_ISERIES */ |
2d27cfd3 BH |
123 | |
124 | /* Hard enable interrupts */ | |
125 | #ifdef CONFIG_PPC_BOOK3E | |
126 | wrteei 1 | |
127 | #else | |
9994a338 PM |
128 | mfmsr r11 |
129 | ori r11,r11,MSR_EE | |
130 | mtmsrd r11,1 | |
2d27cfd3 | 131 | #endif /* CONFIG_PPC_BOOK3E */ |
9994a338 PM |
132 | |
133 | #ifdef SHOW_SYSCALLS | |
134 | bl .do_show_syscall | |
135 | REST_GPR(0,r1) | |
136 | REST_4GPRS(3,r1) | |
137 | REST_2GPRS(7,r1) | |
138 | addi r9,r1,STACK_FRAME_OVERHEAD | |
139 | #endif | |
140 | clrrdi r11,r1,THREAD_SHIFT | |
9994a338 | 141 | ld r10,TI_FLAGS(r11) |
9994a338 PM |
142 | andi. r11,r10,_TIF_SYSCALL_T_OR_A |
143 | bne- syscall_dotrace | |
144 | syscall_dotrace_cont: | |
145 | cmpldi 0,r0,NR_syscalls | |
146 | bge- syscall_enosys | |
147 | ||
148 | system_call: /* label this so stack traces look sane */ | |
149 | /* | |
150 | * Need to vector to 32 Bit or default sys_call_table here, | |
151 | * based on caller's run-mode / personality. | |
152 | */ | |
153 | ld r11,.SYS_CALL_TABLE@toc(2) | |
154 | andi. r10,r10,_TIF_32BIT | |
155 | beq 15f | |
156 | addi r11,r11,8 /* use 32-bit syscall entries */ | |
157 | clrldi r3,r3,32 | |
158 | clrldi r4,r4,32 | |
159 | clrldi r5,r5,32 | |
160 | clrldi r6,r6,32 | |
161 | clrldi r7,r7,32 | |
162 | clrldi r8,r8,32 | |
163 | 15: | |
164 | slwi r0,r0,4 | |
165 | ldx r10,r11,r0 /* Fetch system call handler [ptr] */ | |
166 | mtctr r10 | |
167 | bctrl /* Call handler */ | |
168 | ||
169 | syscall_exit: | |
401d1f02 | 170 | std r3,RESULT(r1) |
9994a338 | 171 | #ifdef SHOW_SYSCALLS |
9994a338 | 172 | bl .do_show_syscall_exit |
401d1f02 | 173 | ld r3,RESULT(r1) |
9994a338 | 174 | #endif |
9994a338 | 175 | clrrdi r12,r1,THREAD_SHIFT |
9994a338 | 176 | |
9994a338 | 177 | ld r8,_MSR(r1) |
2d27cfd3 BH |
178 | #ifdef CONFIG_PPC_BOOK3S |
179 | /* No MSR:RI on BookE */ | |
9994a338 PM |
180 | andi. r10,r8,MSR_RI |
181 | beq- unrecov_restore | |
2d27cfd3 BH |
182 | #endif |
183 | ||
184 | /* Disable interrupts so current_thread_info()->flags can't change, | |
185 | * and so that we don't get interrupted after loading SRR0/1. | |
186 | */ | |
187 | #ifdef CONFIG_PPC_BOOK3E | |
188 | wrteei 0 | |
189 | #else | |
9994a338 PM |
190 | mfmsr r10 |
191 | rldicl r10,r10,48,1 | |
192 | rotldi r10,r10,16 | |
193 | mtmsrd r10,1 | |
2d27cfd3 BH |
194 | #endif /* CONFIG_PPC_BOOK3E */ |
195 | ||
9994a338 | 196 | ld r9,TI_FLAGS(r12) |
401d1f02 | 197 | li r11,-_LAST_ERRNO |
1bd79336 | 198 | andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK) |
9994a338 | 199 | bne- syscall_exit_work |
401d1f02 DW |
200 | cmpld r3,r11 |
201 | ld r5,_CCR(r1) | |
202 | bge- syscall_error | |
203 | syscall_error_cont: | |
9994a338 PM |
204 | ld r7,_NIP(r1) |
205 | stdcx. r0,0,r1 /* to clear the reservation */ | |
206 | andi. r6,r8,MSR_PR | |
207 | ld r4,_LINK(r1) | |
e56a6e20 PM |
208 | /* |
209 | * Clear RI before restoring r13. If we are returning to | |
210 | * userspace and we take an exception after restoring r13, | |
211 | * we end up corrupting the userspace r13 value. | |
212 | */ | |
2d27cfd3 BH |
213 | #ifdef CONFIG_PPC_BOOK3S |
214 | /* No MSR:RI on BookE */ | |
e56a6e20 PM |
215 | li r12,MSR_RI |
216 | andc r11,r10,r12 | |
217 | mtmsrd r11,1 /* clear MSR.RI */ | |
2d27cfd3 BH |
218 | #endif /* CONFIG_PPC_BOOK3S */ |
219 | ||
c6622f63 PM |
220 | beq- 1f |
221 | ACCOUNT_CPU_USER_EXIT(r11, r12) | |
222 | ld r13,GPR13(r1) /* only restore r13 if returning to usermode */ | |
9994a338 | 223 | 1: ld r2,GPR2(r1) |
9994a338 PM |
224 | ld r1,GPR1(r1) |
225 | mtlr r4 | |
226 | mtcr r5 | |
227 | mtspr SPRN_SRR0,r7 | |
228 | mtspr SPRN_SRR1,r8 | |
2d27cfd3 | 229 | RFI |
9994a338 PM |
230 | b . /* prevent speculative execution */ |
231 | ||
401d1f02 | 232 | syscall_error: |
9994a338 | 233 | oris r5,r5,0x1000 /* Set SO bit in CR */ |
401d1f02 | 234 | neg r3,r3 |
9994a338 PM |
235 | std r5,_CCR(r1) |
236 | b syscall_error_cont | |
401d1f02 | 237 | |
9994a338 PM |
238 | /* Traced system call support */ |
239 | syscall_dotrace: | |
240 | bl .save_nvgprs | |
241 | addi r3,r1,STACK_FRAME_OVERHEAD | |
242 | bl .do_syscall_trace_enter | |
4f72c427 RM |
243 | /* |
244 | * Restore argument registers possibly just changed. | |
245 | * We use the return value of do_syscall_trace_enter | |
246 | * for the call number to look up in the table (r0). | |
247 | */ | |
248 | mr r0,r3 | |
9994a338 PM |
249 | ld r3,GPR3(r1) |
250 | ld r4,GPR4(r1) | |
251 | ld r5,GPR5(r1) | |
252 | ld r6,GPR6(r1) | |
253 | ld r7,GPR7(r1) | |
254 | ld r8,GPR8(r1) | |
255 | addi r9,r1,STACK_FRAME_OVERHEAD | |
256 | clrrdi r10,r1,THREAD_SHIFT | |
257 | ld r10,TI_FLAGS(r10) | |
258 | b syscall_dotrace_cont | |
259 | ||
401d1f02 DW |
260 | syscall_enosys: |
261 | li r3,-ENOSYS | |
262 | b syscall_exit | |
263 | ||
264 | syscall_exit_work: | |
265 | /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr. | |
266 | If TIF_NOERROR is set, just save r3 as it is. */ | |
267 | ||
268 | andi. r0,r9,_TIF_RESTOREALL | |
1bd79336 PM |
269 | beq+ 0f |
270 | REST_NVGPRS(r1) | |
271 | b 2f | |
272 | 0: cmpld r3,r11 /* r10 is -LAST_ERRNO */ | |
401d1f02 DW |
273 | blt+ 1f |
274 | andi. r0,r9,_TIF_NOERROR | |
275 | bne- 1f | |
276 | ld r5,_CCR(r1) | |
277 | neg r3,r3 | |
278 | oris r5,r5,0x1000 /* Set SO bit in CR */ | |
279 | std r5,_CCR(r1) | |
280 | 1: std r3,GPR3(r1) | |
281 | 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK) | |
282 | beq 4f | |
283 | ||
1bd79336 | 284 | /* Clear per-syscall TIF flags if any are set. */ |
401d1f02 DW |
285 | |
286 | li r11,_TIF_PERSYSCALL_MASK | |
287 | addi r12,r12,TI_FLAGS | |
288 | 3: ldarx r10,0,r12 | |
289 | andc r10,r10,r11 | |
290 | stdcx. r10,0,r12 | |
291 | bne- 3b | |
292 | subi r12,r12,TI_FLAGS | |
1bd79336 PM |
293 | |
294 | 4: /* Anything else left to do? */ | |
295 | andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP) | |
401d1f02 DW |
296 | beq .ret_from_except_lite |
297 | ||
298 | /* Re-enable interrupts */ | |
2d27cfd3 BH |
299 | #ifdef CONFIG_PPC_BOOK3E |
300 | wrteei 1 | |
301 | #else | |
401d1f02 DW |
302 | mfmsr r10 |
303 | ori r10,r10,MSR_EE | |
304 | mtmsrd r10,1 | |
2d27cfd3 | 305 | #endif /* CONFIG_PPC_BOOK3E */ |
401d1f02 | 306 | |
1bd79336 | 307 | bl .save_nvgprs |
9994a338 PM |
308 | addi r3,r1,STACK_FRAME_OVERHEAD |
309 | bl .do_syscall_trace_leave | |
1bd79336 | 310 | b .ret_from_except |
9994a338 PM |
311 | |
312 | /* Save non-volatile GPRs, if not already saved. */ | |
313 | _GLOBAL(save_nvgprs) | |
314 | ld r11,_TRAP(r1) | |
315 | andi. r0,r11,1 | |
316 | beqlr- | |
317 | SAVE_NVGPRS(r1) | |
318 | clrrdi r0,r11,1 | |
319 | std r0,_TRAP(r1) | |
320 | blr | |
321 | ||
401d1f02 | 322 | |
9994a338 PM |
323 | /* |
324 | * The sigsuspend and rt_sigsuspend system calls can call do_signal | |
325 | * and thus put the process into the stopped state where we might | |
326 | * want to examine its user state with ptrace. Therefore we need | |
327 | * to save all the nonvolatile registers (r14 - r31) before calling | |
328 | * the C code. Similarly, fork, vfork and clone need the full | |
329 | * register state on the stack so that it can be copied to the child. | |
330 | */ | |
9994a338 PM |
331 | |
332 | _GLOBAL(ppc_fork) | |
333 | bl .save_nvgprs | |
334 | bl .sys_fork | |
335 | b syscall_exit | |
336 | ||
337 | _GLOBAL(ppc_vfork) | |
338 | bl .save_nvgprs | |
339 | bl .sys_vfork | |
340 | b syscall_exit | |
341 | ||
342 | _GLOBAL(ppc_clone) | |
343 | bl .save_nvgprs | |
344 | bl .sys_clone | |
345 | b syscall_exit | |
346 | ||
1bd79336 PM |
347 | _GLOBAL(ppc32_swapcontext) |
348 | bl .save_nvgprs | |
349 | bl .compat_sys_swapcontext | |
350 | b syscall_exit | |
351 | ||
352 | _GLOBAL(ppc64_swapcontext) | |
353 | bl .save_nvgprs | |
354 | bl .sys_swapcontext | |
355 | b syscall_exit | |
356 | ||
9994a338 PM |
357 | _GLOBAL(ret_from_fork) |
358 | bl .schedule_tail | |
359 | REST_NVGPRS(r1) | |
360 | li r3,0 | |
361 | b syscall_exit | |
362 | ||
363 | /* | |
364 | * This routine switches between two different tasks. The process | |
365 | * state of one is saved on its kernel stack. Then the state | |
366 | * of the other is restored from its kernel stack. The memory | |
367 | * management hardware is updated to the second process's state. | |
368 | * Finally, we can return to the second process, via ret_from_except. | |
369 | * On entry, r3 points to the THREAD for the current task, r4 | |
370 | * points to the THREAD for the new task. | |
371 | * | |
372 | * Note: there are two ways to get to the "going out" portion | |
373 | * of this code; either by coming in via the entry (_switch) | |
374 | * or via "fork" which must set up an environment equivalent | |
375 | * to the "_switch" path. If you change this you'll have to change | |
376 | * the fork code also. | |
377 | * | |
378 | * The code which creates the new task context is in 'copy_thread' | |
2ef9481e | 379 | * in arch/powerpc/kernel/process.c |
9994a338 PM |
380 | */ |
381 | .align 7 | |
382 | _GLOBAL(_switch) | |
383 | mflr r0 | |
384 | std r0,16(r1) | |
385 | stdu r1,-SWITCH_FRAME_SIZE(r1) | |
386 | /* r3-r13 are caller saved -- Cort */ | |
387 | SAVE_8GPRS(14, r1) | |
388 | SAVE_10GPRS(22, r1) | |
389 | mflr r20 /* Return to switch caller */ | |
390 | mfmsr r22 | |
391 | li r0, MSR_FP | |
ce48b210 MN |
392 | #ifdef CONFIG_VSX |
393 | BEGIN_FTR_SECTION | |
394 | oris r0,r0,MSR_VSX@h /* Disable VSX */ | |
395 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
396 | #endif /* CONFIG_VSX */ | |
9994a338 PM |
397 | #ifdef CONFIG_ALTIVEC |
398 | BEGIN_FTR_SECTION | |
399 | oris r0,r0,MSR_VEC@h /* Disable altivec */ | |
400 | mfspr r24,SPRN_VRSAVE /* save vrsave register value */ | |
401 | std r24,THREAD_VRSAVE(r3) | |
402 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
403 | #endif /* CONFIG_ALTIVEC */ | |
404 | and. r0,r0,r22 | |
405 | beq+ 1f | |
406 | andc r22,r22,r0 | |
2d27cfd3 | 407 | MTMSRD(r22) |
9994a338 PM |
408 | isync |
409 | 1: std r20,_NIP(r1) | |
410 | mfcr r23 | |
411 | std r23,_CCR(r1) | |
412 | std r1,KSP(r3) /* Set old stack pointer */ | |
413 | ||
414 | #ifdef CONFIG_SMP | |
415 | /* We need a sync somewhere here to make sure that if the | |
416 | * previous task gets rescheduled on another CPU, it sees all | |
417 | * stores it has performed on this one. | |
418 | */ | |
419 | sync | |
420 | #endif /* CONFIG_SMP */ | |
421 | ||
422 | addi r6,r4,-THREAD /* Convert THREAD to 'current' */ | |
423 | std r6,PACACURRENT(r13) /* Set new 'current' */ | |
424 | ||
425 | ld r8,KSP(r4) /* new stack pointer */ | |
2d27cfd3 | 426 | #ifdef CONFIG_PPC_BOOK3S |
1189be65 | 427 | BEGIN_FTR_SECTION |
c230328d | 428 | BEGIN_FTR_SECTION_NESTED(95) |
9994a338 PM |
429 | clrrdi r6,r8,28 /* get its ESID */ |
430 | clrrdi r9,r1,28 /* get current sp ESID */ | |
c230328d | 431 | FTR_SECTION_ELSE_NESTED(95) |
1189be65 PM |
432 | clrrdi r6,r8,40 /* get its 1T ESID */ |
433 | clrrdi r9,r1,40 /* get current sp 1T ESID */ | |
c230328d ME |
434 | ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_1T_SEGMENT, 95) |
435 | FTR_SECTION_ELSE | |
436 | b 2f | |
437 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_SLB) | |
9994a338 PM |
438 | clrldi. r0,r6,2 /* is new ESID c00000000? */ |
439 | cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */ | |
440 | cror eq,4*cr1+eq,eq | |
441 | beq 2f /* if yes, don't slbie it */ | |
442 | ||
443 | /* Bolt in the new stack SLB entry */ | |
444 | ld r7,KSP_VSID(r4) /* Get new stack's VSID */ | |
445 | oris r0,r6,(SLB_ESID_V)@h | |
446 | ori r0,r0,(SLB_NUM_BOLTED-1)@l | |
1189be65 PM |
447 | BEGIN_FTR_SECTION |
448 | li r9,MMU_SEGSIZE_1T /* insert B field */ | |
449 | oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h | |
450 | rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0 | |
451 | END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT) | |
2f6093c8 | 452 | |
00efee7d MN |
453 | /* Update the last bolted SLB. No write barriers are needed |
454 | * here, provided we only update the current CPU's SLB shadow | |
455 | * buffer. | |
456 | */ | |
2f6093c8 | 457 | ld r9,PACA_SLBSHADOWPTR(r13) |
11a27ad7 MN |
458 | li r12,0 |
459 | std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */ | |
460 | std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */ | |
461 | std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */ | |
2f6093c8 | 462 | |
f66bce5e OJ |
463 | /* No need to check for CPU_FTR_NO_SLBIE_B here, since when |
464 | * we have 1TB segments, the only CPUs known to have the errata | |
465 | * only support less than 1TB of system memory and we'll never | |
466 | * actually hit this code path. | |
467 | */ | |
468 | ||
9994a338 PM |
469 | slbie r6 |
470 | slbie r6 /* Workaround POWER5 < DD2.1 issue */ | |
471 | slbmte r7,r0 | |
472 | isync | |
9994a338 | 473 | 2: |
2d27cfd3 BH |
474 | #endif /* !CONFIG_PPC_BOOK3S */ |
475 | ||
9994a338 PM |
476 | clrrdi r7,r8,THREAD_SHIFT /* base of new stack */ |
477 | /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE | |
478 | because we don't need to leave the 288-byte ABI gap at the | |
479 | top of the kernel stack. */ | |
480 | addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE | |
481 | ||
482 | mr r1,r8 /* start using new stack pointer */ | |
483 | std r7,PACAKSAVE(r13) | |
484 | ||
485 | ld r6,_CCR(r1) | |
486 | mtcrf 0xFF,r6 | |
487 | ||
488 | #ifdef CONFIG_ALTIVEC | |
489 | BEGIN_FTR_SECTION | |
490 | ld r0,THREAD_VRSAVE(r4) | |
491 | mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */ | |
492 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
493 | #endif /* CONFIG_ALTIVEC */ | |
494 | ||
495 | /* r3-r13 are destroyed -- Cort */ | |
496 | REST_8GPRS(14, r1) | |
497 | REST_10GPRS(22, r1) | |
498 | ||
499 | /* convert old thread to its task_struct for return value */ | |
500 | addi r3,r3,-THREAD | |
501 | ld r7,_NIP(r1) /* Return to _switch caller in new task */ | |
502 | mtlr r7 | |
503 | addi r1,r1,SWITCH_FRAME_SIZE | |
504 | blr | |
505 | ||
506 | .align 7 | |
507 | _GLOBAL(ret_from_except) | |
508 | ld r11,_TRAP(r1) | |
509 | andi. r0,r11,1 | |
510 | bne .ret_from_except_lite | |
511 | REST_NVGPRS(r1) | |
512 | ||
513 | _GLOBAL(ret_from_except_lite) | |
514 | /* | |
515 | * Disable interrupts so that current_thread_info()->flags | |
516 | * can't change between when we test it and when we return | |
517 | * from the interrupt. | |
518 | */ | |
2d27cfd3 BH |
519 | #ifdef CONFIG_PPC_BOOK3E |
520 | wrteei 0 | |
521 | #else | |
9994a338 PM |
522 | mfmsr r10 /* Get current interrupt state */ |
523 | rldicl r9,r10,48,1 /* clear MSR_EE */ | |
524 | rotldi r9,r9,16 | |
525 | mtmsrd r9,1 /* Update machine state */ | |
2d27cfd3 | 526 | #endif /* CONFIG_PPC_BOOK3E */ |
9994a338 PM |
527 | |
528 | #ifdef CONFIG_PREEMPT | |
529 | clrrdi r9,r1,THREAD_SHIFT /* current_thread_info() */ | |
530 | li r0,_TIF_NEED_RESCHED /* bits to check */ | |
531 | ld r3,_MSR(r1) | |
532 | ld r4,TI_FLAGS(r9) | |
533 | /* Move MSR_PR bit in r3 to _TIF_SIGPENDING position in r0 */ | |
534 | rlwimi r0,r3,32+TIF_SIGPENDING-MSR_PR_LG,_TIF_SIGPENDING | |
535 | and. r0,r4,r0 /* check NEED_RESCHED and maybe SIGPENDING */ | |
536 | bne do_work | |
537 | ||
538 | #else /* !CONFIG_PREEMPT */ | |
539 | ld r3,_MSR(r1) /* Returning to user mode? */ | |
540 | andi. r3,r3,MSR_PR | |
541 | beq restore /* if not, just restore regs and return */ | |
542 | ||
543 | /* Check current_thread_info()->flags */ | |
544 | clrrdi r9,r1,THREAD_SHIFT | |
545 | ld r4,TI_FLAGS(r9) | |
546 | andi. r0,r4,_TIF_USER_WORK_MASK | |
547 | bne do_work | |
548 | #endif | |
549 | ||
550 | restore: | |
3f639ee8 | 551 | BEGIN_FW_FTR_SECTION |
01f3880d ME |
552 | ld r5,SOFTE(r1) |
553 | FW_FTR_SECTION_ELSE | |
554 | b iseries_check_pending_irqs | |
555 | ALT_FW_FTR_SECTION_END_IFCLR(FW_FEATURE_ISERIES) | |
556 | 2: | |
945feb17 | 557 | TRACE_AND_RESTORE_IRQ(r5); |
9994a338 | 558 | |
cdd6c482 IM |
559 | #ifdef CONFIG_PERF_EVENTS |
560 | /* check paca->perf_event_pending if we're enabling ints */ | |
93a6d3ce PM |
561 | lbz r3,PACAPERFPEND(r13) |
562 | and. r3,r3,r5 | |
563 | beq 27f | |
cdd6c482 | 564 | bl .perf_event_do_pending |
93a6d3ce | 565 | 27: |
cdd6c482 | 566 | #endif /* CONFIG_PERF_EVENTS */ |
93a6d3ce | 567 | |
e56a6e20 | 568 | /* extract EE bit and use it to restore paca->hard_enabled */ |
9994a338 | 569 | ld r3,_MSR(r1) |
e56a6e20 PM |
570 | rldicl r4,r3,49,63 /* r0 = (r3 >> 15) & 1 */ |
571 | stb r4,PACAHARDIRQEN(r13) | |
572 | ||
2d27cfd3 BH |
573 | #ifdef CONFIG_PPC_BOOK3E |
574 | b .exception_return_book3e | |
575 | #else | |
e56a6e20 PM |
576 | ld r4,_CTR(r1) |
577 | ld r0,_LINK(r1) | |
578 | mtctr r4 | |
579 | mtlr r0 | |
580 | ld r4,_XER(r1) | |
581 | mtspr SPRN_XER,r4 | |
582 | ||
583 | REST_8GPRS(5, r1) | |
584 | ||
9994a338 PM |
585 | andi. r0,r3,MSR_RI |
586 | beq- unrecov_restore | |
587 | ||
e56a6e20 | 588 | stdcx. r0,0,r1 /* to clear the reservation */ |
b0a779de | 589 | |
e56a6e20 PM |
590 | /* |
591 | * Clear RI before restoring r13. If we are returning to | |
592 | * userspace and we take an exception after restoring r13, | |
593 | * we end up corrupting the userspace r13 value. | |
594 | */ | |
595 | mfmsr r4 | |
596 | andc r4,r4,r0 /* r0 contains MSR_RI here */ | |
597 | mtmsrd r4,1 | |
9994a338 PM |
598 | |
599 | /* | |
600 | * r13 is our per cpu area, only restore it if we are returning to | |
601 | * userspace | |
602 | */ | |
e56a6e20 | 603 | andi. r0,r3,MSR_PR |
9994a338 | 604 | beq 1f |
e56a6e20 | 605 | ACCOUNT_CPU_USER_EXIT(r2, r4) |
9994a338 PM |
606 | REST_GPR(13, r1) |
607 | 1: | |
e56a6e20 | 608 | mtspr SPRN_SRR1,r3 |
9994a338 PM |
609 | |
610 | ld r2,_CCR(r1) | |
611 | mtcrf 0xFF,r2 | |
612 | ld r2,_NIP(r1) | |
613 | mtspr SPRN_SRR0,r2 | |
614 | ||
615 | ld r0,GPR0(r1) | |
616 | ld r2,GPR2(r1) | |
617 | ld r3,GPR3(r1) | |
618 | ld r4,GPR4(r1) | |
619 | ld r1,GPR1(r1) | |
620 | ||
621 | rfid | |
622 | b . /* prevent speculative execution */ | |
623 | ||
2d27cfd3 BH |
624 | #endif /* CONFIG_PPC_BOOK3E */ |
625 | ||
01f3880d ME |
626 | iseries_check_pending_irqs: |
627 | #ifdef CONFIG_PPC_ISERIES | |
628 | ld r5,SOFTE(r1) | |
629 | cmpdi 0,r5,0 | |
630 | beq 2b | |
631 | /* Check for pending interrupts (iSeries) */ | |
632 | ld r3,PACALPPACAPTR(r13) | |
633 | ld r3,LPPACAANYINT(r3) | |
634 | cmpdi r3,0 | |
635 | beq+ 2b /* skip do_IRQ if no interrupts */ | |
636 | ||
637 | li r3,0 | |
638 | stb r3,PACASOFTIRQEN(r13) /* ensure we are soft-disabled */ | |
639 | #ifdef CONFIG_TRACE_IRQFLAGS | |
640 | bl .trace_hardirqs_off | |
641 | mfmsr r10 | |
642 | #endif | |
643 | ori r10,r10,MSR_EE | |
644 | mtmsrd r10 /* hard-enable again */ | |
645 | addi r3,r1,STACK_FRAME_OVERHEAD | |
646 | bl .do_IRQ | |
647 | b .ret_from_except_lite /* loop back and handle more */ | |
648 | #endif | |
649 | ||
9994a338 PM |
650 | do_work: |
651 | #ifdef CONFIG_PREEMPT | |
652 | andi. r0,r3,MSR_PR /* Returning to user mode? */ | |
653 | bne user_work | |
654 | /* Check that preempt_count() == 0 and interrupts are enabled */ | |
655 | lwz r8,TI_PREEMPT(r9) | |
656 | cmpwi cr1,r8,0 | |
9994a338 PM |
657 | ld r0,SOFTE(r1) |
658 | cmpdi r0,0 | |
9994a338 PM |
659 | crandc eq,cr1*4+eq,eq |
660 | bne restore | |
4f917ba3 BH |
661 | |
662 | /* Here we are preempting the current task. | |
663 | * | |
664 | * Ensure interrupts are soft-disabled. We also properly mark | |
665 | * the PACA to reflect the fact that they are hard-disabled | |
666 | * and trace the change | |
945feb17 | 667 | */ |
4f917ba3 | 668 | li r0,0 |
d04c56f7 PM |
669 | stb r0,PACASOFTIRQEN(r13) |
670 | stb r0,PACAHARDIRQEN(r13) | |
4f917ba3 BH |
671 | TRACE_DISABLE_INTS |
672 | ||
673 | /* Call the scheduler with soft IRQs off */ | |
674 | 1: bl .preempt_schedule_irq | |
675 | ||
676 | /* Hard-disable interrupts again (and update PACA) */ | |
2d27cfd3 | 677 | #ifdef CONFIG_PPC_BOOK3E |
2d27cfd3 BH |
678 | wrteei 0 |
679 | #else | |
9994a338 | 680 | mfmsr r10 |
4f917ba3 | 681 | rldicl r10,r10,48,1 |
9994a338 PM |
682 | rotldi r10,r10,16 |
683 | mtmsrd r10,1 | |
2d27cfd3 | 684 | #endif /* CONFIG_PPC_BOOK3E */ |
4f917ba3 BH |
685 | li r0,0 |
686 | stb r0,PACAHARDIRQEN(r13) | |
687 | ||
688 | /* Re-test flags and eventually loop */ | |
689 | clrrdi r9,r1,THREAD_SHIFT | |
9994a338 PM |
690 | ld r4,TI_FLAGS(r9) |
691 | andi. r0,r4,_TIF_NEED_RESCHED | |
692 | bne 1b | |
693 | b restore | |
694 | ||
695 | user_work: | |
4f917ba3 BH |
696 | #endif /* CONFIG_PREEMPT */ |
697 | ||
9994a338 | 698 | /* Enable interrupts */ |
2d27cfd3 BH |
699 | #ifdef CONFIG_PPC_BOOK3E |
700 | wrteei 1 | |
701 | #else | |
9994a338 PM |
702 | ori r10,r10,MSR_EE |
703 | mtmsrd r10,1 | |
2d27cfd3 | 704 | #endif /* CONFIG_PPC_BOOK3E */ |
9994a338 PM |
705 | |
706 | andi. r0,r4,_TIF_NEED_RESCHED | |
707 | beq 1f | |
708 | bl .schedule | |
709 | b .ret_from_except_lite | |
710 | ||
711 | 1: bl .save_nvgprs | |
7d6d637d | 712 | addi r3,r1,STACK_FRAME_OVERHEAD |
9994a338 PM |
713 | bl .do_signal |
714 | b .ret_from_except | |
715 | ||
716 | unrecov_restore: | |
717 | addi r3,r1,STACK_FRAME_OVERHEAD | |
718 | bl .unrecoverable_exception | |
719 | b unrecov_restore | |
720 | ||
721 | #ifdef CONFIG_PPC_RTAS | |
722 | /* | |
723 | * On CHRP, the Run-Time Abstraction Services (RTAS) have to be | |
724 | * called with the MMU off. | |
725 | * | |
726 | * In addition, we need to be in 32b mode, at least for now. | |
727 | * | |
728 | * Note: r3 is an input parameter to rtas, so don't trash it... | |
729 | */ | |
730 | _GLOBAL(enter_rtas) | |
731 | mflr r0 | |
732 | std r0,16(r1) | |
733 | stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */ | |
734 | ||
735 | /* Because RTAS is running in 32b mode, it clobbers the high order half | |
736 | * of all registers that it saves. We therefore save those registers | |
737 | * RTAS might touch to the stack. (r0, r3-r13 are caller saved) | |
738 | */ | |
739 | SAVE_GPR(2, r1) /* Save the TOC */ | |
740 | SAVE_GPR(13, r1) /* Save paca */ | |
741 | SAVE_8GPRS(14, r1) /* Save the non-volatiles */ | |
742 | SAVE_10GPRS(22, r1) /* ditto */ | |
743 | ||
744 | mfcr r4 | |
745 | std r4,_CCR(r1) | |
746 | mfctr r5 | |
747 | std r5,_CTR(r1) | |
748 | mfspr r6,SPRN_XER | |
749 | std r6,_XER(r1) | |
750 | mfdar r7 | |
751 | std r7,_DAR(r1) | |
752 | mfdsisr r8 | |
753 | std r8,_DSISR(r1) | |
9994a338 | 754 | |
9fe901d1 MK |
755 | /* Temporary workaround to clear CR until RTAS can be modified to |
756 | * ignore all bits. | |
757 | */ | |
758 | li r0,0 | |
759 | mtcr r0 | |
760 | ||
007d88d0 | 761 | #ifdef CONFIG_BUG |
9994a338 PM |
762 | /* There is no way it is acceptable to get here with interrupts enabled, |
763 | * check it with the asm equivalent of WARN_ON | |
764 | */ | |
d04c56f7 | 765 | lbz r0,PACASOFTIRQEN(r13) |
9994a338 | 766 | 1: tdnei r0,0 |
007d88d0 DW |
767 | EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING |
768 | #endif | |
769 | ||
d04c56f7 PM |
770 | /* Hard-disable interrupts */ |
771 | mfmsr r6 | |
772 | rldicl r7,r6,48,1 | |
773 | rotldi r7,r7,16 | |
774 | mtmsrd r7,1 | |
775 | ||
9994a338 PM |
776 | /* Unfortunately, the stack pointer and the MSR are also clobbered, |
777 | * so they are saved in the PACA which allows us to restore | |
778 | * our original state after RTAS returns. | |
779 | */ | |
780 | std r1,PACAR1(r13) | |
781 | std r6,PACASAVEDMSR(r13) | |
782 | ||
783 | /* Setup our real return addr */ | |
e58c3495 DG |
784 | LOAD_REG_ADDR(r4,.rtas_return_loc) |
785 | clrldi r4,r4,2 /* convert to realmode address */ | |
9994a338 PM |
786 | mtlr r4 |
787 | ||
788 | li r0,0 | |
789 | ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI | |
790 | andc r0,r6,r0 | |
791 | ||
792 | li r9,1 | |
793 | rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG) | |
794 | ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP | |
795 | andc r6,r0,r9 | |
796 | ori r6,r6,MSR_RI | |
797 | sync /* disable interrupts so SRR0/1 */ | |
798 | mtmsrd r0 /* don't get trashed */ | |
799 | ||
e58c3495 | 800 | LOAD_REG_ADDR(r4, rtas) |
9994a338 PM |
801 | ld r5,RTASENTRY(r4) /* get the rtas->entry value */ |
802 | ld r4,RTASBASE(r4) /* get the rtas->base value */ | |
803 | ||
804 | mtspr SPRN_SRR0,r5 | |
805 | mtspr SPRN_SRR1,r6 | |
806 | rfid | |
807 | b . /* prevent speculative execution */ | |
808 | ||
809 | _STATIC(rtas_return_loc) | |
810 | /* relocation is off at this point */ | |
ee43eb78 | 811 | mfspr r4,SPRN_SPRG_PACA /* Get PACA */ |
e58c3495 | 812 | clrldi r4,r4,2 /* convert to realmode address */ |
9994a338 | 813 | |
e31aa453 PM |
814 | bcl 20,31,$+4 |
815 | 0: mflr r3 | |
816 | ld r3,(1f-0b)(r3) /* get &.rtas_restore_regs */ | |
817 | ||
9994a338 PM |
818 | mfmsr r6 |
819 | li r0,MSR_RI | |
820 | andc r6,r6,r0 | |
821 | sync | |
822 | mtmsrd r6 | |
823 | ||
824 | ld r1,PACAR1(r4) /* Restore our SP */ | |
9994a338 PM |
825 | ld r4,PACASAVEDMSR(r4) /* Restore our MSR */ |
826 | ||
827 | mtspr SPRN_SRR0,r3 | |
828 | mtspr SPRN_SRR1,r4 | |
829 | rfid | |
830 | b . /* prevent speculative execution */ | |
831 | ||
e31aa453 PM |
832 | .align 3 |
833 | 1: .llong .rtas_restore_regs | |
834 | ||
9994a338 PM |
835 | _STATIC(rtas_restore_regs) |
836 | /* relocation is on at this point */ | |
837 | REST_GPR(2, r1) /* Restore the TOC */ | |
838 | REST_GPR(13, r1) /* Restore paca */ | |
839 | REST_8GPRS(14, r1) /* Restore the non-volatiles */ | |
840 | REST_10GPRS(22, r1) /* ditto */ | |
841 | ||
ee43eb78 | 842 | mfspr r13,SPRN_SPRG_PACA |
9994a338 PM |
843 | |
844 | ld r4,_CCR(r1) | |
845 | mtcr r4 | |
846 | ld r5,_CTR(r1) | |
847 | mtctr r5 | |
848 | ld r6,_XER(r1) | |
849 | mtspr SPRN_XER,r6 | |
850 | ld r7,_DAR(r1) | |
851 | mtdar r7 | |
852 | ld r8,_DSISR(r1) | |
853 | mtdsisr r8 | |
9994a338 PM |
854 | |
855 | addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */ | |
856 | ld r0,16(r1) /* get return address */ | |
857 | ||
858 | mtlr r0 | |
859 | blr /* return to caller */ | |
860 | ||
861 | #endif /* CONFIG_PPC_RTAS */ | |
862 | ||
9994a338 PM |
863 | _GLOBAL(enter_prom) |
864 | mflr r0 | |
865 | std r0,16(r1) | |
866 | stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */ | |
867 | ||
868 | /* Because PROM is running in 32b mode, it clobbers the high order half | |
869 | * of all registers that it saves. We therefore save those registers | |
870 | * PROM might touch to the stack. (r0, r3-r13 are caller saved) | |
871 | */ | |
6c171994 | 872 | SAVE_GPR(2, r1) |
9994a338 PM |
873 | SAVE_GPR(13, r1) |
874 | SAVE_8GPRS(14, r1) | |
875 | SAVE_10GPRS(22, r1) | |
6c171994 | 876 | mfcr r10 |
9994a338 | 877 | mfmsr r11 |
6c171994 | 878 | std r10,_CCR(r1) |
9994a338 PM |
879 | std r11,_MSR(r1) |
880 | ||
881 | /* Get the PROM entrypoint */ | |
6c171994 | 882 | mtlr r4 |
9994a338 PM |
883 | |
884 | /* Switch MSR to 32 bits mode | |
885 | */ | |
2d27cfd3 BH |
886 | #ifdef CONFIG_PPC_BOOK3E |
887 | rlwinm r11,r11,0,1,31 | |
888 | mtmsr r11 | |
889 | #else /* CONFIG_PPC_BOOK3E */ | |
9994a338 PM |
890 | mfmsr r11 |
891 | li r12,1 | |
892 | rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG) | |
893 | andc r11,r11,r12 | |
894 | li r12,1 | |
895 | rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG) | |
896 | andc r11,r11,r12 | |
897 | mtmsrd r11 | |
2d27cfd3 | 898 | #endif /* CONFIG_PPC_BOOK3E */ |
9994a338 PM |
899 | isync |
900 | ||
6c171994 | 901 | /* Enter PROM here... */ |
9994a338 PM |
902 | blrl |
903 | ||
904 | /* Just make sure that r1 top 32 bits didn't get | |
905 | * corrupt by OF | |
906 | */ | |
907 | rldicl r1,r1,0,32 | |
908 | ||
909 | /* Restore the MSR (back to 64 bits) */ | |
910 | ld r0,_MSR(r1) | |
6c171994 | 911 | MTMSRD(r0) |
9994a338 PM |
912 | isync |
913 | ||
914 | /* Restore other registers */ | |
915 | REST_GPR(2, r1) | |
916 | REST_GPR(13, r1) | |
917 | REST_8GPRS(14, r1) | |
918 | REST_10GPRS(22, r1) | |
919 | ld r4,_CCR(r1) | |
920 | mtcr r4 | |
9994a338 PM |
921 | |
922 | addi r1,r1,PROM_FRAME_SIZE | |
923 | ld r0,16(r1) | |
924 | mtlr r0 | |
925 | blr | |
4e491d14 | 926 | |
606576ce | 927 | #ifdef CONFIG_FUNCTION_TRACER |
4e491d14 SR |
928 | #ifdef CONFIG_DYNAMIC_FTRACE |
929 | _GLOBAL(mcount) | |
930 | _GLOBAL(_mcount) | |
4e491d14 SR |
931 | blr |
932 | ||
933 | _GLOBAL(ftrace_caller) | |
934 | /* Taken from output of objdump from lib64/glibc */ | |
935 | mflr r3 | |
936 | ld r11, 0(r1) | |
937 | stdu r1, -112(r1) | |
938 | std r3, 128(r1) | |
939 | ld r4, 16(r11) | |
395a59d0 | 940 | subi r3, r3, MCOUNT_INSN_SIZE |
4e491d14 SR |
941 | .globl ftrace_call |
942 | ftrace_call: | |
943 | bl ftrace_stub | |
944 | nop | |
46542888 SR |
945 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
946 | .globl ftrace_graph_call | |
947 | ftrace_graph_call: | |
948 | b ftrace_graph_stub | |
949 | _GLOBAL(ftrace_graph_stub) | |
950 | #endif | |
4e491d14 SR |
951 | ld r0, 128(r1) |
952 | mtlr r0 | |
953 | addi r1, r1, 112 | |
954 | _GLOBAL(ftrace_stub) | |
955 | blr | |
956 | #else | |
957 | _GLOBAL(mcount) | |
958 | blr | |
959 | ||
960 | _GLOBAL(_mcount) | |
961 | /* Taken from output of objdump from lib64/glibc */ | |
962 | mflr r3 | |
963 | ld r11, 0(r1) | |
964 | stdu r1, -112(r1) | |
965 | std r3, 128(r1) | |
966 | ld r4, 16(r11) | |
967 | ||
395a59d0 | 968 | subi r3, r3, MCOUNT_INSN_SIZE |
4e491d14 SR |
969 | LOAD_REG_ADDR(r5,ftrace_trace_function) |
970 | ld r5,0(r5) | |
971 | ld r5,0(r5) | |
972 | mtctr r5 | |
973 | bctrl | |
4e491d14 | 974 | nop |
6794c782 SR |
975 | |
976 | ||
977 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | |
978 | b ftrace_graph_caller | |
979 | #endif | |
4e491d14 SR |
980 | ld r0, 128(r1) |
981 | mtlr r0 | |
982 | addi r1, r1, 112 | |
983 | _GLOBAL(ftrace_stub) | |
984 | blr | |
985 | ||
6794c782 SR |
986 | #endif /* CONFIG_DYNAMIC_FTRACE */ |
987 | ||
988 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | |
46542888 | 989 | _GLOBAL(ftrace_graph_caller) |
6794c782 SR |
990 | /* load r4 with local address */ |
991 | ld r4, 128(r1) | |
992 | subi r4, r4, MCOUNT_INSN_SIZE | |
993 | ||
994 | /* get the parent address */ | |
995 | ld r11, 112(r1) | |
996 | addi r3, r11, 16 | |
997 | ||
998 | bl .prepare_ftrace_return | |
999 | nop | |
1000 | ||
1001 | ld r0, 128(r1) | |
1002 | mtlr r0 | |
1003 | addi r1, r1, 112 | |
1004 | blr | |
1005 | ||
1006 | _GLOBAL(return_to_handler) | |
bb725340 SR |
1007 | /* need to save return values */ |
1008 | std r4, -24(r1) | |
1009 | std r3, -16(r1) | |
1010 | std r31, -8(r1) | |
1011 | mr r31, r1 | |
1012 | stdu r1, -112(r1) | |
1013 | ||
1014 | bl .ftrace_return_to_handler | |
1015 | nop | |
1016 | ||
1017 | /* return value has real return address */ | |
1018 | mtlr r3 | |
1019 | ||
1020 | ld r1, 0(r1) | |
1021 | ld r4, -24(r1) | |
1022 | ld r3, -16(r1) | |
1023 | ld r31, -8(r1) | |
1024 | ||
1025 | /* Jump back to real return address */ | |
1026 | blr | |
1027 | ||
1028 | _GLOBAL(mod_return_to_handler) | |
6794c782 SR |
1029 | /* need to save return values */ |
1030 | std r4, -32(r1) | |
1031 | std r3, -24(r1) | |
1032 | /* save TOC */ | |
1033 | std r2, -16(r1) | |
1034 | std r31, -8(r1) | |
1035 | mr r31, r1 | |
1036 | stdu r1, -112(r1) | |
1037 | ||
bb725340 SR |
1038 | /* |
1039 | * We are in a module using the module's TOC. | |
1040 | * Switch to our TOC to run inside the core kernel. | |
1041 | */ | |
be10ab10 | 1042 | ld r2, PACATOC(r13) |
6794c782 SR |
1043 | |
1044 | bl .ftrace_return_to_handler | |
1045 | nop | |
1046 | ||
1047 | /* return value has real return address */ | |
1048 | mtlr r3 | |
1049 | ||
1050 | ld r1, 0(r1) | |
1051 | ld r4, -32(r1) | |
1052 | ld r3, -24(r1) | |
1053 | ld r2, -16(r1) | |
1054 | ld r31, -8(r1) | |
1055 | ||
1056 | /* Jump back to real return address */ | |
1057 | blr | |
1058 | #endif /* CONFIG_FUNCTION_GRAPH_TRACER */ | |
1059 | #endif /* CONFIG_FUNCTION_TRACER */ |