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1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
55037d17 GS |
2 | /* |
3 | * The file intends to implement PE based on the information from | |
4 | * platforms. Basically, there have 3 types of PEs: PHB/Bus/Device. | |
5 | * All the PEs should be organized as hierarchy tree. The first level | |
6 | * of the tree will be associated to existing PHBs since the particular | |
7 | * PE is only meaningful in one PHB domain. | |
8 | * | |
9 | * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2012. | |
55037d17 GS |
10 | */ |
11 | ||
652defed | 12 | #include <linux/delay.h> |
55037d17 GS |
13 | #include <linux/export.h> |
14 | #include <linux/gfp.h> | |
55037d17 GS |
15 | #include <linux/kernel.h> |
16 | #include <linux/pci.h> | |
17 | #include <linux/string.h> | |
18 | ||
19 | #include <asm/pci-bridge.h> | |
20 | #include <asm/ppc-pci.h> | |
21 | ||
bb593c00 | 22 | static int eeh_pe_aux_size = 0; |
55037d17 GS |
23 | static LIST_HEAD(eeh_phb_pe); |
24 | ||
bb593c00 GS |
25 | /** |
26 | * eeh_set_pe_aux_size - Set PE auxillary data size | |
27 | * @size: PE auxillary data size | |
28 | * | |
29 | * Set PE auxillary data size | |
30 | */ | |
31 | void eeh_set_pe_aux_size(int size) | |
32 | { | |
33 | if (size < 0) | |
34 | return; | |
35 | ||
36 | eeh_pe_aux_size = size; | |
37 | } | |
38 | ||
55037d17 GS |
39 | /** |
40 | * eeh_pe_alloc - Allocate PE | |
41 | * @phb: PCI controller | |
42 | * @type: PE type | |
43 | * | |
44 | * Allocate PE instance dynamically. | |
45 | */ | |
46 | static struct eeh_pe *eeh_pe_alloc(struct pci_controller *phb, int type) | |
47 | { | |
48 | struct eeh_pe *pe; | |
bb593c00 GS |
49 | size_t alloc_size; |
50 | ||
51 | alloc_size = sizeof(struct eeh_pe); | |
52 | if (eeh_pe_aux_size) { | |
53 | alloc_size = ALIGN(alloc_size, cache_line_size()); | |
54 | alloc_size += eeh_pe_aux_size; | |
55 | } | |
55037d17 GS |
56 | |
57 | /* Allocate PHB PE */ | |
bb593c00 | 58 | pe = kzalloc(alloc_size, GFP_KERNEL); |
55037d17 GS |
59 | if (!pe) return NULL; |
60 | ||
61 | /* Initialize PHB PE */ | |
62 | pe->type = type; | |
63 | pe->phb = phb; | |
64 | INIT_LIST_HEAD(&pe->child_list); | |
55037d17 GS |
65 | INIT_LIST_HEAD(&pe->edevs); |
66 | ||
bb593c00 GS |
67 | pe->data = (void *)pe + ALIGN(sizeof(struct eeh_pe), |
68 | cache_line_size()); | |
55037d17 GS |
69 | return pe; |
70 | } | |
71 | ||
72 | /** | |
73 | * eeh_phb_pe_create - Create PHB PE | |
74 | * @phb: PCI controller | |
75 | * | |
76 | * The function should be called while the PHB is detected during | |
77 | * system boot or PCI hotplug in order to create PHB PE. | |
78 | */ | |
cad5cef6 | 79 | int eeh_phb_pe_create(struct pci_controller *phb) |
55037d17 GS |
80 | { |
81 | struct eeh_pe *pe; | |
82 | ||
83 | /* Allocate PHB PE */ | |
84 | pe = eeh_pe_alloc(phb, EEH_PE_PHB); | |
85 | if (!pe) { | |
86 | pr_err("%s: out of memory!\n", __func__); | |
87 | return -ENOMEM; | |
88 | } | |
89 | ||
90 | /* Put it into the list */ | |
55037d17 | 91 | list_add_tail(&pe->child, &eeh_phb_pe); |
55037d17 | 92 | |
1f52f176 | 93 | pr_debug("EEH: Add PE for PHB#%x\n", phb->global_number); |
55037d17 GS |
94 | |
95 | return 0; | |
96 | } | |
97 | ||
fef7f905 SB |
98 | /** |
99 | * eeh_wait_state - Wait for PE state | |
100 | * @pe: EEH PE | |
101 | * @max_wait: maximal period in millisecond | |
102 | * | |
103 | * Wait for the state of associated PE. It might take some time | |
104 | * to retrieve the PE's state. | |
105 | */ | |
106 | int eeh_wait_state(struct eeh_pe *pe, int max_wait) | |
107 | { | |
108 | int ret; | |
109 | int mwait; | |
110 | ||
111 | /* | |
112 | * According to PAPR, the state of PE might be temporarily | |
113 | * unavailable. Under the circumstance, we have to wait | |
114 | * for indicated time determined by firmware. The maximal | |
115 | * wait time is 5 minutes, which is acquired from the original | |
116 | * EEH implementation. Also, the original implementation | |
117 | * also defined the minimal wait time as 1 second. | |
118 | */ | |
119 | #define EEH_STATE_MIN_WAIT_TIME (1000) | |
120 | #define EEH_STATE_MAX_WAIT_TIME (300 * 1000) | |
121 | ||
122 | while (1) { | |
123 | ret = eeh_ops->get_state(pe, &mwait); | |
124 | ||
125 | if (ret != EEH_STATE_UNAVAILABLE) | |
126 | return ret; | |
127 | ||
128 | if (max_wait <= 0) { | |
129 | pr_warn("%s: Timeout when getting PE's state (%d)\n", | |
130 | __func__, max_wait); | |
131 | return EEH_STATE_NOT_SUPPORT; | |
132 | } | |
133 | ||
134 | if (mwait < EEH_STATE_MIN_WAIT_TIME) { | |
135 | pr_warn("%s: Firmware returned bad wait value %d\n", | |
136 | __func__, mwait); | |
137 | mwait = EEH_STATE_MIN_WAIT_TIME; | |
138 | } else if (mwait > EEH_STATE_MAX_WAIT_TIME) { | |
139 | pr_warn("%s: Firmware returned too long wait value %d\n", | |
140 | __func__, mwait); | |
141 | mwait = EEH_STATE_MAX_WAIT_TIME; | |
142 | } | |
143 | ||
144 | msleep(min(mwait, max_wait)); | |
145 | max_wait -= mwait; | |
146 | } | |
147 | } | |
148 | ||
55037d17 GS |
149 | /** |
150 | * eeh_phb_pe_get - Retrieve PHB PE based on the given PHB | |
151 | * @phb: PCI controller | |
152 | * | |
153 | * The overall PEs form hierarchy tree. The first layer of the | |
154 | * hierarchy tree is composed of PHB PEs. The function is used | |
155 | * to retrieve the corresponding PHB PE according to the given PHB. | |
156 | */ | |
9ff67433 | 157 | struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb) |
55037d17 GS |
158 | { |
159 | struct eeh_pe *pe; | |
160 | ||
55037d17 GS |
161 | list_for_each_entry(pe, &eeh_phb_pe, child) { |
162 | /* | |
163 | * Actually, we needn't check the type since | |
164 | * the PE for PHB has been determined when that | |
165 | * was created. | |
166 | */ | |
7844663a | 167 | if ((pe->type & EEH_PE_PHB) && pe->phb == phb) |
55037d17 | 168 | return pe; |
55037d17 GS |
169 | } |
170 | ||
55037d17 GS |
171 | return NULL; |
172 | } | |
22f4ab12 GS |
173 | |
174 | /** | |
175 | * eeh_pe_next - Retrieve the next PE in the tree | |
176 | * @pe: current PE | |
177 | * @root: root PE | |
178 | * | |
179 | * The function is used to retrieve the next PE in the | |
180 | * hierarchy PE tree. | |
181 | */ | |
309ed3a7 | 182 | struct eeh_pe *eeh_pe_next(struct eeh_pe *pe, struct eeh_pe *root) |
22f4ab12 GS |
183 | { |
184 | struct list_head *next = pe->child_list.next; | |
185 | ||
186 | if (next == &pe->child_list) { | |
187 | while (1) { | |
188 | if (pe == root) | |
189 | return NULL; | |
190 | next = pe->child.next; | |
191 | if (next != &pe->parent->child_list) | |
192 | break; | |
193 | pe = pe->parent; | |
194 | } | |
195 | } | |
196 | ||
197 | return list_entry(next, struct eeh_pe, child); | |
198 | } | |
199 | ||
200 | /** | |
201 | * eeh_pe_traverse - Traverse PEs in the specified PHB | |
202 | * @root: root PE | |
203 | * @fn: callback | |
204 | * @flag: extra parameter to callback | |
205 | * | |
206 | * The function is used to traverse the specified PE and its | |
207 | * child PEs. The traversing is to be terminated once the | |
208 | * callback returns something other than NULL, or no more PEs | |
209 | * to be traversed. | |
210 | */ | |
f5c57710 | 211 | void *eeh_pe_traverse(struct eeh_pe *root, |
d6c4932f | 212 | eeh_pe_traverse_func fn, void *flag) |
22f4ab12 GS |
213 | { |
214 | struct eeh_pe *pe; | |
215 | void *ret; | |
216 | ||
309ed3a7 | 217 | eeh_for_each_pe(root, pe) { |
22f4ab12 GS |
218 | ret = fn(pe, flag); |
219 | if (ret) return ret; | |
220 | } | |
221 | ||
222 | return NULL; | |
223 | } | |
224 | ||
9e6d2cf6 GS |
225 | /** |
226 | * eeh_pe_dev_traverse - Traverse the devices from the PE | |
227 | * @root: EEH PE | |
228 | * @fn: function callback | |
229 | * @flag: extra parameter to callback | |
230 | * | |
231 | * The function is used to traverse the devices of the specified | |
232 | * PE and its child PEs. | |
233 | */ | |
234 | void *eeh_pe_dev_traverse(struct eeh_pe *root, | |
d6c4932f | 235 | eeh_edev_traverse_func fn, void *flag) |
9e6d2cf6 GS |
236 | { |
237 | struct eeh_pe *pe; | |
9feed42e | 238 | struct eeh_dev *edev, *tmp; |
9e6d2cf6 GS |
239 | void *ret; |
240 | ||
241 | if (!root) { | |
0dae2743 GS |
242 | pr_warn("%s: Invalid PE %p\n", |
243 | __func__, root); | |
9e6d2cf6 GS |
244 | return NULL; |
245 | } | |
246 | ||
247 | /* Traverse root PE */ | |
309ed3a7 | 248 | eeh_for_each_pe(root, pe) { |
9feed42e | 249 | eeh_pe_for_each_dev(pe, edev, tmp) { |
9e6d2cf6 | 250 | ret = fn(edev, flag); |
ef6a2857 | 251 | if (ret) |
ea81245c | 252 | return ret; |
9e6d2cf6 GS |
253 | } |
254 | } | |
255 | ||
256 | return NULL; | |
257 | } | |
258 | ||
22f4ab12 GS |
259 | /** |
260 | * __eeh_pe_get - Check the PE address | |
261 | * @data: EEH PE | |
262 | * @flag: EEH device | |
263 | * | |
264 | * For one particular PE, it can be identified by PE address | |
265 | * or tranditional BDF address. BDF address is composed of | |
266 | * Bus/Device/Function number. The extra data referred by flag | |
267 | * indicates which type of address should be used. | |
268 | */ | |
8bae6a23 AK |
269 | struct eeh_pe_get_flag { |
270 | int pe_no; | |
271 | int config_addr; | |
272 | }; | |
273 | ||
d6c4932f | 274 | static void *__eeh_pe_get(struct eeh_pe *pe, void *flag) |
22f4ab12 | 275 | { |
8bae6a23 | 276 | struct eeh_pe_get_flag *tmp = (struct eeh_pe_get_flag *) flag; |
22f4ab12 GS |
277 | |
278 | /* Unexpected PHB PE */ | |
5efc3ad7 | 279 | if (pe->type & EEH_PE_PHB) |
22f4ab12 GS |
280 | return NULL; |
281 | ||
2aa5cf9e GS |
282 | /* |
283 | * We prefer PE address. For most cases, we should | |
284 | * have non-zero PE address | |
285 | */ | |
286 | if (eeh_has_flag(EEH_VALID_PE_ZERO)) { | |
8bae6a23 | 287 | if (tmp->pe_no == pe->addr) |
2aa5cf9e GS |
288 | return pe; |
289 | } else { | |
8bae6a23 AK |
290 | if (tmp->pe_no && |
291 | (tmp->pe_no == pe->addr)) | |
2d521784 | 292 | return pe; |
2aa5cf9e | 293 | } |
22f4ab12 GS |
294 | |
295 | /* Try BDF address */ | |
8bae6a23 AK |
296 | if (tmp->config_addr && |
297 | (tmp->config_addr == pe->config_addr)) | |
22f4ab12 GS |
298 | return pe; |
299 | ||
300 | return NULL; | |
301 | } | |
302 | ||
303 | /** | |
304 | * eeh_pe_get - Search PE based on the given address | |
8bae6a23 AK |
305 | * @phb: PCI controller |
306 | * @pe_no: PE number | |
307 | * @config_addr: Config address | |
22f4ab12 GS |
308 | * |
309 | * Search the corresponding PE based on the specified address which | |
310 | * is included in the eeh device. The function is used to check if | |
311 | * the associated PE has been created against the PE address. It's | |
312 | * notable that the PE address has 2 format: traditional PE address | |
313 | * which is composed of PCI bus/device/function number, or unified | |
314 | * PE address. | |
315 | */ | |
8bae6a23 AK |
316 | struct eeh_pe *eeh_pe_get(struct pci_controller *phb, |
317 | int pe_no, int config_addr) | |
22f4ab12 | 318 | { |
8bae6a23 AK |
319 | struct eeh_pe *root = eeh_phb_pe_get(phb); |
320 | struct eeh_pe_get_flag tmp = { pe_no, config_addr }; | |
22f4ab12 GS |
321 | struct eeh_pe *pe; |
322 | ||
8bae6a23 | 323 | pe = eeh_pe_traverse(root, __eeh_pe_get, &tmp); |
22f4ab12 GS |
324 | |
325 | return pe; | |
326 | } | |
327 | ||
328 | /** | |
329 | * eeh_pe_get_parent - Retrieve the parent PE | |
330 | * @edev: EEH device | |
331 | * | |
332 | * The whole PEs existing in the system are organized as hierarchy | |
333 | * tree. The function is used to retrieve the parent PE according | |
334 | * to the parent EEH device. | |
335 | */ | |
336 | static struct eeh_pe *eeh_pe_get_parent(struct eeh_dev *edev) | |
337 | { | |
22f4ab12 | 338 | struct eeh_dev *parent; |
0bd78587 | 339 | struct pci_dn *pdn = eeh_dev_to_pdn(edev); |
22f4ab12 GS |
340 | |
341 | /* | |
342 | * It might have the case for the indirect parent | |
343 | * EEH device already having associated PE, but | |
344 | * the direct parent EEH device doesn't have yet. | |
345 | */ | |
c29fa27d WY |
346 | if (edev->physfn) |
347 | pdn = pci_get_pdn(edev->physfn); | |
348 | else | |
349 | pdn = pdn ? pdn->parent : NULL; | |
0bd78587 | 350 | while (pdn) { |
22f4ab12 | 351 | /* We're poking out of PCI territory */ |
0bd78587 GS |
352 | parent = pdn_to_eeh_dev(pdn); |
353 | if (!parent) | |
354 | return NULL; | |
22f4ab12 GS |
355 | |
356 | if (parent->pe) | |
357 | return parent->pe; | |
358 | ||
0bd78587 | 359 | pdn = pdn->parent; |
22f4ab12 GS |
360 | } |
361 | ||
362 | return NULL; | |
363 | } | |
9b84348c GS |
364 | |
365 | /** | |
366 | * eeh_add_to_parent_pe - Add EEH device to parent PE | |
367 | * @edev: EEH device | |
368 | * | |
369 | * Add EEH device to the parent PE. If the parent PE already | |
370 | * exists, the PE type will be changed to EEH_PE_BUS. Otherwise, | |
371 | * we have to create new PE to hold the EEH device and the new | |
372 | * PE will be linked to its parent PE as well. | |
373 | */ | |
374 | int eeh_add_to_parent_pe(struct eeh_dev *edev) | |
375 | { | |
376 | struct eeh_pe *pe, *parent; | |
69672bd7 | 377 | struct pci_dn *pdn = eeh_dev_to_pdn(edev); |
405b33a7 | 378 | int config_addr = (pdn->busno << 8) | (pdn->devfn); |
9b84348c | 379 | |
433185d2 GS |
380 | /* Check if the PE number is valid */ |
381 | if (!eeh_has_flag(EEH_VALID_PE_ZERO) && !edev->pe_config_addr) { | |
1ff8f36f | 382 | eeh_edev_err(edev, "PE#0 is invalid for this PHB!\n"); |
433185d2 GS |
383 | return -EINVAL; |
384 | } | |
385 | ||
9b84348c GS |
386 | /* |
387 | * Search the PE has been existing or not according | |
388 | * to the PE address. If that has been existing, the | |
389 | * PE should be composed of PCI bus and its subordinate | |
390 | * components. | |
391 | */ | |
405b33a7 | 392 | pe = eeh_pe_get(pdn->phb, edev->pe_config_addr, config_addr); |
5efc3ad7 | 393 | if (pe && !(pe->type & EEH_PE_INVALID)) { |
9b84348c GS |
394 | /* Mark the PE as type of PCI bus */ |
395 | pe->type = EEH_PE_BUS; | |
396 | edev->pe = pe; | |
397 | ||
398 | /* Put the edev to PE */ | |
80e65b00 | 399 | list_add_tail(&edev->entry, &pe->edevs); |
1ff8f36f | 400 | eeh_edev_dbg(edev, "Added to bus PE\n"); |
5efc3ad7 GS |
401 | return 0; |
402 | } else if (pe && (pe->type & EEH_PE_INVALID)) { | |
80e65b00 | 403 | list_add_tail(&edev->entry, &pe->edevs); |
5efc3ad7 GS |
404 | edev->pe = pe; |
405 | /* | |
406 | * We're running to here because of PCI hotplug caused by | |
407 | * EEH recovery. We need clear EEH_PE_INVALID until the top. | |
408 | */ | |
409 | parent = pe; | |
410 | while (parent) { | |
411 | if (!(parent->type & EEH_PE_INVALID)) | |
412 | break; | |
473af09b | 413 | parent->type &= ~EEH_PE_INVALID; |
5efc3ad7 GS |
414 | parent = parent->parent; |
415 | } | |
5efc3ad7 | 416 | |
1ff8f36f SB |
417 | eeh_edev_dbg(edev, "Added to device PE (parent: PE#%x)\n", |
418 | pe->parent->addr); | |
9b84348c GS |
419 | return 0; |
420 | } | |
421 | ||
422 | /* Create a new EEH PE */ | |
c29fa27d | 423 | if (edev->physfn) |
69672bd7 | 424 | pe = eeh_pe_alloc(pdn->phb, EEH_PE_VF); |
c29fa27d | 425 | else |
69672bd7 | 426 | pe = eeh_pe_alloc(pdn->phb, EEH_PE_DEVICE); |
9b84348c GS |
427 | if (!pe) { |
428 | pr_err("%s: out of memory!\n", __func__); | |
429 | return -ENOMEM; | |
430 | } | |
431 | pe->addr = edev->pe_config_addr; | |
405b33a7 | 432 | pe->config_addr = config_addr; |
9b84348c GS |
433 | |
434 | /* | |
435 | * Put the new EEH PE into hierarchy tree. If the parent | |
436 | * can't be found, the newly created PE will be attached | |
437 | * to PHB directly. Otherwise, we have to associate the | |
438 | * PE with its parent. | |
439 | */ | |
440 | parent = eeh_pe_get_parent(edev); | |
441 | if (!parent) { | |
69672bd7 | 442 | parent = eeh_phb_pe_get(pdn->phb); |
9b84348c GS |
443 | if (!parent) { |
444 | pr_err("%s: No PHB PE is found (PHB Domain=%d)\n", | |
69672bd7 | 445 | __func__, pdn->phb->global_number); |
9b84348c GS |
446 | edev->pe = NULL; |
447 | kfree(pe); | |
448 | return -EEXIST; | |
449 | } | |
450 | } | |
451 | pe->parent = parent; | |
452 | ||
453 | /* | |
454 | * Put the newly created PE into the child list and | |
455 | * link the EEH device accordingly. | |
456 | */ | |
457 | list_add_tail(&pe->child, &parent->child_list); | |
80e65b00 | 458 | list_add_tail(&edev->entry, &pe->edevs); |
9b84348c | 459 | edev->pe = pe; |
1ff8f36f SB |
460 | eeh_edev_dbg(edev, "Added to device PE (parent: PE#%x)\n", |
461 | pe->parent->addr); | |
9b84348c GS |
462 | |
463 | return 0; | |
464 | } | |
82e8882f GS |
465 | |
466 | /** | |
467 | * eeh_rmv_from_parent_pe - Remove one EEH device from the associated PE | |
468 | * @edev: EEH device | |
469 | * | |
470 | * The PE hierarchy tree might be changed when doing PCI hotplug. | |
471 | * Also, the PCI devices or buses could be removed from the system | |
472 | * during EEH recovery. So we have to call the function remove the | |
473 | * corresponding PE accordingly if necessary. | |
474 | */ | |
807a827d | 475 | int eeh_rmv_from_parent_pe(struct eeh_dev *edev) |
82e8882f | 476 | { |
5efc3ad7 GS |
477 | struct eeh_pe *pe, *parent, *child; |
478 | int cnt; | |
82e8882f | 479 | |
9a3eda26 SB |
480 | pe = eeh_dev_to_pe(edev); |
481 | if (!pe) { | |
1ff8f36f | 482 | eeh_edev_dbg(edev, "No PE found for device.\n"); |
82e8882f GS |
483 | return -EEXIST; |
484 | } | |
485 | ||
486 | /* Remove the EEH device */ | |
82e8882f | 487 | edev->pe = NULL; |
80e65b00 | 488 | list_del(&edev->entry); |
82e8882f GS |
489 | |
490 | /* | |
491 | * Check if the parent PE includes any EEH devices. | |
492 | * If not, we should delete that. Also, we should | |
493 | * delete the parent PE if it doesn't have associated | |
494 | * child PEs and EEH devices. | |
495 | */ | |
496 | while (1) { | |
497 | parent = pe->parent; | |
5efc3ad7 | 498 | if (pe->type & EEH_PE_PHB) |
82e8882f GS |
499 | break; |
500 | ||
807a827d | 501 | if (!(pe->state & EEH_PE_KEEP)) { |
20ee6a97 GS |
502 | if (list_empty(&pe->edevs) && |
503 | list_empty(&pe->child_list)) { | |
504 | list_del(&pe->child); | |
505 | kfree(pe); | |
506 | } else { | |
507 | break; | |
5efc3ad7 | 508 | } |
20ee6a97 GS |
509 | } else { |
510 | if (list_empty(&pe->edevs)) { | |
511 | cnt = 0; | |
512 | list_for_each_entry(child, &pe->child_list, child) { | |
e716e014 | 513 | if (!(child->type & EEH_PE_INVALID)) { |
20ee6a97 GS |
514 | cnt++; |
515 | break; | |
516 | } | |
517 | } | |
5efc3ad7 | 518 | |
20ee6a97 GS |
519 | if (!cnt) |
520 | pe->type |= EEH_PE_INVALID; | |
521 | else | |
522 | break; | |
523 | } | |
82e8882f GS |
524 | } |
525 | ||
526 | pe = parent; | |
527 | } | |
528 | ||
529 | return 0; | |
530 | } | |
5b663529 | 531 | |
5a71978e GS |
532 | /** |
533 | * eeh_pe_update_time_stamp - Update PE's frozen time stamp | |
534 | * @pe: EEH PE | |
535 | * | |
536 | * We have time stamp for each PE to trace its time of getting | |
537 | * frozen in last hour. The function should be called to update | |
538 | * the time stamp on first error of the specific PE. On the other | |
539 | * handle, we needn't account for errors happened in last hour. | |
540 | */ | |
541 | void eeh_pe_update_time_stamp(struct eeh_pe *pe) | |
542 | { | |
edfd17ff | 543 | time64_t tstamp; |
5a71978e GS |
544 | |
545 | if (!pe) return; | |
546 | ||
547 | if (pe->freeze_count <= 0) { | |
548 | pe->freeze_count = 0; | |
edfd17ff | 549 | pe->tstamp = ktime_get_seconds(); |
5a71978e | 550 | } else { |
edfd17ff AB |
551 | tstamp = ktime_get_seconds(); |
552 | if (tstamp - pe->tstamp > 3600) { | |
5a71978e GS |
553 | pe->tstamp = tstamp; |
554 | pe->freeze_count = 0; | |
555 | } | |
556 | } | |
557 | } | |
558 | ||
5b663529 | 559 | /** |
e762bb89 SB |
560 | * eeh_pe_state_mark - Mark specified state for PE and its associated device |
561 | * @pe: EEH PE | |
5b663529 | 562 | * |
e762bb89 SB |
563 | * EEH error affects the current PE and its child PEs. The function |
564 | * is used to mark appropriate state for the affected PEs and the | |
565 | * associated devices. | |
5b663529 | 566 | */ |
e762bb89 | 567 | void eeh_pe_state_mark(struct eeh_pe *root, int state) |
5b663529 | 568 | { |
e762bb89 | 569 | struct eeh_pe *pe; |
b6541db1 | 570 | |
e762bb89 SB |
571 | eeh_for_each_pe(root, pe) |
572 | if (!(pe->state & EEH_PE_REMOVED)) | |
573 | pe->state |= state; | |
5b663529 | 574 | } |
e762bb89 | 575 | EXPORT_SYMBOL_GPL(eeh_pe_state_mark); |
5b663529 GS |
576 | |
577 | /** | |
e762bb89 | 578 | * eeh_pe_mark_isolated |
5b663529 GS |
579 | * @pe: EEH PE |
580 | * | |
e762bb89 SB |
581 | * Record that a PE has been isolated by marking the PE and it's children as |
582 | * EEH_PE_ISOLATED (and EEH_PE_CFG_BLOCKED, if required) and their PCI devices | |
583 | * as pci_channel_io_frozen. | |
5b663529 | 584 | */ |
e762bb89 | 585 | void eeh_pe_mark_isolated(struct eeh_pe *root) |
5b663529 | 586 | { |
e762bb89 SB |
587 | struct eeh_pe *pe; |
588 | struct eeh_dev *edev; | |
589 | struct pci_dev *pdev; | |
590 | ||
591 | eeh_pe_state_mark(root, EEH_PE_ISOLATED); | |
592 | eeh_for_each_pe(root, pe) { | |
593 | list_for_each_entry(edev, &pe->edevs, entry) { | |
594 | pdev = eeh_dev_to_pci_dev(edev); | |
595 | if (pdev) | |
596 | pdev->error_state = pci_channel_io_frozen; | |
597 | } | |
598 | /* Block PCI config access if required */ | |
599 | if (pe->state & EEH_PE_CFG_RESTRICTED) | |
600 | pe->state |= EEH_PE_CFG_BLOCKED; | |
601 | } | |
5b663529 | 602 | } |
e762bb89 | 603 | EXPORT_SYMBOL_GPL(eeh_pe_mark_isolated); |
5b663529 | 604 | |
d6c4932f | 605 | static void *__eeh_pe_dev_mode_mark(struct eeh_dev *edev, void *flag) |
d2b0f6f7 | 606 | { |
d2b0f6f7 GS |
607 | int mode = *((int *)flag); |
608 | ||
609 | edev->mode |= mode; | |
610 | ||
611 | return NULL; | |
612 | } | |
613 | ||
614 | /** | |
615 | * eeh_pe_dev_state_mark - Mark state for all device under the PE | |
616 | * @pe: EEH PE | |
617 | * | |
618 | * Mark specific state for all child devices of the PE. | |
619 | */ | |
620 | void eeh_pe_dev_mode_mark(struct eeh_pe *pe, int mode) | |
621 | { | |
622 | eeh_pe_dev_traverse(pe, __eeh_pe_dev_mode_mark, &mode); | |
623 | } | |
624 | ||
5b663529 | 625 | /** |
9ed5ca66 | 626 | * eeh_pe_state_clear - Clear state for the PE |
5b663529 | 627 | * @data: EEH PE |
9ed5ca66 SB |
628 | * @state: state |
629 | * @include_passed: include passed-through devices? | |
5b663529 GS |
630 | * |
631 | * The function is used to clear the indicated state from the | |
632 | * given PE. Besides, we also clear the check count of the PE | |
633 | * as well. | |
634 | */ | |
9ed5ca66 | 635 | void eeh_pe_state_clear(struct eeh_pe *root, int state, bool include_passed) |
5b663529 | 636 | { |
9ed5ca66 | 637 | struct eeh_pe *pe; |
22fca179 GS |
638 | struct eeh_dev *edev, *tmp; |
639 | struct pci_dev *pdev; | |
5b663529 | 640 | |
9ed5ca66 SB |
641 | eeh_for_each_pe(root, pe) { |
642 | /* Keep the state of permanently removed PE intact */ | |
643 | if (pe->state & EEH_PE_REMOVED) | |
644 | continue; | |
d2b0f6f7 | 645 | |
9ed5ca66 SB |
646 | if (!include_passed && eeh_pe_passed(pe)) |
647 | continue; | |
d2b0f6f7 | 648 | |
9ed5ca66 | 649 | pe->state &= ~state; |
22fca179 | 650 | |
9ed5ca66 SB |
651 | /* |
652 | * Special treatment on clearing isolated state. Clear | |
653 | * check count since last isolation and put all affected | |
654 | * devices to normal state. | |
655 | */ | |
656 | if (!(state & EEH_PE_ISOLATED)) | |
22fca179 GS |
657 | continue; |
658 | ||
9ed5ca66 SB |
659 | pe->check_count = 0; |
660 | eeh_pe_for_each_dev(pe, edev, tmp) { | |
661 | pdev = eeh_dev_to_pci_dev(edev); | |
662 | if (!pdev) | |
663 | continue; | |
b6541db1 | 664 | |
9ed5ca66 SB |
665 | pdev->error_state = pci_channel_io_normal; |
666 | } | |
5b663529 | 667 | |
9ed5ca66 SB |
668 | /* Unblock PCI config access if required */ |
669 | if (pe->state & EEH_PE_CFG_RESTRICTED) | |
670 | pe->state &= ~EEH_PE_CFG_BLOCKED; | |
671 | } | |
39bfd715 GS |
672 | } |
673 | ||
652defed GS |
674 | /* |
675 | * Some PCI bridges (e.g. PLX bridges) have primary/secondary | |
676 | * buses assigned explicitly by firmware, and we probably have | |
677 | * lost that after reset. So we have to delay the check until | |
678 | * the PCI-CFG registers have been restored for the parent | |
679 | * bridge. | |
9e6d2cf6 | 680 | * |
652defed GS |
681 | * Don't use normal PCI-CFG accessors, which probably has been |
682 | * blocked on normal path during the stage. So we need utilize | |
683 | * eeh operations, which is always permitted. | |
9e6d2cf6 | 684 | */ |
0bd78587 | 685 | static void eeh_bridge_check_link(struct eeh_dev *edev) |
652defed | 686 | { |
0bd78587 | 687 | struct pci_dn *pdn = eeh_dev_to_pdn(edev); |
652defed GS |
688 | int cap; |
689 | uint32_t val; | |
690 | int timeout = 0; | |
691 | ||
692 | /* | |
693 | * We only check root port and downstream ports of | |
694 | * PCIe switches | |
695 | */ | |
4b83bd45 | 696 | if (!(edev->mode & (EEH_DEV_ROOT_PORT | EEH_DEV_DS_PORT))) |
652defed GS |
697 | return; |
698 | ||
1ff8f36f | 699 | eeh_edev_dbg(edev, "Checking PCIe link...\n"); |
652defed GS |
700 | |
701 | /* Check slot status */ | |
4b83bd45 | 702 | cap = edev->pcie_cap; |
0bd78587 | 703 | eeh_ops->read_config(pdn, cap + PCI_EXP_SLTSTA, 2, &val); |
652defed | 704 | if (!(val & PCI_EXP_SLTSTA_PDS)) { |
1ff8f36f | 705 | eeh_edev_dbg(edev, "No card in the slot (0x%04x) !\n", val); |
652defed GS |
706 | return; |
707 | } | |
708 | ||
709 | /* Check power status if we have the capability */ | |
0bd78587 | 710 | eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCAP, 2, &val); |
652defed | 711 | if (val & PCI_EXP_SLTCAP_PCP) { |
0bd78587 | 712 | eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCTL, 2, &val); |
652defed | 713 | if (val & PCI_EXP_SLTCTL_PCC) { |
1ff8f36f | 714 | eeh_edev_dbg(edev, "In power-off state, power it on ...\n"); |
652defed GS |
715 | val &= ~(PCI_EXP_SLTCTL_PCC | PCI_EXP_SLTCTL_PIC); |
716 | val |= (0x0100 & PCI_EXP_SLTCTL_PIC); | |
0bd78587 | 717 | eeh_ops->write_config(pdn, cap + PCI_EXP_SLTCTL, 2, val); |
652defed GS |
718 | msleep(2 * 1000); |
719 | } | |
720 | } | |
721 | ||
722 | /* Enable link */ | |
0bd78587 | 723 | eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCTL, 2, &val); |
652defed | 724 | val &= ~PCI_EXP_LNKCTL_LD; |
0bd78587 | 725 | eeh_ops->write_config(pdn, cap + PCI_EXP_LNKCTL, 2, val); |
652defed GS |
726 | |
727 | /* Check link */ | |
0bd78587 | 728 | eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCAP, 4, &val); |
652defed | 729 | if (!(val & PCI_EXP_LNKCAP_DLLLARC)) { |
1ff8f36f | 730 | eeh_edev_dbg(edev, "No link reporting capability (0x%08x) \n", val); |
652defed GS |
731 | msleep(1000); |
732 | return; | |
733 | } | |
734 | ||
735 | /* Wait the link is up until timeout (5s) */ | |
736 | timeout = 0; | |
737 | while (timeout < 5000) { | |
738 | msleep(20); | |
739 | timeout += 20; | |
740 | ||
0bd78587 | 741 | eeh_ops->read_config(pdn, cap + PCI_EXP_LNKSTA, 2, &val); |
652defed GS |
742 | if (val & PCI_EXP_LNKSTA_DLLLA) |
743 | break; | |
744 | } | |
745 | ||
746 | if (val & PCI_EXP_LNKSTA_DLLLA) | |
1ff8f36f | 747 | eeh_edev_dbg(edev, "Link up (%s)\n", |
652defed GS |
748 | (val & PCI_EXP_LNKSTA_CLS_2_5GB) ? "2.5GB" : "5GB"); |
749 | else | |
1ff8f36f | 750 | eeh_edev_dbg(edev, "Link not ready (0x%04x)\n", val); |
652defed GS |
751 | } |
752 | ||
753 | #define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF)) | |
754 | #define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)]) | |
755 | ||
0bd78587 | 756 | static void eeh_restore_bridge_bars(struct eeh_dev *edev) |
652defed | 757 | { |
0bd78587 | 758 | struct pci_dn *pdn = eeh_dev_to_pdn(edev); |
652defed GS |
759 | int i; |
760 | ||
761 | /* | |
762 | * Device BARs: 0x10 - 0x18 | |
763 | * Bus numbers and windows: 0x18 - 0x30 | |
764 | */ | |
765 | for (i = 4; i < 13; i++) | |
0bd78587 | 766 | eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]); |
652defed | 767 | /* Rom: 0x38 */ |
0bd78587 | 768 | eeh_ops->write_config(pdn, 14*4, 4, edev->config_space[14]); |
652defed GS |
769 | |
770 | /* Cache line & Latency timer: 0xC 0xD */ | |
0bd78587 | 771 | eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1, |
652defed | 772 | SAVED_BYTE(PCI_CACHE_LINE_SIZE)); |
0bd78587 | 773 | eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1, |
652defed GS |
774 | SAVED_BYTE(PCI_LATENCY_TIMER)); |
775 | /* Max latency, min grant, interrupt ping and line: 0x3C */ | |
0bd78587 | 776 | eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]); |
652defed GS |
777 | |
778 | /* PCI Command: 0x4 */ | |
13a83eac MN |
779 | eeh_ops->write_config(pdn, PCI_COMMAND, 4, edev->config_space[1] | |
780 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
652defed GS |
781 | |
782 | /* Check the PCIe link is ready */ | |
0bd78587 | 783 | eeh_bridge_check_link(edev); |
652defed GS |
784 | } |
785 | ||
0bd78587 | 786 | static void eeh_restore_device_bars(struct eeh_dev *edev) |
9e6d2cf6 | 787 | { |
0bd78587 | 788 | struct pci_dn *pdn = eeh_dev_to_pdn(edev); |
9e6d2cf6 GS |
789 | int i; |
790 | u32 cmd; | |
9e6d2cf6 GS |
791 | |
792 | for (i = 4; i < 10; i++) | |
0bd78587 | 793 | eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]); |
9e6d2cf6 | 794 | /* 12 == Expansion ROM Address */ |
0bd78587 | 795 | eeh_ops->write_config(pdn, 12*4, 4, edev->config_space[12]); |
9e6d2cf6 | 796 | |
0bd78587 | 797 | eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1, |
9e6d2cf6 | 798 | SAVED_BYTE(PCI_CACHE_LINE_SIZE)); |
0bd78587 | 799 | eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1, |
9e6d2cf6 GS |
800 | SAVED_BYTE(PCI_LATENCY_TIMER)); |
801 | ||
802 | /* max latency, min grant, interrupt pin and line */ | |
0bd78587 | 803 | eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]); |
9e6d2cf6 GS |
804 | |
805 | /* | |
806 | * Restore PERR & SERR bits, some devices require it, | |
807 | * don't touch the other command bits | |
808 | */ | |
0bd78587 | 809 | eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cmd); |
9e6d2cf6 GS |
810 | if (edev->config_space[1] & PCI_COMMAND_PARITY) |
811 | cmd |= PCI_COMMAND_PARITY; | |
812 | else | |
813 | cmd &= ~PCI_COMMAND_PARITY; | |
814 | if (edev->config_space[1] & PCI_COMMAND_SERR) | |
815 | cmd |= PCI_COMMAND_SERR; | |
816 | else | |
817 | cmd &= ~PCI_COMMAND_SERR; | |
0bd78587 | 818 | eeh_ops->write_config(pdn, PCI_COMMAND, 4, cmd); |
652defed GS |
819 | } |
820 | ||
821 | /** | |
822 | * eeh_restore_one_device_bars - Restore the Base Address Registers for one device | |
823 | * @data: EEH device | |
824 | * @flag: Unused | |
825 | * | |
826 | * Loads the PCI configuration space base address registers, | |
827 | * the expansion ROM base address, the latency timer, and etc. | |
828 | * from the saved values in the device node. | |
829 | */ | |
d6c4932f | 830 | static void *eeh_restore_one_device_bars(struct eeh_dev *edev, void *flag) |
652defed | 831 | { |
0bd78587 | 832 | struct pci_dn *pdn = eeh_dev_to_pdn(edev); |
652defed | 833 | |
f5c57710 | 834 | /* Do special restore for bridges */ |
4b83bd45 | 835 | if (edev->mode & EEH_DEV_BRIDGE) |
0bd78587 | 836 | eeh_restore_bridge_bars(edev); |
652defed | 837 | else |
0bd78587 | 838 | eeh_restore_device_bars(edev); |
9e6d2cf6 | 839 | |
0bd78587 GS |
840 | if (eeh_ops->restore_config && pdn) |
841 | eeh_ops->restore_config(pdn); | |
1d350544 | 842 | |
9e6d2cf6 GS |
843 | return NULL; |
844 | } | |
845 | ||
846 | /** | |
847 | * eeh_pe_restore_bars - Restore the PCI config space info | |
848 | * @pe: EEH PE | |
849 | * | |
850 | * This routine performs a recursive walk to the children | |
851 | * of this device as well. | |
852 | */ | |
853 | void eeh_pe_restore_bars(struct eeh_pe *pe) | |
854 | { | |
ea81245c GS |
855 | /* |
856 | * We needn't take the EEH lock since eeh_pe_dev_traverse() | |
857 | * will take that. | |
858 | */ | |
9e6d2cf6 GS |
859 | eeh_pe_dev_traverse(pe, eeh_restore_one_device_bars, NULL); |
860 | } | |
9b3c76f0 | 861 | |
357b2f3d GS |
862 | /** |
863 | * eeh_pe_loc_get - Retrieve location code binding to the given PE | |
864 | * @pe: EEH PE | |
865 | * | |
866 | * Retrieve the location code of the given PE. If the primary PE bus | |
867 | * is root bus, we will grab location code from PHB device tree node | |
868 | * or root port. Otherwise, the upstream bridge's device tree node | |
869 | * of the primary PE bus will be checked for the location code. | |
870 | */ | |
871 | const char *eeh_pe_loc_get(struct eeh_pe *pe) | |
872 | { | |
357b2f3d | 873 | struct pci_bus *bus = eeh_pe_bus_get(pe); |
7e56f627 | 874 | struct device_node *dn; |
9e5c6e5a | 875 | const char *loc = NULL; |
357b2f3d | 876 | |
7e56f627 GS |
877 | while (bus) { |
878 | dn = pci_bus_to_OF_node(bus); | |
879 | if (!dn) { | |
880 | bus = bus->parent; | |
881 | continue; | |
882 | } | |
357b2f3d | 883 | |
7e56f627 | 884 | if (pci_is_root_bus(bus)) |
9e5c6e5a | 885 | loc = of_get_property(dn, "ibm,io-base-loc-code", NULL); |
7e56f627 GS |
886 | else |
887 | loc = of_get_property(dn, "ibm,slot-location-code", | |
888 | NULL); | |
889 | ||
357b2f3d | 890 | if (loc) |
7e56f627 | 891 | return loc; |
357b2f3d | 892 | |
7e56f627 | 893 | bus = bus->parent; |
357b2f3d GS |
894 | } |
895 | ||
7e56f627 | 896 | return "N/A"; |
357b2f3d GS |
897 | } |
898 | ||
9b3c76f0 GS |
899 | /** |
900 | * eeh_pe_bus_get - Retrieve PCI bus according to the given PE | |
901 | * @pe: EEH PE | |
902 | * | |
903 | * Retrieve the PCI bus according to the given PE. Basically, | |
904 | * there're 3 types of PEs: PHB/Bus/Device. For PHB PE, the | |
905 | * primary PCI bus will be retrieved. The parent bus will be | |
906 | * returned for BUS PE. However, we don't have associated PCI | |
907 | * bus for DEVICE PE. | |
908 | */ | |
909 | struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe) | |
910 | { | |
9b3c76f0 GS |
911 | struct eeh_dev *edev; |
912 | struct pci_dev *pdev; | |
913 | ||
4eb0799f GS |
914 | if (pe->type & EEH_PE_PHB) |
915 | return pe->phb->bus; | |
8cdb2833 | 916 | |
4eb0799f GS |
917 | /* The primary bus might be cached during probe time */ |
918 | if (pe->state & EEH_PE_PRI_BUS) | |
919 | return pe->bus; | |
920 | ||
921 | /* Retrieve the parent PCI bus of first (top) PCI device */ | |
80e65b00 | 922 | edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry); |
4eb0799f GS |
923 | pdev = eeh_dev_to_pci_dev(edev); |
924 | if (pdev) | |
925 | return pdev->bus; | |
9b3c76f0 | 926 | |
4eb0799f | 927 | return NULL; |
9b3c76f0 | 928 | } |