Commit | Line | Data |
---|---|---|
5d5a0936 | 1 | /* |
5d5a0936 LV |
2 | * PCI address cache; allows the lookup of PCI devices based on I/O address |
3 | * | |
3c8c90ab LV |
4 | * Copyright IBM Corporation 2004 |
5 | * Copyright Linas Vepstas <linas@austin.ibm.com> 2004 | |
5d5a0936 LV |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #include <linux/list.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/rbtree.h> | |
5a0e3ad6 | 25 | #include <linux/slab.h> |
5d5a0936 | 26 | #include <linux/spinlock.h> |
60063497 | 27 | #include <linux/atomic.h> |
5d5a0936 | 28 | #include <asm/pci-bridge.h> |
5ca85ae6 | 29 | #include <asm/debugfs.h> |
5d5a0936 | 30 | #include <asm/ppc-pci.h> |
5d5a0936 | 31 | |
5d5a0936 LV |
32 | |
33 | /** | |
3becd11d QC |
34 | * DOC: Overview |
35 | * | |
5d5a0936 LV |
36 | * The pci address cache subsystem. This subsystem places |
37 | * PCI device address resources into a red-black tree, sorted | |
38 | * according to the address range, so that given only an i/o | |
39 | * address, the corresponding PCI device can be **quickly** | |
40 | * found. It is safe to perform an address lookup in an interrupt | |
41 | * context; this ability is an important feature. | |
42 | * | |
43 | * Currently, the only customer of this code is the EEH subsystem; | |
44 | * thus, this code has been somewhat tailored to suit EEH better. | |
45 | * In particular, the cache does *not* hold the addresses of devices | |
46 | * for which EEH is not enabled. | |
47 | * | |
48 | * (Implementation Note: The RB tree seems to be better/faster | |
49 | * than any hash algo I could think of for this problem, even | |
50 | * with the penalty of slow pointer chases for d-cache misses). | |
51 | */ | |
3becd11d | 52 | |
29f8bf1b | 53 | struct pci_io_addr_range { |
5d5a0936 | 54 | struct rb_node rb_node; |
37213529 WY |
55 | resource_size_t addr_lo; |
56 | resource_size_t addr_hi; | |
f8f7d63f | 57 | struct eeh_dev *edev; |
5d5a0936 | 58 | struct pci_dev *pcidev; |
37213529 | 59 | unsigned long flags; |
5d5a0936 LV |
60 | }; |
61 | ||
29f8bf1b | 62 | static struct pci_io_addr_cache { |
5d5a0936 LV |
63 | struct rb_root rb_root; |
64 | spinlock_t piar_lock; | |
65 | } pci_io_addr_cache_root; | |
66 | ||
3ab96a02 | 67 | static inline struct eeh_dev *__eeh_addr_cache_get_device(unsigned long addr) |
5d5a0936 LV |
68 | { |
69 | struct rb_node *n = pci_io_addr_cache_root.rb_root.rb_node; | |
70 | ||
71 | while (n) { | |
72 | struct pci_io_addr_range *piar; | |
73 | piar = rb_entry(n, struct pci_io_addr_range, rb_node); | |
74 | ||
0ba17888 | 75 | if (addr < piar->addr_lo) |
5d5a0936 | 76 | n = n->rb_left; |
0ba17888 GS |
77 | else if (addr > piar->addr_hi) |
78 | n = n->rb_right; | |
79 | else | |
80 | return piar->edev; | |
5d5a0936 LV |
81 | } |
82 | ||
83 | return NULL; | |
84 | } | |
85 | ||
86 | /** | |
3ab96a02 | 87 | * eeh_addr_cache_get_dev - Get device, given only address |
5d5a0936 LV |
88 | * @addr: mmio (PIO) phys address or i/o port number |
89 | * | |
90 | * Given an mmio phys address, or a port number, find a pci device | |
63457b14 | 91 | * that implements this address. I/O port numbers are assumed to be offset |
5d5a0936 LV |
92 | * from zero (that is, they do *not* have pci_io_addr added in). |
93 | * It is safe to call this function within an interrupt. | |
94 | */ | |
3ab96a02 | 95 | struct eeh_dev *eeh_addr_cache_get_dev(unsigned long addr) |
5d5a0936 | 96 | { |
f8f7d63f | 97 | struct eeh_dev *edev; |
5d5a0936 LV |
98 | unsigned long flags; |
99 | ||
100 | spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags); | |
3ab96a02 | 101 | edev = __eeh_addr_cache_get_device(addr); |
5d5a0936 | 102 | spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags); |
f8f7d63f | 103 | return edev; |
5d5a0936 LV |
104 | } |
105 | ||
106 | #ifdef DEBUG | |
107 | /* | |
108 | * Handy-dandy debug print routine, does nothing more | |
109 | * than print out the contents of our addr cache. | |
110 | */ | |
3ab96a02 | 111 | static void eeh_addr_cache_print(struct pci_io_addr_cache *cache) |
5d5a0936 LV |
112 | { |
113 | struct rb_node *n; | |
114 | int cnt = 0; | |
115 | ||
116 | n = rb_first(&cache->rb_root); | |
117 | while (n) { | |
118 | struct pci_io_addr_range *piar; | |
119 | piar = rb_entry(n, struct pci_io_addr_range, rb_node); | |
c8f02f21 | 120 | pr_info("PCI: %s addr range %d [%pap-%pap]: %s\n", |
5d5a0936 | 121 | (piar->flags & IORESOURCE_IO) ? "i/o" : "mem", cnt, |
91dc0682 | 122 | &piar->addr_lo, &piar->addr_hi, pci_name(piar->pcidev)); |
5d5a0936 LV |
123 | cnt++; |
124 | n = rb_next(n); | |
125 | } | |
126 | } | |
127 | #endif | |
128 | ||
129 | /* Insert address range into the rb tree. */ | |
130 | static struct pci_io_addr_range * | |
37213529 WY |
131 | eeh_addr_cache_insert(struct pci_dev *dev, resource_size_t alo, |
132 | resource_size_t ahi, unsigned long flags) | |
5d5a0936 LV |
133 | { |
134 | struct rb_node **p = &pci_io_addr_cache_root.rb_root.rb_node; | |
135 | struct rb_node *parent = NULL; | |
136 | struct pci_io_addr_range *piar; | |
137 | ||
138 | /* Walk tree, find a place to insert into tree */ | |
139 | while (*p) { | |
140 | parent = *p; | |
141 | piar = rb_entry(parent, struct pci_io_addr_range, rb_node); | |
142 | if (ahi < piar->addr_lo) { | |
143 | p = &parent->rb_left; | |
144 | } else if (alo > piar->addr_hi) { | |
145 | p = &parent->rb_right; | |
146 | } else { | |
147 | if (dev != piar->pcidev || | |
148 | alo != piar->addr_lo || ahi != piar->addr_hi) { | |
0dae2743 | 149 | pr_warn("PIAR: overlapping address range\n"); |
5d5a0936 LV |
150 | } |
151 | return piar; | |
152 | } | |
153 | } | |
7e4bbaf0 | 154 | piar = kzalloc(sizeof(struct pci_io_addr_range), GFP_ATOMIC); |
5d5a0936 LV |
155 | if (!piar) |
156 | return NULL; | |
157 | ||
158 | piar->addr_lo = alo; | |
159 | piar->addr_hi = ahi; | |
f8f7d63f | 160 | piar->edev = pci_dev_to_eeh_dev(dev); |
5d5a0936 LV |
161 | piar->pcidev = dev; |
162 | piar->flags = flags; | |
163 | ||
91dc0682 AD |
164 | pr_debug("PIAR: insert range=[%pap:%pap] dev=%s\n", |
165 | &alo, &ahi, pci_name(dev)); | |
5d5a0936 LV |
166 | |
167 | rb_link_node(&piar->rb_node, parent, p); | |
168 | rb_insert_color(&piar->rb_node, &pci_io_addr_cache_root.rb_root); | |
169 | ||
170 | return piar; | |
171 | } | |
172 | ||
3ab96a02 | 173 | static void __eeh_addr_cache_insert_dev(struct pci_dev *dev) |
5d5a0936 | 174 | { |
c6406d8f | 175 | struct pci_dn *pdn; |
d50a7d4c | 176 | struct eeh_dev *edev; |
5d5a0936 | 177 | int i; |
5d5a0936 | 178 | |
c6406d8f GS |
179 | pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); |
180 | if (!pdn) { | |
0dae2743 GS |
181 | pr_warn("PCI: no pci dn found for dev=%s\n", |
182 | pci_name(dev)); | |
5d5a0936 LV |
183 | return; |
184 | } | |
185 | ||
c6406d8f | 186 | edev = pdn_to_eeh_dev(pdn); |
d50a7d4c | 187 | if (!edev) { |
c6406d8f GS |
188 | pr_warn("PCI: no EEH dev found for %s\n", |
189 | pci_name(dev)); | |
d50a7d4c GS |
190 | return; |
191 | } | |
192 | ||
5d5a0936 | 193 | /* Skip any devices for which EEH is not enabled. */ |
05b1721d | 194 | if (!edev->pe) { |
c6406d8f | 195 | dev_dbg(&dev->dev, "EEH: Skip building address cache\n"); |
5d5a0936 LV |
196 | return; |
197 | } | |
198 | ||
51c0e87e WY |
199 | /* |
200 | * Walk resources on this device, poke the first 7 (6 normal BAR and 1 | |
201 | * ROM BAR) into the tree. | |
202 | */ | |
203 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
37213529 WY |
204 | resource_size_t start = pci_resource_start(dev,i); |
205 | resource_size_t end = pci_resource_end(dev,i); | |
206 | unsigned long flags = pci_resource_flags(dev,i); | |
5d5a0936 LV |
207 | |
208 | /* We are interested only bus addresses, not dma or other stuff */ | |
209 | if (0 == (flags & (IORESOURCE_IO | IORESOURCE_MEM))) | |
210 | continue; | |
211 | if (start == 0 || ~start == 0 || end == 0 || ~end == 0) | |
212 | continue; | |
3ab96a02 | 213 | eeh_addr_cache_insert(dev, start, end, flags); |
5d5a0936 | 214 | } |
5d5a0936 LV |
215 | } |
216 | ||
217 | /** | |
3ab96a02 | 218 | * eeh_addr_cache_insert_dev - Add a device to the address cache |
5d5a0936 LV |
219 | * @dev: PCI device whose I/O addresses we are interested in. |
220 | * | |
221 | * In order to support the fast lookup of devices based on addresses, | |
222 | * we maintain a cache of devices that can be quickly searched. | |
223 | * This routine adds a device to that cache. | |
224 | */ | |
3ab96a02 | 225 | void eeh_addr_cache_insert_dev(struct pci_dev *dev) |
5d5a0936 LV |
226 | { |
227 | unsigned long flags; | |
228 | ||
229 | spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags); | |
3ab96a02 | 230 | __eeh_addr_cache_insert_dev(dev); |
5d5a0936 LV |
231 | spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags); |
232 | } | |
233 | ||
3ab96a02 | 234 | static inline void __eeh_addr_cache_rmv_dev(struct pci_dev *dev) |
5d5a0936 LV |
235 | { |
236 | struct rb_node *n; | |
5d5a0936 LV |
237 | |
238 | restart: | |
239 | n = rb_first(&pci_io_addr_cache_root.rb_root); | |
240 | while (n) { | |
241 | struct pci_io_addr_range *piar; | |
242 | piar = rb_entry(n, struct pci_io_addr_range, rb_node); | |
243 | ||
244 | if (piar->pcidev == dev) { | |
e67fbbec OH |
245 | pr_debug("PIAR: remove range=[%pap:%pap] dev=%s\n", |
246 | &piar->addr_lo, &piar->addr_hi, pci_name(dev)); | |
5d5a0936 | 247 | rb_erase(n, &pci_io_addr_cache_root.rb_root); |
5d5a0936 LV |
248 | kfree(piar); |
249 | goto restart; | |
250 | } | |
251 | n = rb_next(n); | |
252 | } | |
5d5a0936 LV |
253 | } |
254 | ||
255 | /** | |
3ab96a02 | 256 | * eeh_addr_cache_rmv_dev - remove pci device from addr cache |
5d5a0936 LV |
257 | * @dev: device to remove |
258 | * | |
259 | * Remove a device from the addr-cache tree. | |
260 | * This is potentially expensive, since it will walk | |
261 | * the tree multiple times (once per resource). | |
262 | * But so what; device removal doesn't need to be that fast. | |
263 | */ | |
3ab96a02 | 264 | void eeh_addr_cache_rmv_dev(struct pci_dev *dev) |
5d5a0936 LV |
265 | { |
266 | unsigned long flags; | |
267 | ||
268 | spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags); | |
3ab96a02 | 269 | __eeh_addr_cache_rmv_dev(dev); |
5d5a0936 LV |
270 | spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags); |
271 | } | |
272 | ||
273 | /** | |
3ab96a02 | 274 | * eeh_addr_cache_build - Build a cache of I/O addresses |
5d5a0936 LV |
275 | * |
276 | * Build a cache of pci i/o addresses. This cache will be used to | |
277 | * find the pci device that corresponds to a given address. | |
278 | * This routine scans all pci busses to build the cache. | |
279 | * Must be run late in boot process, after the pci controllers | |
d6e05edc | 280 | * have been scanned for devices (after all device resources are known). |
5d5a0936 | 281 | */ |
eeb6361f | 282 | void eeh_addr_cache_build(void) |
5d5a0936 | 283 | { |
c6406d8f | 284 | struct pci_dn *pdn; |
d50a7d4c | 285 | struct eeh_dev *edev; |
5d5a0936 LV |
286 | struct pci_dev *dev = NULL; |
287 | ||
288 | spin_lock_init(&pci_io_addr_cache_root.piar_lock); | |
289 | ||
6901c6cc | 290 | for_each_pci_dev(dev) { |
c6406d8f GS |
291 | pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); |
292 | if (!pdn) | |
ccba051c | 293 | continue; |
d50a7d4c | 294 | |
c6406d8f | 295 | edev = pdn_to_eeh_dev(pdn); |
d50a7d4c GS |
296 | if (!edev) |
297 | continue; | |
298 | ||
d50a7d4c GS |
299 | dev->dev.archdata.edev = edev; |
300 | edev->pdev = dev; | |
e1d04c97 | 301 | |
1abd6018 | 302 | eeh_addr_cache_insert_dev(dev); |
e1d04c97 | 303 | eeh_sysfs_add_device(dev); |
5d5a0936 | 304 | } |
5ca85ae6 | 305 | } |
5d5a0936 | 306 | |
5ca85ae6 OH |
307 | static int eeh_addr_cache_show(struct seq_file *s, void *v) |
308 | { | |
309 | struct pci_io_addr_range *piar; | |
310 | struct rb_node *n; | |
311 | ||
312 | spin_lock(&pci_io_addr_cache_root.piar_lock); | |
313 | for (n = rb_first(&pci_io_addr_cache_root.rb_root); n; n = rb_next(n)) { | |
314 | piar = rb_entry(n, struct pci_io_addr_range, rb_node); | |
315 | ||
316 | seq_printf(s, "%s addr range [%pap-%pap]: %s\n", | |
317 | (piar->flags & IORESOURCE_IO) ? "i/o" : "mem", | |
318 | &piar->addr_lo, &piar->addr_hi, pci_name(piar->pcidev)); | |
319 | } | |
320 | spin_unlock(&pci_io_addr_cache_root.piar_lock); | |
321 | ||
322 | return 0; | |
323 | } | |
324 | DEFINE_SHOW_ATTRIBUTE(eeh_addr_cache); | |
325 | ||
326 | void eeh_cache_debugfs_init(void) | |
327 | { | |
328 | debugfs_create_file_unsafe("eeh_address_cache", 0400, | |
329 | powerpc_debugfs_root, NULL, | |
330 | &eeh_addr_cache_fops); | |
5d5a0936 | 331 | } |