Commit | Line | Data |
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1da177e4 | 1 | /* |
3c8c90ab LV |
2 | * Copyright IBM Corporation 2001, 2005, 2006 |
3 | * Copyright Dave Engebretsen & Todd Inglett 2001 | |
4 | * Copyright Linas Vepstas 2005, 2006 | |
cb3bc9d0 | 5 | * Copyright 2001-2012 IBM Corporation. |
69376502 | 6 | * |
1da177e4 LT |
7 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
69376502 | 11 | * |
1da177e4 LT |
12 | * This program is distributed in the hope that it will be useful, |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
69376502 | 16 | * |
1da177e4 LT |
17 | * You should have received a copy of the GNU General Public License |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
3c8c90ab LV |
20 | * |
21 | * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com> | |
1da177e4 LT |
22 | */ |
23 | ||
6dee3fb9 | 24 | #include <linux/delay.h> |
7f52a526 | 25 | #include <linux/debugfs.h> |
cb3bc9d0 | 26 | #include <linux/sched.h> |
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/list.h> | |
1da177e4 | 29 | #include <linux/pci.h> |
a3032ca9 | 30 | #include <linux/iommu.h> |
1da177e4 LT |
31 | #include <linux/proc_fs.h> |
32 | #include <linux/rbtree.h> | |
66f9af83 | 33 | #include <linux/reboot.h> |
1da177e4 LT |
34 | #include <linux/seq_file.h> |
35 | #include <linux/spinlock.h> | |
66b15db6 | 36 | #include <linux/export.h> |
acaa6176 SR |
37 | #include <linux/of.h> |
38 | ||
60063497 | 39 | #include <linux/atomic.h> |
1e54b938 | 40 | #include <asm/debug.h> |
1da177e4 | 41 | #include <asm/eeh.h> |
172ca926 | 42 | #include <asm/eeh_event.h> |
1da177e4 | 43 | #include <asm/io.h> |
212d16cd | 44 | #include <asm/iommu.h> |
1da177e4 | 45 | #include <asm/machdep.h> |
172ca926 | 46 | #include <asm/ppc-pci.h> |
1da177e4 | 47 | #include <asm/rtas.h> |
1da177e4 | 48 | |
1da177e4 LT |
49 | |
50 | /** Overview: | |
51 | * EEH, or "Extended Error Handling" is a PCI bridge technology for | |
52 | * dealing with PCI bus errors that can't be dealt with within the | |
53 | * usual PCI framework, except by check-stopping the CPU. Systems | |
54 | * that are designed for high-availability/reliability cannot afford | |
55 | * to crash due to a "mere" PCI error, thus the need for EEH. | |
56 | * An EEH-capable bridge operates by converting a detected error | |
57 | * into a "slot freeze", taking the PCI adapter off-line, making | |
58 | * the slot behave, from the OS'es point of view, as if the slot | |
59 | * were "empty": all reads return 0xff's and all writes are silently | |
60 | * ignored. EEH slot isolation events can be triggered by parity | |
61 | * errors on the address or data busses (e.g. during posted writes), | |
69376502 LV |
62 | * which in turn might be caused by low voltage on the bus, dust, |
63 | * vibration, humidity, radioactivity or plain-old failed hardware. | |
1da177e4 LT |
64 | * |
65 | * Note, however, that one of the leading causes of EEH slot | |
66 | * freeze events are buggy device drivers, buggy device microcode, | |
67 | * or buggy device hardware. This is because any attempt by the | |
68 | * device to bus-master data to a memory address that is not | |
69 | * assigned to the device will trigger a slot freeze. (The idea | |
70 | * is to prevent devices-gone-wild from corrupting system memory). | |
71 | * Buggy hardware/drivers will have a miserable time co-existing | |
72 | * with EEH. | |
73 | * | |
74 | * Ideally, a PCI device driver, when suspecting that an isolation | |
25985edc | 75 | * event has occurred (e.g. by reading 0xff's), will then ask EEH |
1da177e4 LT |
76 | * whether this is the case, and then take appropriate steps to |
77 | * reset the PCI slot, the PCI device, and then resume operations. | |
78 | * However, until that day, the checking is done here, with the | |
79 | * eeh_check_failure() routine embedded in the MMIO macros. If | |
80 | * the slot is found to be isolated, an "EEH Event" is synthesized | |
81 | * and sent out for processing. | |
82 | */ | |
83 | ||
5c1344e9 | 84 | /* If a device driver keeps reading an MMIO register in an interrupt |
f36c5227 MM |
85 | * handler after a slot isolation event, it might be broken. |
86 | * This sets the threshold for how many read attempts we allow | |
87 | * before printing an error message. | |
1da177e4 | 88 | */ |
2fd30be8 | 89 | #define EEH_MAX_FAILS 2100000 |
1da177e4 | 90 | |
17213c3b | 91 | /* Time to wait for a PCI slot to report status, in milliseconds */ |
fb48dc22 | 92 | #define PCI_BUS_RESET_WAIT_MSEC (5*60*1000) |
9c547768 | 93 | |
d7bb8862 | 94 | /* |
8a5ad356 GS |
95 | * EEH probe mode support, which is part of the flags, |
96 | * is to support multiple platforms for EEH. Some platforms | |
97 | * like pSeries do PCI emunation based on device tree. | |
98 | * However, other platforms like powernv probe PCI devices | |
99 | * from hardware. The flag is used to distinguish that. | |
100 | * In addition, struct eeh_ops::probe would be invoked for | |
101 | * particular OF node or PCI device so that the corresponding | |
102 | * PE would be created there. | |
d7bb8862 | 103 | */ |
8a5ad356 GS |
104 | int eeh_subsystem_flags; |
105 | EXPORT_SYMBOL(eeh_subsystem_flags); | |
106 | ||
1b28f170 GS |
107 | /* |
108 | * EEH allowed maximal frozen times. If one particular PE's | |
109 | * frozen count in last hour exceeds this limit, the PE will | |
110 | * be forced to be offline permanently. | |
111 | */ | |
112 | int eeh_max_freezes = 5; | |
113 | ||
8a5ad356 GS |
114 | /* Platform dependent EEH operations */ |
115 | struct eeh_ops *eeh_ops = NULL; | |
d7bb8862 | 116 | |
fd761fd8 | 117 | /* Lock to avoid races due to multiple reports of an error */ |
4907581d | 118 | DEFINE_RAW_SPINLOCK(confirm_error_lock); |
fd761fd8 | 119 | |
212d16cd GS |
120 | /* Lock to protect passed flags */ |
121 | static DEFINE_MUTEX(eeh_dev_mutex); | |
122 | ||
17213c3b LV |
123 | /* Buffer for reporting pci register dumps. Its here in BSS, and |
124 | * not dynamically alloced, so that it ends up in RMO where RTAS | |
125 | * can access it. | |
126 | */ | |
f2e0be5e | 127 | #define EEH_PCI_REGS_LOG_LEN 8192 |
d99bb1db LV |
128 | static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN]; |
129 | ||
e575f8db GS |
130 | /* |
131 | * The struct is used to maintain the EEH global statistic | |
132 | * information. Besides, the EEH global statistics will be | |
133 | * exported to user space through procfs | |
134 | */ | |
135 | struct eeh_stats { | |
136 | u64 no_device; /* PCI device not found */ | |
137 | u64 no_dn; /* OF node not found */ | |
138 | u64 no_cfg_addr; /* Config address not found */ | |
139 | u64 ignored_check; /* EEH check skipped */ | |
140 | u64 total_mmio_ffs; /* Total EEH checks */ | |
141 | u64 false_positives; /* Unnecessary EEH checks */ | |
142 | u64 slot_resets; /* PE reset */ | |
143 | }; | |
144 | ||
145 | static struct eeh_stats eeh_stats; | |
1da177e4 | 146 | |
7684b40c LV |
147 | #define IS_BRIDGE(class_code) (((class_code)<<16) == PCI_BASE_CLASS_BRIDGE) |
148 | ||
7f52a526 GS |
149 | static int __init eeh_setup(char *str) |
150 | { | |
151 | if (!strcmp(str, "off")) | |
05b1721d | 152 | eeh_add_flag(EEH_FORCE_DISABLED); |
a450e8f5 GS |
153 | else if (!strcmp(str, "early_log")) |
154 | eeh_add_flag(EEH_EARLY_DUMP_LOG); | |
7f52a526 GS |
155 | |
156 | return 1; | |
157 | } | |
158 | __setup("eeh=", eeh_setup); | |
159 | ||
f2e0be5e GS |
160 | /* |
161 | * This routine captures assorted PCI configuration space data | |
162 | * for the indicated PCI device, and puts them into a buffer | |
163 | * for RTAS error logging. | |
d99bb1db | 164 | */ |
f2e0be5e | 165 | static size_t eeh_dump_dev_log(struct eeh_dev *edev, char *buf, size_t len) |
d99bb1db | 166 | { |
f631acd3 | 167 | struct device_node *dn = eeh_dev_to_of_node(edev); |
d99bb1db | 168 | u32 cfg; |
fcf9892b | 169 | int cap, i; |
0ed352dd GS |
170 | int n = 0, l = 0; |
171 | char buffer[128]; | |
d99bb1db | 172 | |
f631acd3 | 173 | n += scnprintf(buf+n, len-n, "%s\n", dn->full_name); |
2d86c385 | 174 | pr_warn("EEH: of node=%s\n", dn->full_name); |
fcf9892b | 175 | |
3780444c | 176 | eeh_ops->read_config(dn, PCI_VENDOR_ID, 4, &cfg); |
fcf9892b | 177 | n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg); |
2d86c385 | 178 | pr_warn("EEH: PCI device/vendor: %08x\n", cfg); |
fcf9892b | 179 | |
3780444c | 180 | eeh_ops->read_config(dn, PCI_COMMAND, 4, &cfg); |
d99bb1db | 181 | n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg); |
2d86c385 | 182 | pr_warn("EEH: PCI cmd/status register: %08x\n", cfg); |
fcf9892b | 183 | |
0b9369f4 | 184 | /* Gather bridge-specific registers */ |
2a18dfc6 | 185 | if (edev->mode & EEH_DEV_BRIDGE) { |
3780444c | 186 | eeh_ops->read_config(dn, PCI_SEC_STATUS, 2, &cfg); |
0b9369f4 | 187 | n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg); |
2d86c385 | 188 | pr_warn("EEH: Bridge secondary status: %04x\n", cfg); |
0b9369f4 | 189 | |
3780444c | 190 | eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &cfg); |
0b9369f4 | 191 | n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg); |
2d86c385 | 192 | pr_warn("EEH: Bridge control: %04x\n", cfg); |
0b9369f4 LV |
193 | } |
194 | ||
fcf9892b | 195 | /* Dump out the PCI-X command and status regs */ |
2a18dfc6 | 196 | cap = edev->pcix_cap; |
fcf9892b | 197 | if (cap) { |
3780444c | 198 | eeh_ops->read_config(dn, cap, 4, &cfg); |
fcf9892b | 199 | n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg); |
2d86c385 | 200 | pr_warn("EEH: PCI-X cmd: %08x\n", cfg); |
fcf9892b | 201 | |
3780444c | 202 | eeh_ops->read_config(dn, cap+4, 4, &cfg); |
fcf9892b | 203 | n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg); |
2d86c385 | 204 | pr_warn("EEH: PCI-X status: %08x\n", cfg); |
fcf9892b LV |
205 | } |
206 | ||
2a18dfc6 GS |
207 | /* If PCI-E capable, dump PCI-E cap 10 */ |
208 | cap = edev->pcie_cap; | |
209 | if (cap) { | |
fcf9892b | 210 | n += scnprintf(buf+n, len-n, "pci-e cap10:\n"); |
2d86c385 | 211 | pr_warn("EEH: PCI-E capabilities and status follow:\n"); |
fcf9892b LV |
212 | |
213 | for (i=0; i<=8; i++) { | |
2a18dfc6 | 214 | eeh_ops->read_config(dn, cap+4*i, 4, &cfg); |
fcf9892b | 215 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); |
0ed352dd GS |
216 | |
217 | if ((i % 4) == 0) { | |
218 | if (i != 0) | |
219 | pr_warn("%s\n", buffer); | |
220 | ||
221 | l = scnprintf(buffer, sizeof(buffer), | |
222 | "EEH: PCI-E %02x: %08x ", | |
223 | 4*i, cfg); | |
224 | } else { | |
225 | l += scnprintf(buffer+l, sizeof(buffer)-l, | |
226 | "%08x ", cfg); | |
227 | } | |
228 | ||
fcf9892b | 229 | } |
0ed352dd GS |
230 | |
231 | pr_warn("%s\n", buffer); | |
2a18dfc6 | 232 | } |
fcf9892b | 233 | |
2a18dfc6 GS |
234 | /* If AER capable, dump it */ |
235 | cap = edev->aer_cap; | |
236 | if (cap) { | |
237 | n += scnprintf(buf+n, len-n, "pci-e AER:\n"); | |
238 | pr_warn("EEH: PCI-E AER capability register set follows:\n"); | |
239 | ||
0ed352dd | 240 | for (i=0; i<=13; i++) { |
2a18dfc6 GS |
241 | eeh_ops->read_config(dn, cap+4*i, 4, &cfg); |
242 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); | |
0ed352dd GS |
243 | |
244 | if ((i % 4) == 0) { | |
245 | if (i != 0) | |
246 | pr_warn("%s\n", buffer); | |
247 | ||
248 | l = scnprintf(buffer, sizeof(buffer), | |
249 | "EEH: PCI-E AER %02x: %08x ", | |
250 | 4*i, cfg); | |
251 | } else { | |
252 | l += scnprintf(buffer+l, sizeof(buffer)-l, | |
253 | "%08x ", cfg); | |
254 | } | |
fcf9892b | 255 | } |
0ed352dd GS |
256 | |
257 | pr_warn("%s\n", buffer); | |
fcf9892b | 258 | } |
0b9369f4 | 259 | |
d99bb1db LV |
260 | return n; |
261 | } | |
262 | ||
f2e0be5e GS |
263 | static void *eeh_dump_pe_log(void *data, void *flag) |
264 | { | |
265 | struct eeh_pe *pe = data; | |
266 | struct eeh_dev *edev, *tmp; | |
267 | size_t *plen = flag; | |
268 | ||
c59004cc GS |
269 | /* If the PE's config space is blocked, 0xFF's will be |
270 | * returned. It's pointless to collect the log in this | |
271 | * case. | |
272 | */ | |
273 | if (pe->state & EEH_PE_CFG_BLOCKED) | |
274 | return NULL; | |
275 | ||
f2e0be5e GS |
276 | eeh_pe_for_each_dev(pe, edev, tmp) |
277 | *plen += eeh_dump_dev_log(edev, pci_regs_buf + *plen, | |
278 | EEH_PCI_REGS_LOG_LEN - *plen); | |
279 | ||
280 | return NULL; | |
281 | } | |
282 | ||
cb3bc9d0 GS |
283 | /** |
284 | * eeh_slot_error_detail - Generate combined log including driver log and error log | |
ff477966 | 285 | * @pe: EEH PE |
cb3bc9d0 GS |
286 | * @severity: temporary or permanent error log |
287 | * | |
288 | * This routine should be called to generate the combined log, which | |
289 | * is comprised of driver log and error log. The driver log is figured | |
290 | * out from the config space of the corresponding PCI device, while | |
291 | * the error log is fetched through platform dependent function call. | |
292 | */ | |
ff477966 | 293 | void eeh_slot_error_detail(struct eeh_pe *pe, int severity) |
d99bb1db LV |
294 | { |
295 | size_t loglen = 0; | |
d99bb1db | 296 | |
c35ae179 GS |
297 | /* |
298 | * When the PHB is fenced or dead, it's pointless to collect | |
299 | * the data from PCI config space because it should return | |
300 | * 0xFF's. For ER, we still retrieve the data from the PCI | |
301 | * config space. | |
78954700 GS |
302 | * |
303 | * For pHyp, we have to enable IO for log retrieval. Otherwise, | |
304 | * 0xFF's is always returned from PCI config space. | |
c35ae179 | 305 | */ |
9e049375 | 306 | if (!(pe->type & EEH_PE_PHB)) { |
dc561fb9 | 307 | if (eeh_has_flag(EEH_ENABLE_IO_FOR_LOG)) |
78954700 | 308 | eeh_pci_enable(pe, EEH_OPT_THAW_MMIO); |
c35ae179 GS |
309 | eeh_ops->configure_bridge(pe); |
310 | eeh_pe_restore_bars(pe); | |
311 | ||
312 | pci_regs_buf[0] = 0; | |
f2e0be5e | 313 | eeh_pe_traverse(pe, eeh_dump_pe_log, &loglen); |
c35ae179 | 314 | } |
ff477966 GS |
315 | |
316 | eeh_ops->get_log(pe, severity, pci_regs_buf, loglen); | |
d99bb1db LV |
317 | } |
318 | ||
1da177e4 | 319 | /** |
cb3bc9d0 GS |
320 | * eeh_token_to_phys - Convert EEH address token to phys address |
321 | * @token: I/O token, should be address in the form 0xA.... | |
322 | * | |
323 | * This routine should be called to convert virtual I/O address | |
324 | * to physical one. | |
1da177e4 LT |
325 | */ |
326 | static inline unsigned long eeh_token_to_phys(unsigned long token) | |
327 | { | |
328 | pte_t *ptep; | |
329 | unsigned long pa; | |
12bc9f6f | 330 | int hugepage_shift; |
1da177e4 | 331 | |
12bc9f6f AK |
332 | /* |
333 | * We won't find hugepages here, iomem | |
334 | */ | |
335 | ptep = find_linux_pte_or_hugepte(init_mm.pgd, token, &hugepage_shift); | |
1da177e4 LT |
336 | if (!ptep) |
337 | return token; | |
12bc9f6f | 338 | WARN_ON(hugepage_shift); |
1da177e4 LT |
339 | pa = pte_pfn(*ptep) << PAGE_SHIFT; |
340 | ||
341 | return pa | (token & (PAGE_SIZE-1)); | |
342 | } | |
343 | ||
b95cd2cd GS |
344 | /* |
345 | * On PowerNV platform, we might already have fenced PHB there. | |
346 | * For that case, it's meaningless to recover frozen PE. Intead, | |
347 | * We have to handle fenced PHB firstly. | |
348 | */ | |
349 | static int eeh_phb_check_failure(struct eeh_pe *pe) | |
350 | { | |
351 | struct eeh_pe *phb_pe; | |
352 | unsigned long flags; | |
353 | int ret; | |
354 | ||
05b1721d | 355 | if (!eeh_has_flag(EEH_PROBE_MODE_DEV)) |
b95cd2cd GS |
356 | return -EPERM; |
357 | ||
358 | /* Find the PHB PE */ | |
359 | phb_pe = eeh_phb_pe_get(pe->phb); | |
360 | if (!phb_pe) { | |
0dae2743 GS |
361 | pr_warn("%s Can't find PE for PHB#%d\n", |
362 | __func__, pe->phb->global_number); | |
b95cd2cd GS |
363 | return -EEXIST; |
364 | } | |
365 | ||
366 | /* If the PHB has been in problematic state */ | |
367 | eeh_serialize_lock(&flags); | |
9e049375 | 368 | if (phb_pe->state & EEH_PE_ISOLATED) { |
b95cd2cd GS |
369 | ret = 0; |
370 | goto out; | |
371 | } | |
372 | ||
373 | /* Check PHB state */ | |
374 | ret = eeh_ops->get_state(phb_pe, NULL); | |
375 | if ((ret < 0) || | |
376 | (ret == EEH_STATE_NOT_SUPPORT) || | |
377 | (ret & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) == | |
378 | (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) { | |
379 | ret = 0; | |
380 | goto out; | |
381 | } | |
382 | ||
383 | /* Isolate the PHB and send event */ | |
384 | eeh_pe_state_mark(phb_pe, EEH_PE_ISOLATED); | |
385 | eeh_serialize_unlock(flags); | |
b95cd2cd | 386 | |
357b2f3d GS |
387 | pr_err("EEH: PHB#%x failure detected, location: %s\n", |
388 | phb_pe->phb->global_number, eeh_pe_loc_get(phb_pe)); | |
56ca4fde | 389 | dump_stack(); |
5293bf97 | 390 | eeh_send_failure_event(phb_pe); |
b95cd2cd GS |
391 | |
392 | return 1; | |
393 | out: | |
394 | eeh_serialize_unlock(flags); | |
395 | return ret; | |
396 | } | |
397 | ||
1da177e4 | 398 | /** |
f8f7d63f GS |
399 | * eeh_dev_check_failure - Check if all 1's data is due to EEH slot freeze |
400 | * @edev: eeh device | |
1da177e4 LT |
401 | * |
402 | * Check for an EEH failure for the given device node. Call this | |
403 | * routine if the result of a read was all 0xff's and you want to | |
404 | * find out if this is due to an EEH slot freeze. This routine | |
405 | * will query firmware for the EEH status. | |
406 | * | |
407 | * Returns 0 if there has not been an EEH error; otherwise returns | |
69376502 | 408 | * a non-zero value and queues up a slot isolation event notification. |
1da177e4 LT |
409 | * |
410 | * It is safe to call this routine in an interrupt context. | |
411 | */ | |
f8f7d63f | 412 | int eeh_dev_check_failure(struct eeh_dev *edev) |
1da177e4 LT |
413 | { |
414 | int ret; | |
1ad7a72c | 415 | int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); |
1da177e4 | 416 | unsigned long flags; |
f8f7d63f GS |
417 | struct device_node *dn; |
418 | struct pci_dev *dev; | |
357b2f3d | 419 | struct eeh_pe *pe, *parent_pe, *phb_pe; |
fd761fd8 | 420 | int rc = 0; |
f36c5227 | 421 | const char *location; |
1da177e4 | 422 | |
e575f8db | 423 | eeh_stats.total_mmio_ffs++; |
1da177e4 | 424 | |
2ec5a0ad | 425 | if (!eeh_enabled()) |
1da177e4 LT |
426 | return 0; |
427 | ||
f8f7d63f | 428 | if (!edev) { |
e575f8db | 429 | eeh_stats.no_dn++; |
1da177e4 | 430 | return 0; |
177bc936 | 431 | } |
f8f7d63f GS |
432 | dn = eeh_dev_to_of_node(edev); |
433 | dev = eeh_dev_to_pci_dev(edev); | |
2a58222f | 434 | pe = eeh_dev_to_pe(edev); |
1da177e4 LT |
435 | |
436 | /* Access to IO BARs might get this far and still not want checking. */ | |
66523d9f | 437 | if (!pe) { |
e575f8db | 438 | eeh_stats.ignored_check++; |
66523d9f GS |
439 | pr_debug("EEH: Ignored check for %s %s\n", |
440 | eeh_pci_name(dev), dn->full_name); | |
1da177e4 LT |
441 | return 0; |
442 | } | |
443 | ||
66523d9f | 444 | if (!pe->addr && !pe->config_addr) { |
e575f8db | 445 | eeh_stats.no_cfg_addr++; |
1da177e4 LT |
446 | return 0; |
447 | } | |
448 | ||
b95cd2cd GS |
449 | /* |
450 | * On PowerNV platform, we might already have fenced PHB | |
451 | * there and we need take care of that firstly. | |
452 | */ | |
453 | ret = eeh_phb_check_failure(pe); | |
454 | if (ret > 0) | |
455 | return ret; | |
456 | ||
05ec424e GS |
457 | /* |
458 | * If the PE isn't owned by us, we shouldn't check the | |
459 | * state. Instead, let the owner handle it if the PE has | |
460 | * been frozen. | |
461 | */ | |
462 | if (eeh_pe_passed(pe)) | |
463 | return 0; | |
464 | ||
fd761fd8 LV |
465 | /* If we already have a pending isolation event for this |
466 | * slot, we know it's bad already, we don't need to check. | |
467 | * Do this checking under a lock; as multiple PCI devices | |
468 | * in one slot might report errors simultaneously, and we | |
469 | * only want one error recovery routine running. | |
1da177e4 | 470 | */ |
4907581d | 471 | eeh_serialize_lock(&flags); |
fd761fd8 | 472 | rc = 1; |
66523d9f GS |
473 | if (pe->state & EEH_PE_ISOLATED) { |
474 | pe->check_count++; | |
475 | if (pe->check_count % EEH_MAX_FAILS == 0) { | |
f36c5227 | 476 | location = of_get_property(dn, "ibm,loc-code", NULL); |
cb3bc9d0 | 477 | printk(KERN_ERR "EEH: %d reads ignored for recovering device at " |
f36c5227 | 478 | "location=%s driver=%s pci addr=%s\n", |
66523d9f | 479 | pe->check_count, location, |
778a785f | 480 | eeh_driver_name(dev), eeh_pci_name(dev)); |
cb3bc9d0 | 481 | printk(KERN_ERR "EEH: Might be infinite loop in %s driver\n", |
778a785f | 482 | eeh_driver_name(dev)); |
5c1344e9 | 483 | dump_stack(); |
1da177e4 | 484 | } |
fd761fd8 | 485 | goto dn_unlock; |
1da177e4 LT |
486 | } |
487 | ||
488 | /* | |
489 | * Now test for an EEH failure. This is VERY expensive. | |
490 | * Note that the eeh_config_addr may be a parent device | |
491 | * in the case of a device behind a bridge, or it may be | |
492 | * function zero of a multi-function device. | |
493 | * In any case they must share a common PHB. | |
494 | */ | |
66523d9f | 495 | ret = eeh_ops->get_state(pe, NULL); |
76e6faf7 | 496 | |
39d16e29 | 497 | /* Note that config-io to empty slots may fail; |
cb3bc9d0 | 498 | * they are empty when they don't have children. |
eb594a47 GS |
499 | * We will punt with the following conditions: Failure to get |
500 | * PE's state, EEH not support and Permanently unavailable | |
501 | * state, PE is in good state. | |
cb3bc9d0 | 502 | */ |
eb594a47 GS |
503 | if ((ret < 0) || |
504 | (ret == EEH_STATE_NOT_SUPPORT) || | |
1ad7a72c | 505 | ((ret & active_flags) == active_flags)) { |
e575f8db | 506 | eeh_stats.false_positives++; |
66523d9f | 507 | pe->false_positives++; |
fd761fd8 LV |
508 | rc = 0; |
509 | goto dn_unlock; | |
76e6faf7 LV |
510 | } |
511 | ||
1ad7a72c GS |
512 | /* |
513 | * It should be corner case that the parent PE has been | |
514 | * put into frozen state as well. We should take care | |
515 | * that at first. | |
516 | */ | |
517 | parent_pe = pe->parent; | |
518 | while (parent_pe) { | |
519 | /* Hit the ceiling ? */ | |
520 | if (parent_pe->type & EEH_PE_PHB) | |
521 | break; | |
522 | ||
523 | /* Frozen parent PE ? */ | |
524 | ret = eeh_ops->get_state(parent_pe, NULL); | |
525 | if (ret > 0 && | |
526 | (ret & active_flags) != active_flags) | |
527 | pe = parent_pe; | |
528 | ||
529 | /* Next parent level */ | |
530 | parent_pe = parent_pe->parent; | |
531 | } | |
532 | ||
e575f8db | 533 | eeh_stats.slot_resets++; |
a84f273c | 534 | |
fd761fd8 LV |
535 | /* Avoid repeated reports of this failure, including problems |
536 | * with other functions on this device, and functions under | |
cb3bc9d0 GS |
537 | * bridges. |
538 | */ | |
66523d9f | 539 | eeh_pe_state_mark(pe, EEH_PE_ISOLATED); |
4907581d | 540 | eeh_serialize_unlock(flags); |
1da177e4 | 541 | |
1da177e4 LT |
542 | /* Most EEH events are due to device driver bugs. Having |
543 | * a stack trace will help the device-driver authors figure | |
cb3bc9d0 GS |
544 | * out what happened. So print that out. |
545 | */ | |
357b2f3d GS |
546 | phb_pe = eeh_phb_pe_get(pe->phb); |
547 | pr_err("EEH: Frozen PHB#%x-PE#%x detected\n", | |
548 | pe->phb->global_number, pe->addr); | |
549 | pr_err("EEH: PE location: %s, PHB location: %s\n", | |
550 | eeh_pe_loc_get(pe), eeh_pe_loc_get(phb_pe)); | |
56ca4fde GS |
551 | dump_stack(); |
552 | ||
5293bf97 GS |
553 | eeh_send_failure_event(pe); |
554 | ||
fd761fd8 LV |
555 | return 1; |
556 | ||
557 | dn_unlock: | |
4907581d | 558 | eeh_serialize_unlock(flags); |
fd761fd8 | 559 | return rc; |
1da177e4 LT |
560 | } |
561 | ||
f8f7d63f | 562 | EXPORT_SYMBOL_GPL(eeh_dev_check_failure); |
1da177e4 LT |
563 | |
564 | /** | |
cb3bc9d0 | 565 | * eeh_check_failure - Check if all 1's data is due to EEH slot freeze |
3e938052 | 566 | * @token: I/O address |
1da177e4 | 567 | * |
3e938052 | 568 | * Check for an EEH failure at the given I/O address. Call this |
1da177e4 | 569 | * routine if the result of a read was all 0xff's and you want to |
3e938052 | 570 | * find out if this is due to an EEH slot freeze event. This routine |
1da177e4 LT |
571 | * will query firmware for the EEH status. |
572 | * | |
573 | * Note this routine is safe to call in an interrupt context. | |
574 | */ | |
3e938052 | 575 | int eeh_check_failure(const volatile void __iomem *token) |
1da177e4 LT |
576 | { |
577 | unsigned long addr; | |
f8f7d63f | 578 | struct eeh_dev *edev; |
1da177e4 LT |
579 | |
580 | /* Finding the phys addr + pci device; this is pretty quick. */ | |
581 | addr = eeh_token_to_phys((unsigned long __force) token); | |
3ab96a02 | 582 | edev = eeh_addr_cache_get_dev(addr); |
f8f7d63f | 583 | if (!edev) { |
e575f8db | 584 | eeh_stats.no_device++; |
3e938052 | 585 | return 0; |
177bc936 | 586 | } |
1da177e4 | 587 | |
3e938052 | 588 | return eeh_dev_check_failure(edev); |
1da177e4 | 589 | } |
1da177e4 LT |
590 | EXPORT_SYMBOL(eeh_check_failure); |
591 | ||
6dee3fb9 | 592 | |
47b5c838 | 593 | /** |
cce4b2d2 | 594 | * eeh_pci_enable - Enable MMIO or DMA transfers for this slot |
ff477966 | 595 | * @pe: EEH PE |
cb3bc9d0 GS |
596 | * |
597 | * This routine should be called to reenable frozen MMIO or DMA | |
598 | * so that it would work correctly again. It's useful while doing | |
599 | * recovery or log collection on the indicated device. | |
47b5c838 | 600 | */ |
ff477966 | 601 | int eeh_pci_enable(struct eeh_pe *pe, int function) |
47b5c838 | 602 | { |
4d4f577e | 603 | int active_flag, rc; |
78954700 GS |
604 | |
605 | /* | |
606 | * pHyp doesn't allow to enable IO or DMA on unfrozen PE. | |
607 | * Also, it's pointless to enable them on unfrozen PE. So | |
4d4f577e | 608 | * we have to check before enabling IO or DMA. |
78954700 | 609 | */ |
4d4f577e GS |
610 | switch (function) { |
611 | case EEH_OPT_THAW_MMIO: | |
612 | active_flag = EEH_STATE_MMIO_ACTIVE; | |
613 | break; | |
614 | case EEH_OPT_THAW_DMA: | |
615 | active_flag = EEH_STATE_DMA_ACTIVE; | |
616 | break; | |
617 | case EEH_OPT_DISABLE: | |
618 | case EEH_OPT_ENABLE: | |
619 | case EEH_OPT_FREEZE_PE: | |
620 | active_flag = 0; | |
621 | break; | |
622 | default: | |
623 | pr_warn("%s: Invalid function %d\n", | |
624 | __func__, function); | |
625 | return -EINVAL; | |
626 | } | |
627 | ||
628 | /* | |
629 | * Check if IO or DMA has been enabled before | |
630 | * enabling them. | |
631 | */ | |
632 | if (active_flag) { | |
78954700 GS |
633 | rc = eeh_ops->get_state(pe, NULL); |
634 | if (rc < 0) | |
635 | return rc; | |
636 | ||
4d4f577e GS |
637 | /* Needn't enable it at all */ |
638 | if (rc == EEH_STATE_NOT_SUPPORT) | |
639 | return 0; | |
640 | ||
641 | /* It's already enabled */ | |
642 | if (rc & active_flag) | |
78954700 GS |
643 | return 0; |
644 | } | |
47b5c838 | 645 | |
4d4f577e GS |
646 | |
647 | /* Issue the request */ | |
ff477966 | 648 | rc = eeh_ops->set_option(pe, function); |
47b5c838 | 649 | if (rc) |
78954700 GS |
650 | pr_warn("%s: Unexpected state change %d on " |
651 | "PHB#%d-PE#%x, err=%d\n", | |
652 | __func__, function, pe->phb->global_number, | |
653 | pe->addr, rc); | |
47b5c838 | 654 | |
4d4f577e GS |
655 | /* Check if the request is finished successfully */ |
656 | if (active_flag) { | |
657 | rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC); | |
658 | if (rc <= 0) | |
659 | return rc; | |
78954700 | 660 | |
4d4f577e GS |
661 | if (rc & active_flag) |
662 | return 0; | |
78954700 | 663 | |
4d4f577e GS |
664 | return -EIO; |
665 | } | |
fa1be476 | 666 | |
47b5c838 LV |
667 | return rc; |
668 | } | |
669 | ||
28158cd1 GS |
670 | static void *eeh_disable_and_save_dev_state(void *data, void *userdata) |
671 | { | |
672 | struct eeh_dev *edev = data; | |
673 | struct pci_dev *pdev = eeh_dev_to_pci_dev(edev); | |
674 | struct pci_dev *dev = userdata; | |
675 | ||
676 | /* | |
677 | * The caller should have disabled and saved the | |
678 | * state for the specified device | |
679 | */ | |
680 | if (!pdev || pdev == dev) | |
681 | return NULL; | |
682 | ||
683 | /* Ensure we have D0 power state */ | |
684 | pci_set_power_state(pdev, PCI_D0); | |
685 | ||
686 | /* Save device state */ | |
687 | pci_save_state(pdev); | |
688 | ||
689 | /* | |
690 | * Disable device to avoid any DMA traffic and | |
691 | * interrupt from the device | |
692 | */ | |
693 | pci_write_config_word(pdev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); | |
694 | ||
695 | return NULL; | |
696 | } | |
697 | ||
698 | static void *eeh_restore_dev_state(void *data, void *userdata) | |
699 | { | |
700 | struct eeh_dev *edev = data; | |
701 | struct device_node *dn = eeh_dev_to_of_node(edev); | |
702 | struct pci_dev *pdev = eeh_dev_to_pci_dev(edev); | |
703 | struct pci_dev *dev = userdata; | |
704 | ||
705 | if (!pdev) | |
706 | return NULL; | |
707 | ||
708 | /* Apply customization from firmware */ | |
709 | if (dn && eeh_ops->restore_config) | |
710 | eeh_ops->restore_config(dn); | |
711 | ||
712 | /* The caller should restore state for the specified device */ | |
713 | if (pdev != dev) | |
714 | pci_save_state(pdev); | |
715 | ||
716 | return NULL; | |
717 | } | |
718 | ||
00c2ae35 BK |
719 | /** |
720 | * pcibios_set_pcie_slot_reset - Set PCI-E reset state | |
cb3bc9d0 GS |
721 | * @dev: pci device struct |
722 | * @state: reset state to enter | |
00c2ae35 BK |
723 | * |
724 | * Return value: | |
725 | * 0 if success | |
cb3bc9d0 | 726 | */ |
00c2ae35 BK |
727 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) |
728 | { | |
c270a24c | 729 | struct eeh_dev *edev = pci_dev_to_eeh_dev(dev); |
2a58222f | 730 | struct eeh_pe *pe = eeh_dev_to_pe(edev); |
c270a24c GS |
731 | |
732 | if (!pe) { | |
733 | pr_err("%s: No PE found on PCI device %s\n", | |
734 | __func__, pci_name(dev)); | |
735 | return -EINVAL; | |
736 | } | |
00c2ae35 BK |
737 | |
738 | switch (state) { | |
739 | case pcie_deassert_reset: | |
c270a24c | 740 | eeh_ops->reset(pe, EEH_RESET_DEACTIVATE); |
28158cd1 | 741 | eeh_unfreeze_pe(pe, false); |
8a6b3710 | 742 | eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED); |
28158cd1 | 743 | eeh_pe_dev_traverse(pe, eeh_restore_dev_state, dev); |
00c2ae35 BK |
744 | break; |
745 | case pcie_hot_reset: | |
28158cd1 GS |
746 | eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE); |
747 | eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev); | |
8a6b3710 | 748 | eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED); |
c270a24c | 749 | eeh_ops->reset(pe, EEH_RESET_HOT); |
00c2ae35 BK |
750 | break; |
751 | case pcie_warm_reset: | |
28158cd1 GS |
752 | eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE); |
753 | eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev); | |
8a6b3710 | 754 | eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED); |
c270a24c | 755 | eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL); |
00c2ae35 BK |
756 | break; |
757 | default: | |
8a6b3710 | 758 | eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED); |
00c2ae35 BK |
759 | return -EINVAL; |
760 | }; | |
761 | ||
762 | return 0; | |
763 | } | |
764 | ||
cb5b5624 | 765 | /** |
c270a24c GS |
766 | * eeh_set_pe_freset - Check the required reset for the indicated device |
767 | * @data: EEH device | |
768 | * @flag: return value | |
cb3bc9d0 GS |
769 | * |
770 | * Each device might have its preferred reset type: fundamental or | |
771 | * hot reset. The routine is used to collected the information for | |
772 | * the indicated device and its children so that the bunch of the | |
773 | * devices could be reset properly. | |
774 | */ | |
c270a24c | 775 | static void *eeh_set_dev_freset(void *data, void *flag) |
cb3bc9d0 GS |
776 | { |
777 | struct pci_dev *dev; | |
c270a24c GS |
778 | unsigned int *freset = (unsigned int *)flag; |
779 | struct eeh_dev *edev = (struct eeh_dev *)data; | |
6dee3fb9 | 780 | |
c270a24c | 781 | dev = eeh_dev_to_pci_dev(edev); |
cb3bc9d0 GS |
782 | if (dev) |
783 | *freset |= dev->needs_freset; | |
784 | ||
c270a24c | 785 | return NULL; |
cb3bc9d0 GS |
786 | } |
787 | ||
788 | /** | |
cce4b2d2 | 789 | * eeh_reset_pe_once - Assert the pci #RST line for 1/4 second |
c270a24c | 790 | * @pe: EEH PE |
cb3bc9d0 GS |
791 | * |
792 | * Assert the PCI #RST line for 1/4 second. | |
793 | */ | |
c270a24c | 794 | static void eeh_reset_pe_once(struct eeh_pe *pe) |
6dee3fb9 | 795 | { |
308fc4f8 | 796 | unsigned int freset = 0; |
6e19314c | 797 | |
308fc4f8 RL |
798 | /* Determine type of EEH reset required for |
799 | * Partitionable Endpoint, a hot-reset (1) | |
800 | * or a fundamental reset (3). | |
801 | * A fundamental reset required by any device under | |
802 | * Partitionable Endpoint trumps hot-reset. | |
a84f273c | 803 | */ |
c270a24c | 804 | eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset); |
308fc4f8 RL |
805 | |
806 | if (freset) | |
c270a24c | 807 | eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL); |
6e19314c | 808 | else |
c270a24c | 809 | eeh_ops->reset(pe, EEH_RESET_HOT); |
6dee3fb9 | 810 | |
c270a24c | 811 | eeh_ops->reset(pe, EEH_RESET_DEACTIVATE); |
e1029263 LV |
812 | } |
813 | ||
cb3bc9d0 | 814 | /** |
cce4b2d2 | 815 | * eeh_reset_pe - Reset the indicated PE |
c270a24c | 816 | * @pe: EEH PE |
cb3bc9d0 GS |
817 | * |
818 | * This routine should be called to reset indicated device, including | |
819 | * PE. A PE might include multiple PCI devices and sometimes PCI bridges | |
820 | * might be involved as well. | |
821 | */ | |
c270a24c | 822 | int eeh_reset_pe(struct eeh_pe *pe) |
e1029263 | 823 | { |
326a98ea | 824 | int flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); |
b85743ee | 825 | int i, state, ret; |
e1029263 | 826 | |
28bf36f9 GS |
827 | /* Mark as reset and block config space */ |
828 | eeh_pe_state_mark(pe, EEH_PE_RESET | EEH_PE_CFG_BLOCKED); | |
829 | ||
9c547768 | 830 | /* Take three shots at resetting the bus */ |
b85743ee | 831 | for (i = 0; i < 3; i++) { |
c270a24c | 832 | eeh_reset_pe_once(pe); |
6dee3fb9 | 833 | |
78954700 GS |
834 | /* |
835 | * EEH_PE_ISOLATED is expected to be removed after | |
836 | * BAR restore. | |
837 | */ | |
b85743ee GS |
838 | state = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC); |
839 | if ((state & flags) == flags) { | |
840 | ret = 0; | |
841 | goto out; | |
842 | } | |
e1029263 | 843 | |
b85743ee GS |
844 | if (state < 0) { |
845 | pr_warn("%s: Unrecoverable slot failure on PHB#%d-PE#%x", | |
c270a24c | 846 | __func__, pe->phb->global_number, pe->addr); |
b85743ee GS |
847 | ret = -ENOTRECOVERABLE; |
848 | goto out; | |
e1029263 | 849 | } |
b85743ee GS |
850 | |
851 | /* We might run out of credits */ | |
852 | ret = -EIO; | |
853 | pr_warn("%s: Failure %d resetting PHB#%x-PE#%x\n (%d)\n", | |
854 | __func__, state, pe->phb->global_number, pe->addr, (i + 1)); | |
6dee3fb9 | 855 | } |
b6495c0c | 856 | |
b85743ee | 857 | out: |
28bf36f9 | 858 | eeh_pe_state_clear(pe, EEH_PE_RESET | EEH_PE_CFG_BLOCKED); |
b85743ee | 859 | return ret; |
6dee3fb9 LV |
860 | } |
861 | ||
8b553f32 | 862 | /** |
cb3bc9d0 | 863 | * eeh_save_bars - Save device bars |
f631acd3 | 864 | * @edev: PCI device associated EEH device |
8b553f32 LV |
865 | * |
866 | * Save the values of the device bars. Unlike the restore | |
867 | * routine, this routine is *not* recursive. This is because | |
31116f0b | 868 | * PCI devices are added individually; but, for the restore, |
8b553f32 LV |
869 | * an entire slot is reset at a time. |
870 | */ | |
d7bb8862 | 871 | void eeh_save_bars(struct eeh_dev *edev) |
8b553f32 LV |
872 | { |
873 | int i; | |
f631acd3 | 874 | struct device_node *dn; |
8b553f32 | 875 | |
f631acd3 | 876 | if (!edev) |
8b553f32 | 877 | return; |
f631acd3 | 878 | dn = eeh_dev_to_of_node(edev); |
a84f273c | 879 | |
8b553f32 | 880 | for (i = 0; i < 16; i++) |
3780444c | 881 | eeh_ops->read_config(dn, i * 4, 4, &edev->config_space[i]); |
bf898ec5 GS |
882 | |
883 | /* | |
884 | * For PCI bridges including root port, we need enable bus | |
885 | * master explicitly. Otherwise, it can't fetch IODA table | |
886 | * entries correctly. So we cache the bit in advance so that | |
887 | * we can restore it after reset, either PHB range or PE range. | |
888 | */ | |
889 | if (edev->mode & EEH_DEV_BRIDGE) | |
890 | edev->config_space[1] |= PCI_COMMAND_MASTER; | |
8b553f32 LV |
891 | } |
892 | ||
aa1e6374 GS |
893 | /** |
894 | * eeh_ops_register - Register platform dependent EEH operations | |
895 | * @ops: platform dependent EEH operations | |
896 | * | |
897 | * Register the platform dependent EEH operation callback | |
898 | * functions. The platform should call this function before | |
899 | * any other EEH operations. | |
900 | */ | |
901 | int __init eeh_ops_register(struct eeh_ops *ops) | |
902 | { | |
903 | if (!ops->name) { | |
0dae2743 | 904 | pr_warn("%s: Invalid EEH ops name for %p\n", |
aa1e6374 GS |
905 | __func__, ops); |
906 | return -EINVAL; | |
907 | } | |
908 | ||
909 | if (eeh_ops && eeh_ops != ops) { | |
0dae2743 | 910 | pr_warn("%s: EEH ops of platform %s already existing (%s)\n", |
aa1e6374 GS |
911 | __func__, eeh_ops->name, ops->name); |
912 | return -EEXIST; | |
913 | } | |
914 | ||
915 | eeh_ops = ops; | |
916 | ||
917 | return 0; | |
918 | } | |
919 | ||
920 | /** | |
921 | * eeh_ops_unregister - Unreigster platform dependent EEH operations | |
922 | * @name: name of EEH platform operations | |
923 | * | |
924 | * Unregister the platform dependent EEH operation callback | |
925 | * functions. | |
926 | */ | |
927 | int __exit eeh_ops_unregister(const char *name) | |
928 | { | |
929 | if (!name || !strlen(name)) { | |
0dae2743 | 930 | pr_warn("%s: Invalid EEH ops name\n", |
aa1e6374 GS |
931 | __func__); |
932 | return -EINVAL; | |
933 | } | |
934 | ||
935 | if (eeh_ops && !strcmp(eeh_ops->name, name)) { | |
936 | eeh_ops = NULL; | |
937 | return 0; | |
938 | } | |
939 | ||
940 | return -EEXIST; | |
941 | } | |
942 | ||
66f9af83 GS |
943 | static int eeh_reboot_notifier(struct notifier_block *nb, |
944 | unsigned long action, void *unused) | |
945 | { | |
05b1721d | 946 | eeh_clear_flag(EEH_ENABLED); |
66f9af83 GS |
947 | return NOTIFY_DONE; |
948 | } | |
949 | ||
950 | static struct notifier_block eeh_reboot_nb = { | |
951 | .notifier_call = eeh_reboot_notifier, | |
952 | }; | |
953 | ||
cb3bc9d0 GS |
954 | /** |
955 | * eeh_init - EEH initialization | |
956 | * | |
1da177e4 LT |
957 | * Initialize EEH by trying to enable it for all of the adapters in the system. |
958 | * As a side effect we can determine here if eeh is supported at all. | |
959 | * Note that we leave EEH on so failed config cycles won't cause a machine | |
960 | * check. If a user turns off EEH for a particular adapter they are really | |
961 | * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't | |
962 | * grant access to a slot if EEH isn't enabled, and so we always enable | |
963 | * EEH for all slots/all devices. | |
964 | * | |
965 | * The eeh-force-off option disables EEH checking globally, for all slots. | |
966 | * Even if force-off is set, the EEH hardware is still enabled, so that | |
967 | * newer systems can boot. | |
968 | */ | |
eeb6361f | 969 | int eeh_init(void) |
1da177e4 | 970 | { |
1a5c2e63 | 971 | struct pci_controller *hose, *tmp; |
ff57b454 | 972 | struct pci_dn *pdn; |
51fb5f56 GS |
973 | static int cnt = 0; |
974 | int ret = 0; | |
975 | ||
976 | /* | |
977 | * We have to delay the initialization on PowerNV after | |
978 | * the PCI hierarchy tree has been built because the PEs | |
979 | * are figured out based on PCI devices instead of device | |
980 | * tree nodes | |
981 | */ | |
982 | if (machine_is(powernv) && cnt++ <= 0) | |
983 | return ret; | |
e2af155c | 984 | |
66f9af83 GS |
985 | /* Register reboot notifier */ |
986 | ret = register_reboot_notifier(&eeh_reboot_nb); | |
987 | if (ret) { | |
988 | pr_warn("%s: Failed to register notifier (%d)\n", | |
989 | __func__, ret); | |
990 | return ret; | |
991 | } | |
992 | ||
e2af155c GS |
993 | /* call platform initialization function */ |
994 | if (!eeh_ops) { | |
0dae2743 | 995 | pr_warn("%s: Platform EEH operation not found\n", |
e2af155c | 996 | __func__); |
35e5cfe2 | 997 | return -EEXIST; |
221195fb | 998 | } else if ((ret = eeh_ops->init())) |
35e5cfe2 | 999 | return ret; |
1da177e4 | 1000 | |
c8608558 GS |
1001 | /* Initialize EEH event */ |
1002 | ret = eeh_event_init(); | |
1003 | if (ret) | |
1004 | return ret; | |
1005 | ||
1a5c2e63 | 1006 | /* Enable EEH for all adapters */ |
ff57b454 GS |
1007 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { |
1008 | pdn = hose->pci_data; | |
1009 | traverse_pci_dn(pdn, eeh_ops->probe, NULL); | |
1da177e4 LT |
1010 | } |
1011 | ||
21fd21f5 GS |
1012 | /* |
1013 | * Call platform post-initialization. Actually, It's good chance | |
1014 | * to inform platform that EEH is ready to supply service if the | |
1015 | * I/O cache stuff has been built up. | |
1016 | */ | |
1017 | if (eeh_ops->post_init) { | |
1018 | ret = eeh_ops->post_init(); | |
1019 | if (ret) | |
1020 | return ret; | |
1021 | } | |
1022 | ||
2ec5a0ad | 1023 | if (eeh_enabled()) |
d7bb8862 | 1024 | pr_info("EEH: PCI Enhanced I/O Error Handling Enabled\n"); |
1da177e4 | 1025 | else |
0dae2743 | 1026 | pr_warn("EEH: No capable adapters found\n"); |
35e5cfe2 GS |
1027 | |
1028 | return ret; | |
1da177e4 LT |
1029 | } |
1030 | ||
35e5cfe2 GS |
1031 | core_initcall_sync(eeh_init); |
1032 | ||
1da177e4 | 1033 | /** |
cb3bc9d0 | 1034 | * eeh_add_device_early - Enable EEH for the indicated device_node |
ff57b454 | 1035 | * @pdn: PCI device node for which to set up EEH |
1da177e4 LT |
1036 | * |
1037 | * This routine must be used to perform EEH initialization for PCI | |
1038 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
1039 | * This routine must be called before any i/o is performed to the | |
1040 | * adapter (inluding any config-space i/o). | |
1041 | * Whether this actually enables EEH or not for this device depends | |
1042 | * on the CEC architecture, type of the device, on earlier boot | |
1043 | * command-line arguments & etc. | |
1044 | */ | |
ff57b454 | 1045 | void eeh_add_device_early(struct pci_dn *pdn) |
1da177e4 LT |
1046 | { |
1047 | struct pci_controller *phb; | |
ff57b454 | 1048 | struct eeh_dev *edev = pdn_to_eeh_dev(pdn); |
1da177e4 | 1049 | |
ff57b454 | 1050 | if (!edev) |
1da177e4 | 1051 | return; |
f751f841 LV |
1052 | |
1053 | /* USB Bus children of PCI devices will not have BUID's */ | |
ff57b454 GS |
1054 | phb = edev->phb; |
1055 | if (NULL == phb || | |
1056 | (eeh_has_flag(EEH_PROBE_MODE_DEVTREE) && 0 == phb->buid)) | |
1da177e4 | 1057 | return; |
1da177e4 | 1058 | |
ff57b454 | 1059 | eeh_ops->probe(pdn, NULL); |
1da177e4 | 1060 | } |
1da177e4 | 1061 | |
cb3bc9d0 GS |
1062 | /** |
1063 | * eeh_add_device_tree_early - Enable EEH for the indicated device | |
ff57b454 | 1064 | * @pdn: PCI device node |
cb3bc9d0 GS |
1065 | * |
1066 | * This routine must be used to perform EEH initialization for the | |
1067 | * indicated PCI device that was added after system boot (e.g. | |
1068 | * hotplug, dlpar). | |
1069 | */ | |
ff57b454 | 1070 | void eeh_add_device_tree_early(struct pci_dn *pdn) |
e2a296ee | 1071 | { |
ff57b454 GS |
1072 | struct pci_dn *n; |
1073 | ||
1074 | if (!pdn) | |
1075 | return; | |
acaa6176 | 1076 | |
ff57b454 GS |
1077 | list_for_each_entry(n, &pdn->child_list, list) |
1078 | eeh_add_device_tree_early(n); | |
1079 | eeh_add_device_early(pdn); | |
e2a296ee LV |
1080 | } |
1081 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_early); | |
1082 | ||
1da177e4 | 1083 | /** |
cb3bc9d0 | 1084 | * eeh_add_device_late - Perform EEH initialization for the indicated pci device |
1da177e4 LT |
1085 | * @dev: pci device for which to set up EEH |
1086 | * | |
1087 | * This routine must be used to complete EEH initialization for PCI | |
1088 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
1089 | */ | |
f2856491 | 1090 | void eeh_add_device_late(struct pci_dev *dev) |
1da177e4 | 1091 | { |
56b0fca3 | 1092 | struct device_node *dn; |
f631acd3 | 1093 | struct eeh_dev *edev; |
56b0fca3 | 1094 | |
2ec5a0ad | 1095 | if (!dev || !eeh_enabled()) |
1da177e4 LT |
1096 | return; |
1097 | ||
57b066ff | 1098 | pr_debug("EEH: Adding device %s\n", pci_name(dev)); |
1da177e4 | 1099 | |
56b0fca3 | 1100 | dn = pci_device_to_OF_node(dev); |
2ef822c5 | 1101 | edev = of_node_to_eeh_dev(dn); |
f631acd3 | 1102 | if (edev->pdev == dev) { |
57b066ff BH |
1103 | pr_debug("EEH: Already referenced !\n"); |
1104 | return; | |
1105 | } | |
f5c57710 GS |
1106 | |
1107 | /* | |
1108 | * The EEH cache might not be removed correctly because of | |
1109 | * unbalanced kref to the device during unplug time, which | |
1110 | * relies on pcibios_release_device(). So we have to remove | |
1111 | * that here explicitly. | |
1112 | */ | |
1113 | if (edev->pdev) { | |
1114 | eeh_rmv_from_parent_pe(edev); | |
1115 | eeh_addr_cache_rmv_dev(edev->pdev); | |
1116 | eeh_sysfs_remove_device(edev->pdev); | |
ab55d218 | 1117 | edev->mode &= ~EEH_DEV_SYSFS; |
f5c57710 | 1118 | |
f26c7a03 GS |
1119 | /* |
1120 | * We definitely should have the PCI device removed | |
1121 | * though it wasn't correctly. So we needn't call | |
1122 | * into error handler afterwards. | |
1123 | */ | |
1124 | edev->mode |= EEH_DEV_NO_HANDLER; | |
1125 | ||
f5c57710 GS |
1126 | edev->pdev = NULL; |
1127 | dev->dev.archdata.edev = NULL; | |
1128 | } | |
57b066ff | 1129 | |
f631acd3 GS |
1130 | edev->pdev = dev; |
1131 | dev->dev.archdata.edev = edev; | |
56b0fca3 | 1132 | |
3ab96a02 | 1133 | eeh_addr_cache_insert_dev(dev); |
1da177e4 | 1134 | } |
794e085e | 1135 | |
cb3bc9d0 GS |
1136 | /** |
1137 | * eeh_add_device_tree_late - Perform EEH initialization for the indicated PCI bus | |
1138 | * @bus: PCI bus | |
1139 | * | |
1140 | * This routine must be used to perform EEH initialization for PCI | |
1141 | * devices which are attached to the indicated PCI bus. The PCI bus | |
1142 | * is added after system boot through hotplug or dlpar. | |
1143 | */ | |
794e085e NF |
1144 | void eeh_add_device_tree_late(struct pci_bus *bus) |
1145 | { | |
1146 | struct pci_dev *dev; | |
1147 | ||
1148 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
a84f273c GS |
1149 | eeh_add_device_late(dev); |
1150 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1151 | struct pci_bus *subbus = dev->subordinate; | |
1152 | if (subbus) | |
1153 | eeh_add_device_tree_late(subbus); | |
1154 | } | |
794e085e NF |
1155 | } |
1156 | } | |
1157 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_late); | |
1da177e4 | 1158 | |
6a040ce7 TLSC |
1159 | /** |
1160 | * eeh_add_sysfs_files - Add EEH sysfs files for the indicated PCI bus | |
1161 | * @bus: PCI bus | |
1162 | * | |
1163 | * This routine must be used to add EEH sysfs files for PCI | |
1164 | * devices which are attached to the indicated PCI bus. The PCI bus | |
1165 | * is added after system boot through hotplug or dlpar. | |
1166 | */ | |
1167 | void eeh_add_sysfs_files(struct pci_bus *bus) | |
1168 | { | |
1169 | struct pci_dev *dev; | |
1170 | ||
1171 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1172 | eeh_sysfs_add_device(dev); | |
1173 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1174 | struct pci_bus *subbus = dev->subordinate; | |
1175 | if (subbus) | |
1176 | eeh_add_sysfs_files(subbus); | |
1177 | } | |
1178 | } | |
1179 | } | |
1180 | EXPORT_SYMBOL_GPL(eeh_add_sysfs_files); | |
1181 | ||
1da177e4 | 1182 | /** |
cb3bc9d0 | 1183 | * eeh_remove_device - Undo EEH setup for the indicated pci device |
1da177e4 LT |
1184 | * @dev: pci device to be removed |
1185 | * | |
794e085e NF |
1186 | * This routine should be called when a device is removed from |
1187 | * a running system (e.g. by hotplug or dlpar). It unregisters | |
1188 | * the PCI device from the EEH subsystem. I/O errors affecting | |
1189 | * this device will no longer be detected after this call; thus, | |
1190 | * i/o errors affecting this slot may leave this device unusable. | |
1da177e4 | 1191 | */ |
807a827d | 1192 | void eeh_remove_device(struct pci_dev *dev) |
1da177e4 | 1193 | { |
f631acd3 GS |
1194 | struct eeh_dev *edev; |
1195 | ||
2ec5a0ad | 1196 | if (!dev || !eeh_enabled()) |
1da177e4 | 1197 | return; |
f631acd3 | 1198 | edev = pci_dev_to_eeh_dev(dev); |
1da177e4 LT |
1199 | |
1200 | /* Unregister the device with the EEH/PCI address search system */ | |
57b066ff | 1201 | pr_debug("EEH: Removing device %s\n", pci_name(dev)); |
56b0fca3 | 1202 | |
f5c57710 | 1203 | if (!edev || !edev->pdev || !edev->pe) { |
57b066ff BH |
1204 | pr_debug("EEH: Not referenced !\n"); |
1205 | return; | |
b055a9e1 | 1206 | } |
f5c57710 GS |
1207 | |
1208 | /* | |
1209 | * During the hotplug for EEH error recovery, we need the EEH | |
1210 | * device attached to the parent PE in order for BAR restore | |
1211 | * a bit later. So we keep it for BAR restore and remove it | |
1212 | * from the parent PE during the BAR resotre. | |
1213 | */ | |
f631acd3 GS |
1214 | edev->pdev = NULL; |
1215 | dev->dev.archdata.edev = NULL; | |
f5c57710 GS |
1216 | if (!(edev->pe->state & EEH_PE_KEEP)) |
1217 | eeh_rmv_from_parent_pe(edev); | |
1218 | else | |
1219 | edev->mode |= EEH_DEV_DISCONNECTED; | |
57b066ff | 1220 | |
f26c7a03 GS |
1221 | /* |
1222 | * We're removing from the PCI subsystem, that means | |
1223 | * the PCI device driver can't support EEH or not | |
1224 | * well. So we rely on hotplug completely to do recovery | |
1225 | * for the specific PCI device. | |
1226 | */ | |
1227 | edev->mode |= EEH_DEV_NO_HANDLER; | |
1228 | ||
3ab96a02 | 1229 | eeh_addr_cache_rmv_dev(dev); |
57b066ff | 1230 | eeh_sysfs_remove_device(dev); |
ab55d218 | 1231 | edev->mode &= ~EEH_DEV_SYSFS; |
1da177e4 | 1232 | } |
1da177e4 | 1233 | |
4eeeff0e GS |
1234 | int eeh_unfreeze_pe(struct eeh_pe *pe, bool sw_state) |
1235 | { | |
1236 | int ret; | |
1237 | ||
1238 | ret = eeh_pci_enable(pe, EEH_OPT_THAW_MMIO); | |
1239 | if (ret) { | |
1240 | pr_warn("%s: Failure %d enabling IO on PHB#%x-PE#%x\n", | |
1241 | __func__, ret, pe->phb->global_number, pe->addr); | |
1242 | return ret; | |
1243 | } | |
1244 | ||
1245 | ret = eeh_pci_enable(pe, EEH_OPT_THAW_DMA); | |
1246 | if (ret) { | |
1247 | pr_warn("%s: Failure %d enabling DMA on PHB#%x-PE#%x\n", | |
1248 | __func__, ret, pe->phb->global_number, pe->addr); | |
1249 | return ret; | |
1250 | } | |
1251 | ||
1252 | /* Clear software isolated state */ | |
1253 | if (sw_state && (pe->state & EEH_PE_ISOLATED)) | |
1254 | eeh_pe_state_clear(pe, EEH_PE_ISOLATED); | |
1255 | ||
1256 | return ret; | |
1257 | } | |
1258 | ||
5cfb20b9 GS |
1259 | |
1260 | static struct pci_device_id eeh_reset_ids[] = { | |
1261 | { PCI_DEVICE(0x19a2, 0x0710) }, /* Emulex, BE */ | |
1262 | { PCI_DEVICE(0x10df, 0xe220) }, /* Emulex, Lancer */ | |
b1d76a7d | 1263 | { PCI_DEVICE(0x14e4, 0x1657) }, /* Broadcom BCM5719 */ |
5cfb20b9 GS |
1264 | { 0 } |
1265 | }; | |
1266 | ||
1267 | static int eeh_pe_change_owner(struct eeh_pe *pe) | |
1268 | { | |
1269 | struct eeh_dev *edev, *tmp; | |
1270 | struct pci_dev *pdev; | |
1271 | struct pci_device_id *id; | |
1272 | int flags, ret; | |
1273 | ||
1274 | /* Check PE state */ | |
1275 | flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); | |
1276 | ret = eeh_ops->get_state(pe, NULL); | |
1277 | if (ret < 0 || ret == EEH_STATE_NOT_SUPPORT) | |
1278 | return 0; | |
1279 | ||
1280 | /* Unfrozen PE, nothing to do */ | |
1281 | if ((ret & flags) == flags) | |
1282 | return 0; | |
1283 | ||
1284 | /* Frozen PE, check if it needs PE level reset */ | |
1285 | eeh_pe_for_each_dev(pe, edev, tmp) { | |
1286 | pdev = eeh_dev_to_pci_dev(edev); | |
1287 | if (!pdev) | |
1288 | continue; | |
1289 | ||
1290 | for (id = &eeh_reset_ids[0]; id->vendor != 0; id++) { | |
1291 | if (id->vendor != PCI_ANY_ID && | |
1292 | id->vendor != pdev->vendor) | |
1293 | continue; | |
1294 | if (id->device != PCI_ANY_ID && | |
1295 | id->device != pdev->device) | |
1296 | continue; | |
1297 | if (id->subvendor != PCI_ANY_ID && | |
1298 | id->subvendor != pdev->subsystem_vendor) | |
1299 | continue; | |
1300 | if (id->subdevice != PCI_ANY_ID && | |
1301 | id->subdevice != pdev->subsystem_device) | |
1302 | continue; | |
1303 | ||
1304 | goto reset; | |
1305 | } | |
1306 | } | |
1307 | ||
1308 | return eeh_unfreeze_pe(pe, true); | |
1309 | ||
1310 | reset: | |
1311 | return eeh_pe_reset_and_recover(pe); | |
1312 | } | |
1313 | ||
212d16cd GS |
1314 | /** |
1315 | * eeh_dev_open - Increase count of pass through devices for PE | |
1316 | * @pdev: PCI device | |
1317 | * | |
1318 | * Increase count of passed through devices for the indicated | |
1319 | * PE. In the result, the EEH errors detected on the PE won't be | |
1320 | * reported. The PE owner will be responsible for detection | |
1321 | * and recovery. | |
1322 | */ | |
1323 | int eeh_dev_open(struct pci_dev *pdev) | |
1324 | { | |
1325 | struct eeh_dev *edev; | |
404079c8 | 1326 | int ret = -ENODEV; |
212d16cd GS |
1327 | |
1328 | mutex_lock(&eeh_dev_mutex); | |
1329 | ||
1330 | /* No PCI device ? */ | |
1331 | if (!pdev) | |
1332 | goto out; | |
1333 | ||
1334 | /* No EEH device or PE ? */ | |
1335 | edev = pci_dev_to_eeh_dev(pdev); | |
1336 | if (!edev || !edev->pe) | |
1337 | goto out; | |
1338 | ||
404079c8 GS |
1339 | /* |
1340 | * The PE might have been put into frozen state, but we | |
1341 | * didn't detect that yet. The passed through PCI devices | |
1342 | * in frozen PE won't work properly. Clear the frozen state | |
1343 | * in advance. | |
1344 | */ | |
5cfb20b9 | 1345 | ret = eeh_pe_change_owner(edev->pe); |
4eeeff0e GS |
1346 | if (ret) |
1347 | goto out; | |
404079c8 | 1348 | |
212d16cd GS |
1349 | /* Increase PE's pass through count */ |
1350 | atomic_inc(&edev->pe->pass_dev_cnt); | |
1351 | mutex_unlock(&eeh_dev_mutex); | |
1352 | ||
1353 | return 0; | |
1354 | out: | |
1355 | mutex_unlock(&eeh_dev_mutex); | |
404079c8 | 1356 | return ret; |
212d16cd GS |
1357 | } |
1358 | EXPORT_SYMBOL_GPL(eeh_dev_open); | |
1359 | ||
1360 | /** | |
1361 | * eeh_dev_release - Decrease count of pass through devices for PE | |
1362 | * @pdev: PCI device | |
1363 | * | |
1364 | * Decrease count of pass through devices for the indicated PE. If | |
1365 | * there is no passed through device in PE, the EEH errors detected | |
1366 | * on the PE will be reported and handled as usual. | |
1367 | */ | |
1368 | void eeh_dev_release(struct pci_dev *pdev) | |
1369 | { | |
1370 | struct eeh_dev *edev; | |
1371 | ||
1372 | mutex_lock(&eeh_dev_mutex); | |
1373 | ||
1374 | /* No PCI device ? */ | |
1375 | if (!pdev) | |
1376 | goto out; | |
1377 | ||
1378 | /* No EEH device ? */ | |
1379 | edev = pci_dev_to_eeh_dev(pdev); | |
1380 | if (!edev || !edev->pe || !eeh_pe_passed(edev->pe)) | |
1381 | goto out; | |
1382 | ||
1383 | /* Decrease PE's pass through count */ | |
1384 | atomic_dec(&edev->pe->pass_dev_cnt); | |
1385 | WARN_ON(atomic_read(&edev->pe->pass_dev_cnt) < 0); | |
5cfb20b9 | 1386 | eeh_pe_change_owner(edev->pe); |
212d16cd GS |
1387 | out: |
1388 | mutex_unlock(&eeh_dev_mutex); | |
1389 | } | |
1390 | EXPORT_SYMBOL(eeh_dev_release); | |
1391 | ||
2194dc27 BH |
1392 | #ifdef CONFIG_IOMMU_API |
1393 | ||
a3032ca9 GS |
1394 | static int dev_has_iommu_table(struct device *dev, void *data) |
1395 | { | |
1396 | struct pci_dev *pdev = to_pci_dev(dev); | |
1397 | struct pci_dev **ppdev = data; | |
1398 | struct iommu_table *tbl; | |
1399 | ||
1400 | if (!dev) | |
1401 | return 0; | |
1402 | ||
1403 | tbl = get_iommu_table_base(dev); | |
1404 | if (tbl && tbl->it_group) { | |
1405 | *ppdev = pdev; | |
1406 | return 1; | |
1407 | } | |
1408 | ||
1409 | return 0; | |
1410 | } | |
1411 | ||
212d16cd GS |
1412 | /** |
1413 | * eeh_iommu_group_to_pe - Convert IOMMU group to EEH PE | |
1414 | * @group: IOMMU group | |
1415 | * | |
1416 | * The routine is called to convert IOMMU group to EEH PE. | |
1417 | */ | |
1418 | struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group) | |
1419 | { | |
212d16cd GS |
1420 | struct pci_dev *pdev = NULL; |
1421 | struct eeh_dev *edev; | |
a3032ca9 | 1422 | int ret; |
212d16cd GS |
1423 | |
1424 | /* No IOMMU group ? */ | |
1425 | if (!group) | |
1426 | return NULL; | |
1427 | ||
a3032ca9 GS |
1428 | ret = iommu_group_for_each_dev(group, &pdev, dev_has_iommu_table); |
1429 | if (!ret || !pdev) | |
212d16cd GS |
1430 | return NULL; |
1431 | ||
1432 | /* No EEH device or PE ? */ | |
1433 | edev = pci_dev_to_eeh_dev(pdev); | |
1434 | if (!edev || !edev->pe) | |
1435 | return NULL; | |
1436 | ||
1437 | return edev->pe; | |
1438 | } | |
537e5400 | 1439 | EXPORT_SYMBOL_GPL(eeh_iommu_group_to_pe); |
212d16cd | 1440 | |
2194dc27 BH |
1441 | #endif /* CONFIG_IOMMU_API */ |
1442 | ||
212d16cd GS |
1443 | /** |
1444 | * eeh_pe_set_option - Set options for the indicated PE | |
1445 | * @pe: EEH PE | |
1446 | * @option: requested option | |
1447 | * | |
1448 | * The routine is called to enable or disable EEH functionality | |
1449 | * on the indicated PE, to enable IO or DMA for the frozen PE. | |
1450 | */ | |
1451 | int eeh_pe_set_option(struct eeh_pe *pe, int option) | |
1452 | { | |
1453 | int ret = 0; | |
1454 | ||
1455 | /* Invalid PE ? */ | |
1456 | if (!pe) | |
1457 | return -ENODEV; | |
1458 | ||
1459 | /* | |
1460 | * EEH functionality could possibly be disabled, just | |
1461 | * return error for the case. And the EEH functinality | |
1462 | * isn't expected to be disabled on one specific PE. | |
1463 | */ | |
1464 | switch (option) { | |
1465 | case EEH_OPT_ENABLE: | |
4eeeff0e | 1466 | if (eeh_enabled()) { |
5cfb20b9 | 1467 | ret = eeh_pe_change_owner(pe); |
212d16cd | 1468 | break; |
4eeeff0e | 1469 | } |
212d16cd GS |
1470 | ret = -EIO; |
1471 | break; | |
1472 | case EEH_OPT_DISABLE: | |
1473 | break; | |
1474 | case EEH_OPT_THAW_MMIO: | |
1475 | case EEH_OPT_THAW_DMA: | |
1476 | if (!eeh_ops || !eeh_ops->set_option) { | |
1477 | ret = -ENOENT; | |
1478 | break; | |
1479 | } | |
1480 | ||
4eeeff0e | 1481 | ret = eeh_pci_enable(pe, option); |
212d16cd GS |
1482 | break; |
1483 | default: | |
1484 | pr_debug("%s: Option %d out of range (%d, %d)\n", | |
1485 | __func__, option, EEH_OPT_DISABLE, EEH_OPT_THAW_DMA); | |
1486 | ret = -EINVAL; | |
1487 | } | |
1488 | ||
1489 | return ret; | |
1490 | } | |
1491 | EXPORT_SYMBOL_GPL(eeh_pe_set_option); | |
1492 | ||
1493 | /** | |
1494 | * eeh_pe_get_state - Retrieve PE's state | |
1495 | * @pe: EEH PE | |
1496 | * | |
1497 | * Retrieve the PE's state, which includes 3 aspects: enabled | |
1498 | * DMA, enabled IO and asserted reset. | |
1499 | */ | |
1500 | int eeh_pe_get_state(struct eeh_pe *pe) | |
1501 | { | |
1502 | int result, ret = 0; | |
1503 | bool rst_active, dma_en, mmio_en; | |
1504 | ||
1505 | /* Existing PE ? */ | |
1506 | if (!pe) | |
1507 | return -ENODEV; | |
1508 | ||
1509 | if (!eeh_ops || !eeh_ops->get_state) | |
1510 | return -ENOENT; | |
1511 | ||
1512 | result = eeh_ops->get_state(pe, NULL); | |
1513 | rst_active = !!(result & EEH_STATE_RESET_ACTIVE); | |
1514 | dma_en = !!(result & EEH_STATE_DMA_ENABLED); | |
1515 | mmio_en = !!(result & EEH_STATE_MMIO_ENABLED); | |
1516 | ||
1517 | if (rst_active) | |
1518 | ret = EEH_PE_STATE_RESET; | |
1519 | else if (dma_en && mmio_en) | |
1520 | ret = EEH_PE_STATE_NORMAL; | |
1521 | else if (!dma_en && !mmio_en) | |
1522 | ret = EEH_PE_STATE_STOPPED_IO_DMA; | |
1523 | else if (!dma_en && mmio_en) | |
1524 | ret = EEH_PE_STATE_STOPPED_DMA; | |
1525 | else | |
1526 | ret = EEH_PE_STATE_UNAVAIL; | |
1527 | ||
1528 | return ret; | |
1529 | } | |
1530 | EXPORT_SYMBOL_GPL(eeh_pe_get_state); | |
1531 | ||
316233ff GS |
1532 | static int eeh_pe_reenable_devices(struct eeh_pe *pe) |
1533 | { | |
1534 | struct eeh_dev *edev, *tmp; | |
1535 | struct pci_dev *pdev; | |
1536 | int ret = 0; | |
1537 | ||
1538 | /* Restore config space */ | |
1539 | eeh_pe_restore_bars(pe); | |
1540 | ||
1541 | /* | |
1542 | * Reenable PCI devices as the devices passed | |
1543 | * through are always enabled before the reset. | |
1544 | */ | |
1545 | eeh_pe_for_each_dev(pe, edev, tmp) { | |
1546 | pdev = eeh_dev_to_pci_dev(edev); | |
1547 | if (!pdev) | |
1548 | continue; | |
1549 | ||
1550 | ret = pci_reenable_device(pdev); | |
1551 | if (ret) { | |
1552 | pr_warn("%s: Failure %d reenabling %s\n", | |
1553 | __func__, ret, pci_name(pdev)); | |
1554 | return ret; | |
1555 | } | |
1556 | } | |
1557 | ||
1558 | /* The PE is still in frozen state */ | |
c9dd0143 | 1559 | return eeh_unfreeze_pe(pe, true); |
316233ff GS |
1560 | } |
1561 | ||
212d16cd GS |
1562 | /** |
1563 | * eeh_pe_reset - Issue PE reset according to specified type | |
1564 | * @pe: EEH PE | |
1565 | * @option: reset type | |
1566 | * | |
1567 | * The routine is called to reset the specified PE with the | |
1568 | * indicated type, either fundamental reset or hot reset. | |
1569 | * PE reset is the most important part for error recovery. | |
1570 | */ | |
1571 | int eeh_pe_reset(struct eeh_pe *pe, int option) | |
1572 | { | |
1573 | int ret = 0; | |
1574 | ||
1575 | /* Invalid PE ? */ | |
1576 | if (!pe) | |
1577 | return -ENODEV; | |
1578 | ||
1579 | if (!eeh_ops || !eeh_ops->set_option || !eeh_ops->reset) | |
1580 | return -ENOENT; | |
1581 | ||
1582 | switch (option) { | |
1583 | case EEH_RESET_DEACTIVATE: | |
1584 | ret = eeh_ops->reset(pe, option); | |
8a6b3710 | 1585 | eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED); |
212d16cd GS |
1586 | if (ret) |
1587 | break; | |
1588 | ||
316233ff | 1589 | ret = eeh_pe_reenable_devices(pe); |
212d16cd GS |
1590 | break; |
1591 | case EEH_RESET_HOT: | |
1592 | case EEH_RESET_FUNDAMENTAL: | |
0d5ee520 GS |
1593 | /* |
1594 | * Proactively freeze the PE to drop all MMIO access | |
1595 | * during reset, which should be banned as it's always | |
1596 | * cause recursive EEH error. | |
1597 | */ | |
1598 | eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE); | |
1599 | ||
8a6b3710 | 1600 | eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED); |
212d16cd GS |
1601 | ret = eeh_ops->reset(pe, option); |
1602 | break; | |
1603 | default: | |
1604 | pr_debug("%s: Unsupported option %d\n", | |
1605 | __func__, option); | |
1606 | ret = -EINVAL; | |
1607 | } | |
1608 | ||
1609 | return ret; | |
1610 | } | |
1611 | EXPORT_SYMBOL_GPL(eeh_pe_reset); | |
1612 | ||
1613 | /** | |
1614 | * eeh_pe_configure - Configure PCI bridges after PE reset | |
1615 | * @pe: EEH PE | |
1616 | * | |
1617 | * The routine is called to restore the PCI config space for | |
1618 | * those PCI devices, especially PCI bridges affected by PE | |
1619 | * reset issued previously. | |
1620 | */ | |
1621 | int eeh_pe_configure(struct eeh_pe *pe) | |
1622 | { | |
1623 | int ret = 0; | |
1624 | ||
1625 | /* Invalid PE ? */ | |
1626 | if (!pe) | |
1627 | return -ENODEV; | |
1628 | ||
212d16cd GS |
1629 | return ret; |
1630 | } | |
1631 | EXPORT_SYMBOL_GPL(eeh_pe_configure); | |
1632 | ||
1da177e4 LT |
1633 | static int proc_eeh_show(struct seq_file *m, void *v) |
1634 | { | |
2ec5a0ad | 1635 | if (!eeh_enabled()) { |
1da177e4 | 1636 | seq_printf(m, "EEH Subsystem is globally disabled\n"); |
e575f8db | 1637 | seq_printf(m, "eeh_total_mmio_ffs=%llu\n", eeh_stats.total_mmio_ffs); |
1da177e4 LT |
1638 | } else { |
1639 | seq_printf(m, "EEH Subsystem is enabled\n"); | |
177bc936 | 1640 | seq_printf(m, |
e575f8db GS |
1641 | "no device=%llu\n" |
1642 | "no device node=%llu\n" | |
1643 | "no config address=%llu\n" | |
1644 | "check not wanted=%llu\n" | |
1645 | "eeh_total_mmio_ffs=%llu\n" | |
1646 | "eeh_false_positives=%llu\n" | |
1647 | "eeh_slot_resets=%llu\n", | |
1648 | eeh_stats.no_device, | |
1649 | eeh_stats.no_dn, | |
1650 | eeh_stats.no_cfg_addr, | |
1651 | eeh_stats.ignored_check, | |
1652 | eeh_stats.total_mmio_ffs, | |
1653 | eeh_stats.false_positives, | |
1654 | eeh_stats.slot_resets); | |
1da177e4 LT |
1655 | } |
1656 | ||
1657 | return 0; | |
1658 | } | |
1659 | ||
1660 | static int proc_eeh_open(struct inode *inode, struct file *file) | |
1661 | { | |
1662 | return single_open(file, proc_eeh_show, NULL); | |
1663 | } | |
1664 | ||
5dfe4c96 | 1665 | static const struct file_operations proc_eeh_operations = { |
1da177e4 LT |
1666 | .open = proc_eeh_open, |
1667 | .read = seq_read, | |
1668 | .llseek = seq_lseek, | |
1669 | .release = single_release, | |
1670 | }; | |
1671 | ||
7f52a526 GS |
1672 | #ifdef CONFIG_DEBUG_FS |
1673 | static int eeh_enable_dbgfs_set(void *data, u64 val) | |
1674 | { | |
1675 | if (val) | |
05b1721d | 1676 | eeh_clear_flag(EEH_FORCE_DISABLED); |
7f52a526 | 1677 | else |
05b1721d | 1678 | eeh_add_flag(EEH_FORCE_DISABLED); |
7f52a526 GS |
1679 | |
1680 | /* Notify the backend */ | |
1681 | if (eeh_ops->post_init) | |
1682 | eeh_ops->post_init(); | |
1683 | ||
1684 | return 0; | |
1685 | } | |
1686 | ||
1687 | static int eeh_enable_dbgfs_get(void *data, u64 *val) | |
1688 | { | |
1689 | if (eeh_enabled()) | |
1690 | *val = 0x1ul; | |
1691 | else | |
1692 | *val = 0x0ul; | |
1693 | return 0; | |
1694 | } | |
1695 | ||
1b28f170 GS |
1696 | static int eeh_freeze_dbgfs_set(void *data, u64 val) |
1697 | { | |
1698 | eeh_max_freezes = val; | |
1699 | return 0; | |
1700 | } | |
1701 | ||
1702 | static int eeh_freeze_dbgfs_get(void *data, u64 *val) | |
1703 | { | |
1704 | *val = eeh_max_freezes; | |
1705 | return 0; | |
1706 | } | |
1707 | ||
7f52a526 GS |
1708 | DEFINE_SIMPLE_ATTRIBUTE(eeh_enable_dbgfs_ops, eeh_enable_dbgfs_get, |
1709 | eeh_enable_dbgfs_set, "0x%llx\n"); | |
1b28f170 GS |
1710 | DEFINE_SIMPLE_ATTRIBUTE(eeh_freeze_dbgfs_ops, eeh_freeze_dbgfs_get, |
1711 | eeh_freeze_dbgfs_set, "0x%llx\n"); | |
7f52a526 GS |
1712 | #endif |
1713 | ||
1da177e4 LT |
1714 | static int __init eeh_init_proc(void) |
1715 | { | |
7f52a526 | 1716 | if (machine_is(pseries) || machine_is(powernv)) { |
8feaa434 | 1717 | proc_create("powerpc/eeh", 0, NULL, &proc_eeh_operations); |
7f52a526 GS |
1718 | #ifdef CONFIG_DEBUG_FS |
1719 | debugfs_create_file("eeh_enable", 0600, | |
1720 | powerpc_debugfs_root, NULL, | |
1721 | &eeh_enable_dbgfs_ops); | |
1b28f170 GS |
1722 | debugfs_create_file("eeh_max_freezes", 0600, |
1723 | powerpc_debugfs_root, NULL, | |
1724 | &eeh_freeze_dbgfs_ops); | |
7f52a526 GS |
1725 | #endif |
1726 | } | |
1727 | ||
1da177e4 LT |
1728 | return 0; |
1729 | } | |
1730 | __initcall(eeh_init_proc); |