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24cc67de BH |
1 | /* |
2 | * This file contains low level CPU setup functions. | |
3 | * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org) | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version | |
8 | * 2 of the License, or (at your option) any later version. | |
9 | * | |
10 | */ | |
11 | ||
12 | #include <asm/processor.h> | |
13 | #include <asm/page.h> | |
14 | #include <asm/cputable.h> | |
15 | #include <asm/ppc_asm.h> | |
16 | #include <asm/asm-offsets.h> | |
17 | #include <asm/cache.h> | |
18 | ||
19 | /* Entry: r3 = crap, r4 = ptr to cputable entry | |
20 | * | |
21 | * Note that we can be called twice for pseudo-PVRs | |
22 | */ | |
23 | _GLOBAL(__setup_cpu_power7) | |
24 | mflr r11 | |
25 | bl __init_hvmode_206 | |
26 | mtlr r11 | |
27 | beqlr | |
b144871c BH |
28 | li r0,0 |
29 | mtspr SPRN_LPID,r0 | |
24cc67de | 30 | bl __init_LPCR |
b144871c | 31 | bl __init_TLB |
24cc67de BH |
32 | mtlr r11 |
33 | blr | |
34 | ||
35 | _GLOBAL(__restore_cpu_power7) | |
36 | mflr r11 | |
37 | mfmsr r3 | |
38 | rldicl. r0,r3,4,63 | |
39 | beqlr | |
b144871c BH |
40 | li r0,0 |
41 | mtspr SPRN_LPID,r0 | |
24cc67de | 42 | bl __init_LPCR |
b144871c | 43 | bl __init_TLB |
24cc67de BH |
44 | mtlr r11 |
45 | blr | |
46 | ||
47 | __init_hvmode_206: | |
48 | /* Disable CPU_FTR_HVMODE_206 and exit if MSR:HV is not set */ | |
49 | mfmsr r3 | |
50 | rldicl. r0,r3,4,63 | |
51 | bnelr | |
52 | ld r5,CPU_SPEC_FEATURES(r4) | |
53 | LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE_206) | |
54 | xor r5,r5,r6 | |
55 | std r5,CPU_SPEC_FEATURES(r4) | |
56 | blr | |
57 | ||
58 | __init_LPCR: | |
59 | /* Setup a sane LPCR: | |
60 | * | |
a5d4f3ad | 61 | * LPES = 0b01 (HSRR0/1 used for 0x500) |
24cc67de | 62 | * PECE = 0b111 |
895796a8 | 63 | * DPFD = 4 |
24cc67de BH |
64 | * |
65 | * Other bits untouched for now | |
66 | */ | |
67 | mfspr r3,SPRN_LPCR | |
68 | ori r3,r3,(LPCR_LPES0|LPCR_LPES1) | |
a5d4f3ad | 69 | xori r3,r3, LPCR_LPES0 |
24cc67de | 70 | ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2) |
895796a8 BH |
71 | li r5,7 |
72 | sldi r5,r5,LPCR_DPFD_SH | |
73 | andc r3,r3,r5 | |
74 | li r5,4 | |
75 | sldi r5,r5,LPCR_DPFD_SH | |
76 | or r3,r3,r5 | |
24cc67de BH |
77 | mtspr SPRN_LPCR,r3 |
78 | isync | |
79 | blr | |
b144871c BH |
80 | |
81 | __init_TLB: | |
82 | /* Clear the TLB */ | |
83 | li r6,128 | |
84 | mtctr r6 | |
85 | li r7,0xc00 /* IS field = 0b11 */ | |
86 | ptesync | |
87 | 2: tlbiel r7 | |
88 | addi r7,r7,0x1000 | |
89 | bdnz 2b | |
90 | ptesync | |
91 | 1: blr |