[linux-2.6-block.git] / arch / powerpc / kernel / cpu_setup_power.S

/*
 * This file contains low level CPU setup functions.
 *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 *
 */

#include <asm/processor.h>
#include <asm/page.h>
#include <asm/cputable.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/cache.h>
#include <asm/book3s/64/mmu-hash.h>

/* Entry: r3 = crap, r4 = ptr to cputable entry
 *
 * Note that we can be called twice for pseudo-PVRs
 */
_GLOBAL(__setup_cpu_power7)
	mflr	r11
	bl	__init_hvmode_206
	mtlr	r11
	beqlr
	li	r0,0
	mtspr	SPRN_LPID,r0
	mfspr	r3,SPRN_LPCR
	li	r4,(LPCR_LPES1 >> LPCR_LPES_SH)
	bl	__init_LPCR_ISA206
	mtlr	r11
	blr

_GLOBAL(__restore_cpu_power7)
	mflr	r11
	mfmsr	r3
	rldicl.	r0,r3,4,63
	beqlr
	li	r0,0
	mtspr	SPRN_LPID,r0
	mfspr	r3,SPRN_LPCR
	li	r4,(LPCR_LPES1 >> LPCR_LPES_SH)
	bl	__init_LPCR_ISA206
	mtlr	r11
	blr

_GLOBAL(__setup_cpu_power8)
	mflr	r11
	bl	__init_FSCR
	bl	__init_PMU
	bl	__init_PMU_ISA207
	bl	__init_hvmode_206
	mtlr	r11
	beqlr
	li	r0,0
	mtspr	SPRN_LPID,r0
	mfspr	r3,SPRN_LPCR
	ori	r3, r3, LPCR_PECEDH
	li	r4,0 /* LPES = 0 */
	bl	__init_LPCR_ISA206
	bl	__init_HFSCR
	bl	__init_PMU_HV
	bl	__init_PMU_HV_ISA207
	mtlr	r11
	blr

_GLOBAL(__restore_cpu_power8)
	mflr	r11
	bl	__init_FSCR
	bl	__init_PMU
	bl	__init_PMU_ISA207
	mfmsr	r3
	rldicl.	r0,r3,4,63
	mtlr	r11
	beqlr
	li	r0,0
	mtspr	SPRN_LPID,r0
	mfspr   r3,SPRN_LPCR
	ori	r3, r3, LPCR_PECEDH
	li	r4,0 /* LPES = 0 */
	bl	__init_LPCR_ISA206
	bl	__init_HFSCR
	bl	__init_PMU_HV
	bl	__init_PMU_HV_ISA207
	mtlr	r11
	blr

_GLOBAL(__setup_cpu_power9)
	mflr	r11
	bl	__init_FSCR
	bl	__init_PMU
	bl	__init_hvmode_206
	mtlr	r11
	beqlr
	li	r0,0
	mtspr	SPRN_PSSCR,r0
	mtspr	SPRN_LPID,r0
	mtspr	SPRN_PID,r0
	mfspr	r3,SPRN_LPCR
	LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE  | LPCR_HEIC)
	or	r3, r3, r4
	LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
	andc	r3, r3, r4
	li	r4,0 /* LPES = 0 */
	bl	__init_LPCR_ISA300
	bl	__init_HFSCR
	bl	__init_PMU_HV
	mtlr	r11
	blr

_GLOBAL(__restore_cpu_power9)
	mflr	r11
	bl	__init_FSCR
	bl	__init_PMU
	mfmsr	r3
	rldicl.	r0,r3,4,63
	mtlr	r11
	beqlr
	li	r0,0
	mtspr	SPRN_PSSCR,r0
	mtspr	SPRN_LPID,r0
	mtspr	SPRN_PID,r0
	mfspr   r3,SPRN_LPCR
	LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE | LPCR_HEIC)
	or	r3, r3, r4
	LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
	andc	r3, r3, r4
	li	r4,0 /* LPES = 0 */
	bl	__init_LPCR_ISA300
	bl	__init_HFSCR
	bl	__init_PMU_HV
	mtlr	r11
	blr

__init_hvmode_206:
	/* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
	mfmsr	r3
	rldicl.	r0,r3,4,63
	bnelr
	ld	r5,CPU_SPEC_FEATURES(r4)
	LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
	xor	r5,r5,r6
	std	r5,CPU_SPEC_FEATURES(r4)
	blr

__init_LPCR_ISA206:
	/* Setup a sane LPCR:
	 *   Called with initial LPCR in R3 and desired LPES 2-bit value in R4
	 *
	 *   LPES = 0b01 (HSRR0/1 used for 0x500)
	 *   PECE = 0b111
	 *   DPFD = 4
	 *   HDICE = 0
	 *   VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
	 *   VRMASD = 0b10000 (L=1, LP=00)
	 *
	 * Other bits untouched for now
	 */
	li	r5,0x10
	rldimi	r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5

	/* POWER9 has no VRMASD */
__init_LPCR_ISA300:
	rldimi	r3,r4, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
	ori	r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
	li	r5,4
	rldimi	r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
	clrrdi	r3,r3,1		/* clear HDICE */
	li	r5,4
	rldimi	r3,r5, LPCR_VC_SH, 0
	mtspr	SPRN_LPCR,r3
	isync
	blr

__init_FSCR:
	mfspr	r3,SPRN_FSCR
	ori	r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB
	mtspr	SPRN_FSCR,r3
	blr

__init_HFSCR:
	mfspr	r3,SPRN_HFSCR
	ori	r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\
		      HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB|HFSCR_MSGP
	mtspr	SPRN_HFSCR,r3
	blr

__init_PMU_HV:
	li	r5,0
	mtspr	SPRN_MMCRC,r5
	blr

__init_PMU_HV_ISA207:
	li	r5,0
	mtspr	SPRN_MMCRH,r5
	blr

__init_PMU:
	li	r5,0
	mtspr	SPRN_MMCRA,r5
	mtspr	SPRN_MMCR0,r5
	mtspr	SPRN_MMCR1,r5
	mtspr	SPRN_MMCR2,r5
	blr

__init_PMU_ISA207:
	li	r5,0
	mtspr	SPRN_MMCRS,r5
	blr
Commit	Line	Data
24cc67de BH	1	/*
	2	* This file contains low level CPU setup functions.
	3	* Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version
	8	* 2 of the License, or (at your option) any later version.
	9	*
	10	*/
	11
	12	#include <asm/processor.h>
	13	#include <asm/page.h>
	14	#include <asm/cputable.h>
	15	#include <asm/ppc_asm.h>
	16	#include <asm/asm-offsets.h>
	17	#include <asm/cache.h>
f64e8084	18	#include <asm/book3s/64/mmu-hash.h>
24cc67de BH	19
	20	/* Entry: r3 = crap, r4 = ptr to cputable entry
	21	*
	22	* Note that we can be called twice for pseudo-PVRs
	23	*/
	24	_GLOBAL(__setup_cpu_power7)
	25	mflr r11
	26	bl __init_hvmode_206
	27	mtlr r11
	28	beqlr
b144871c BH	29	li r0,0
b144871c BH	30	mtspr SPRN_LPID,r0
f7c32c24	31	mfspr r3,SPRN_LPCR
08a1e650	32	li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
700b7ead	33	bl __init_LPCR_ISA206
24cc67de BH	34	mtlr r11
	35	blr
	36
	37	_GLOBAL(__restore_cpu_power7)
	38	mflr r11
	39	mfmsr r3
	40	rldicl. r0,r3,4,63
	41	beqlr
b144871c BH	42	li r0,0
b144871c BH	43	mtspr SPRN_LPID,r0
f7c32c24	44	mfspr r3,SPRN_LPCR
08a1e650	45	li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
700b7ead	46	bl __init_LPCR_ISA206
aec937b1 MN	47	mtlr r11
	48	blr
	49
	50	_GLOBAL(__setup_cpu_power8)
	51	mflr r11
57d23167	52	bl __init_FSCR
240686c1	53	bl __init_PMU
393eb79a	54	bl __init_PMU_ISA207
aec937b1 MN	55	bl __init_hvmode_206
	56	mtlr r11
	57	beqlr
	58	li r0,0
	59	mtspr SPRN_LPID,r0
f7c32c24	60	mfspr r3,SPRN_LPCR
d4e58e59	61	ori r3, r3, LPCR_PECEDH
08a1e650	62	li r4,0 /* LPES = 0 */
700b7ead	63	bl __init_LPCR_ISA206
2a3563b0	64	bl __init_HFSCR
240686c1	65	bl __init_PMU_HV
393eb79a	66	bl __init_PMU_HV_ISA207
aec937b1 MN	67	mtlr r11
	68	blr
	69
	70	_GLOBAL(__restore_cpu_power8)
	71	mflr r11
57d23167	72	bl __init_FSCR
240686c1	73	bl __init_PMU
393eb79a	74	bl __init_PMU_ISA207
aec937b1 MN	75	mfmsr r3
aec937b1 MN	76	rldicl. r0,r3,4,63
8c2a3817	77	mtlr r11
aec937b1 MN	78	beqlr
	79	li r0,0
	80	mtspr SPRN_LPID,r0
f7c32c24	81	mfspr r3,SPRN_LPCR
d4e58e59	82	ori r3, r3, LPCR_PECEDH
08a1e650	83	li r4,0 /* LPES = 0 */
700b7ead	84	bl __init_LPCR_ISA206
2a3563b0	85	bl __init_HFSCR
240686c1	86	bl __init_PMU_HV
393eb79a	87	bl __init_PMU_HV_ISA207
24cc67de BH	88	mtlr r11
	89	blr
	90
c3ab300e MN	91	_GLOBAL(__setup_cpu_power9)
	92	mflr r11
	93	bl __init_FSCR
393eb79a	94	bl __init_PMU
c3ab300e MN	95	bl __init_hvmode_206
	96	mtlr r11
	97	beqlr
	98	li r0,0
378f96d3	99	mtspr SPRN_PSSCR,r0
c3ab300e	100	mtspr SPRN_LPID,r0
371b8044	101	mtspr SPRN_PID,r0
c3ab300e	102	mfspr r3,SPRN_LPCR
08a1e650	103	LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH \| LPCR_PECE_HVEE \| LPCR_HVICE \| LPCR_HEIC)
7a43906f	104	or r3, r3, r4
fda2d27d AK	105	LOAD_REG_IMMEDIATE(r4, LPCR_UPRT \| LPCR_HR)
fda2d27d AK	106	andc r3, r3, r4
8d1b48ef	107	li r4,0 /* LPES = 0 */
700b7ead	108	bl __init_LPCR_ISA300
c3ab300e	109	bl __init_HFSCR
393eb79a	110	bl __init_PMU_HV
c3ab300e MN	111	mtlr r11
	112	blr
	113
	114	_GLOBAL(__restore_cpu_power9)
	115	mflr r11
	116	bl __init_FSCR
393eb79a	117	bl __init_PMU
c3ab300e MN	118	mfmsr r3
	119	rldicl. r0,r3,4,63
	120	mtlr r11
	121	beqlr
	122	li r0,0
378f96d3	123	mtspr SPRN_PSSCR,r0
c3ab300e	124	mtspr SPRN_LPID,r0
371b8044	125	mtspr SPRN_PID,r0
c3ab300e	126	mfspr r3,SPRN_LPCR
08a1e650	127	LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH \| LPCR_PECE_HVEE \| LPCR_HVICE \| LPCR_HEIC)
7a43906f	128	or r3, r3, r4
fda2d27d AK	129	LOAD_REG_IMMEDIATE(r4, LPCR_UPRT \| LPCR_HR)
fda2d27d AK	130	andc r3, r3, r4
8d1b48ef	131	li r4,0 /* LPES = 0 */
700b7ead	132	bl __init_LPCR_ISA300
c3ab300e	133	bl __init_HFSCR
393eb79a	134	bl __init_PMU_HV
c3ab300e MN	135	mtlr r11
	136	blr
	137
24cc67de	138	__init_hvmode_206:
969391c5	139	/* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
24cc67de BH	140	mfmsr r3
	141	rldicl. r0,r3,4,63
	142	bnelr
	143	ld r5,CPU_SPEC_FEATURES(r4)
969391c5	144	LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
24cc67de BH	145	xor r5,r5,r6
	146	std r5,CPU_SPEC_FEATURES(r4)
	147	blr
	148
700b7ead	149	__init_LPCR_ISA206:
24cc67de	150	/* Setup a sane LPCR:
08a1e650	151	* Called with initial LPCR in R3 and desired LPES 2-bit value in R4
24cc67de	152	*
a5d4f3ad	153	* LPES = 0b01 (HSRR0/1 used for 0x500)
24cc67de	154	* PECE = 0b111
895796a8	155	* DPFD = 4
923c53ca PM	156	* HDICE = 0
	157	* VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
	158	* VRMASD = 0b10000 (L=1, LP=00)
24cc67de BH	159	*
	160	* Other bits untouched for now
	161	*/
700b7ead NP	162	li r5,0x10
	163	rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
	164
	165	/* POWER9 has no VRMASD */
	166	__init_LPCR_ISA300:
08a1e650	167	rldimi r3,r4, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
24cc67de	168	ori r3,r3,(LPCR_PECE0\|LPCR_PECE1\|LPCR_PECE2)
895796a8	169	li r5,4
923c53ca PM	170	rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
	171	clrrdi r3,r3,1 /* clear HDICE */
	172	li r5,4
	173	rldimi r3,r5, LPCR_VC_SH, 0
24cc67de BH	174	mtspr SPRN_LPCR,r3
	175	isync
	176	blr
b144871c	177
2468dcf6 IM	178	__init_FSCR:
2468dcf6 IM	179	mfspr r3,SPRN_FSCR
1ddf499e	180	ori r3,r3,FSCR_TAR\|FSCR_DSCR\|FSCR_EBB
2468dcf6 IM	181	mtspr SPRN_FSCR,r3
	182	blr
	183
2a3563b0 MN	184	__init_HFSCR:
2a3563b0 MN	185	mfspr r3,SPRN_HFSCR
53b56ca0	186	ori r3,r3,HFSCR_TAR\|HFSCR_TM\|HFSCR_BHRB\|HFSCR_PM\|\
02ed21ae	187	HFSCR_DSCR\|HFSCR_VECVSX\|HFSCR_FP\|HFSCR_EBB\|HFSCR_MSGP
2a3563b0 MN	188	mtspr SPRN_HFSCR,r3
	189	blr
	190
240686c1 ME	191	__init_PMU_HV:
	192	li r5,0
	193	mtspr SPRN_MMCRC,r5
393eb79a MS	194	blr
	195
	196	__init_PMU_HV_ISA207:
	197	li r5,0
240686c1 ME	198	mtspr SPRN_MMCRH,r5
	199	blr
	200
	201	__init_PMU:
	202	li r5,0
240686c1 ME	203	mtspr SPRN_MMCRA,r5
	204	mtspr SPRN_MMCR0,r5
	205	mtspr SPRN_MMCR1,r5
	206	mtspr SPRN_MMCR2,r5
	207	blr
393eb79a MS	208
	209	__init_PMU_ISA207:
	210	li r5,0
	211	mtspr SPRN_MMCRS,r5
	212	blr