[linux-2.6-block.git] / arch / powerpc / kernel / cpu_setup_power.S

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * This file contains low level CPU setup functions.
 *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
 */

#include <asm/processor.h>
#include <asm/page.h>
#include <asm/cputable.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/cache.h>
#include <asm/book3s/64/mmu-hash.h>

/* Entry: r3 = crap, r4 = ptr to cputable entry
 *
 * Note that we can be called twice for pseudo-PVRs
 */
_GLOBAL(__setup_cpu_power7)
	mflr	r11
	bl	__init_hvmode_206
	mtlr	r11
	beqlr
	li	r0,0
	mtspr	SPRN_LPID,r0
	LOAD_REG_IMMEDIATE(r0, PCR_MASK)
	mtspr	SPRN_PCR,r0
	mfspr	r3,SPRN_LPCR
	li	r4,(LPCR_LPES1 >> LPCR_LPES_SH)
	bl	__init_LPCR_ISA206
	mtlr	r11
	blr

_GLOBAL(__restore_cpu_power7)
	mflr	r11
	mfmsr	r3
	rldicl.	r0,r3,4,63
	beqlr
	li	r0,0
	mtspr	SPRN_LPID,r0
	LOAD_REG_IMMEDIATE(r0, PCR_MASK)
	mtspr	SPRN_PCR,r0
	mfspr	r3,SPRN_LPCR
	li	r4,(LPCR_LPES1 >> LPCR_LPES_SH)
	bl	__init_LPCR_ISA206
	mtlr	r11
	blr

_GLOBAL(__setup_cpu_power8)
	mflr	r11
	bl	__init_FSCR
	bl	__init_PMU
	bl	__init_PMU_ISA207
	bl	__init_hvmode_206
	mtlr	r11
	beqlr
	li	r0,0
	mtspr	SPRN_LPID,r0
	LOAD_REG_IMMEDIATE(r0, PCR_MASK)
	mtspr	SPRN_PCR,r0
	mfspr	r3,SPRN_LPCR
	ori	r3, r3, LPCR_PECEDH
	li	r4,0 /* LPES = 0 */
	bl	__init_LPCR_ISA206
	bl	__init_HFSCR
	bl	__init_PMU_HV
	bl	__init_PMU_HV_ISA207
	mtlr	r11
	blr

_GLOBAL(__restore_cpu_power8)
	mflr	r11
	bl	__init_FSCR
	bl	__init_PMU
	bl	__init_PMU_ISA207
	mfmsr	r3
	rldicl.	r0,r3,4,63
	mtlr	r11
	beqlr
	li	r0,0
	mtspr	SPRN_LPID,r0
	LOAD_REG_IMMEDIATE(r0, PCR_MASK)
	mtspr	SPRN_PCR,r0
	mfspr   r3,SPRN_LPCR
	ori	r3, r3, LPCR_PECEDH
	li	r4,0 /* LPES = 0 */
	bl	__init_LPCR_ISA206
	bl	__init_HFSCR
	bl	__init_PMU_HV
	bl	__init_PMU_HV_ISA207
	mtlr	r11
	blr

_GLOBAL(__setup_cpu_power9)
	mflr	r11
	bl	__init_FSCR
	bl	__init_PMU
	bl	__init_hvmode_206
	mtlr	r11
	beqlr
	li	r0,0
	mtspr	SPRN_PSSCR,r0
	mtspr	SPRN_LPID,r0
	mtspr	SPRN_PID,r0
	LOAD_REG_IMMEDIATE(r0, PCR_MASK)
	mtspr	SPRN_PCR,r0
	mfspr	r3,SPRN_LPCR
	LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE  | LPCR_HEIC)
	or	r3, r3, r4
	LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
	andc	r3, r3, r4
	li	r4,0 /* LPES = 0 */
	bl	__init_LPCR_ISA300
	bl	__init_HFSCR
	bl	__init_PMU_HV
	mtlr	r11
	blr

_GLOBAL(__restore_cpu_power9)
	mflr	r11
	bl	__init_FSCR
	bl	__init_PMU
	mfmsr	r3
	rldicl.	r0,r3,4,63
	mtlr	r11
	beqlr
	li	r0,0
	mtspr	SPRN_PSSCR,r0
	mtspr	SPRN_LPID,r0
	mtspr	SPRN_PID,r0
	LOAD_REG_IMMEDIATE(r0, PCR_MASK)
	mtspr	SPRN_PCR,r0
	mfspr   r3,SPRN_LPCR
	LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE | LPCR_HEIC)
	or	r3, r3, r4
	LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
	andc	r3, r3, r4
	li	r4,0 /* LPES = 0 */
	bl	__init_LPCR_ISA300
	bl	__init_HFSCR
	bl	__init_PMU_HV
	mtlr	r11
	blr

__init_hvmode_206:
	/* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
	mfmsr	r3
	rldicl.	r0,r3,4,63
	bnelr
	ld	r5,CPU_SPEC_FEATURES(r4)
	LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE | CPU_FTR_P9_TM_HV_ASSIST)
	andc	r5,r5,r6
	std	r5,CPU_SPEC_FEATURES(r4)
	blr

__init_LPCR_ISA206:
	/* Setup a sane LPCR:
	 *   Called with initial LPCR in R3 and desired LPES 2-bit value in R4
	 *
	 *   LPES = 0b01 (HSRR0/1 used for 0x500)
	 *   PECE = 0b111
	 *   DPFD = 4
	 *   HDICE = 0
	 *   VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
	 *   VRMASD = 0b10000 (L=1, LP=00)
	 *
	 * Other bits untouched for now
	 */
	li	r5,0x10
	rldimi	r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5

	/* POWER9 has no VRMASD */
__init_LPCR_ISA300:
	rldimi	r3,r4, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
	ori	r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
	li	r5,4
	rldimi	r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
	clrrdi	r3,r3,1		/* clear HDICE */
	li	r5,4
	rldimi	r3,r5, LPCR_VC_SH, 0
	mtspr	SPRN_LPCR,r3
	isync
	blr

__init_FSCR:
	mfspr	r3,SPRN_FSCR
	ori	r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB
	mtspr	SPRN_FSCR,r3
	blr

__init_HFSCR:
	mfspr	r3,SPRN_HFSCR
	ori	r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\
		      HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB|HFSCR_MSGP
	mtspr	SPRN_HFSCR,r3
	blr

__init_PMU_HV:
	li	r5,0
	mtspr	SPRN_MMCRC,r5
	blr

__init_PMU_HV_ISA207:
	li	r5,0
	mtspr	SPRN_MMCRH,r5
	blr

__init_PMU:
	li	r5,0
	mtspr	SPRN_MMCRA,r5
	mtspr	SPRN_MMCR0,r5
	mtspr	SPRN_MMCR1,r5
	mtspr	SPRN_MMCR2,r5
	blr

__init_PMU_ISA207:
	li	r5,0
	mtspr	SPRN_MMCRS,r5
	blr
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
24cc67de BH	2	/*
	3	* This file contains low level CPU setup functions.
	4	* Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
24cc67de BH	5	*/
	6
	7	#include <asm/processor.h>
	8	#include <asm/page.h>
	9	#include <asm/cputable.h>
	10	#include <asm/ppc_asm.h>
	11	#include <asm/asm-offsets.h>
	12	#include <asm/cache.h>
f64e8084	13	#include <asm/book3s/64/mmu-hash.h>
24cc67de BH	14
	15	/* Entry: r3 = crap, r4 = ptr to cputable entry
	16	*
	17	* Note that we can be called twice for pseudo-PVRs
	18	*/
	19	_GLOBAL(__setup_cpu_power7)
	20	mflr r11
	21	bl __init_hvmode_206
	22	mtlr r11
	23	beqlr
b144871c BH	24	li r0,0
b144871c BH	25	mtspr SPRN_LPID,r0
13c7bb3c	26	LOAD_REG_IMMEDIATE(r0, PCR_MASK)
faf37c44	27	mtspr SPRN_PCR,r0
f7c32c24	28	mfspr r3,SPRN_LPCR
08a1e650	29	li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
700b7ead	30	bl __init_LPCR_ISA206
24cc67de BH	31	mtlr r11
	32	blr
	33
	34	_GLOBAL(__restore_cpu_power7)
	35	mflr r11
	36	mfmsr r3
	37	rldicl. r0,r3,4,63
	38	beqlr
b144871c BH	39	li r0,0
b144871c BH	40	mtspr SPRN_LPID,r0
13c7bb3c	41	LOAD_REG_IMMEDIATE(r0, PCR_MASK)
faf37c44	42	mtspr SPRN_PCR,r0
f7c32c24	43	mfspr r3,SPRN_LPCR
08a1e650	44	li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
700b7ead	45	bl __init_LPCR_ISA206
aec937b1 MN	46	mtlr r11
	47	blr
	48
	49	_GLOBAL(__setup_cpu_power8)
	50	mflr r11
57d23167	51	bl __init_FSCR
240686c1	52	bl __init_PMU
393eb79a	53	bl __init_PMU_ISA207
aec937b1 MN	54	bl __init_hvmode_206
	55	mtlr r11
	56	beqlr
	57	li r0,0
	58	mtspr SPRN_LPID,r0
13c7bb3c	59	LOAD_REG_IMMEDIATE(r0, PCR_MASK)
faf37c44	60	mtspr SPRN_PCR,r0
f7c32c24	61	mfspr r3,SPRN_LPCR
d4e58e59	62	ori r3, r3, LPCR_PECEDH
08a1e650	63	li r4,0 /* LPES = 0 */
700b7ead	64	bl __init_LPCR_ISA206
2a3563b0	65	bl __init_HFSCR
240686c1	66	bl __init_PMU_HV
393eb79a	67	bl __init_PMU_HV_ISA207
aec937b1 MN	68	mtlr r11
	69	blr
	70
	71	_GLOBAL(__restore_cpu_power8)
	72	mflr r11
57d23167	73	bl __init_FSCR
240686c1	74	bl __init_PMU
393eb79a	75	bl __init_PMU_ISA207
aec937b1 MN	76	mfmsr r3
aec937b1 MN	77	rldicl. r0,r3,4,63
8c2a3817	78	mtlr r11
aec937b1 MN	79	beqlr
	80	li r0,0
	81	mtspr SPRN_LPID,r0
13c7bb3c	82	LOAD_REG_IMMEDIATE(r0, PCR_MASK)
faf37c44	83	mtspr SPRN_PCR,r0
f7c32c24	84	mfspr r3,SPRN_LPCR
d4e58e59	85	ori r3, r3, LPCR_PECEDH
08a1e650	86	li r4,0 /* LPES = 0 */
700b7ead	87	bl __init_LPCR_ISA206
2a3563b0	88	bl __init_HFSCR
240686c1	89	bl __init_PMU_HV
393eb79a	90	bl __init_PMU_HV_ISA207
24cc67de BH	91	mtlr r11
	92	blr
	93
c3ab300e MN	94	_GLOBAL(__setup_cpu_power9)
	95	mflr r11
	96	bl __init_FSCR
393eb79a	97	bl __init_PMU
c3ab300e MN	98	bl __init_hvmode_206
	99	mtlr r11
	100	beqlr
	101	li r0,0
378f96d3	102	mtspr SPRN_PSSCR,r0
c3ab300e	103	mtspr SPRN_LPID,r0
371b8044	104	mtspr SPRN_PID,r0
13c7bb3c	105	LOAD_REG_IMMEDIATE(r0, PCR_MASK)
faf37c44	106	mtspr SPRN_PCR,r0
c3ab300e	107	mfspr r3,SPRN_LPCR
08a1e650	108	LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH \| LPCR_PECE_HVEE \| LPCR_HVICE \| LPCR_HEIC)
7a43906f	109	or r3, r3, r4
fda2d27d AK	110	LOAD_REG_IMMEDIATE(r4, LPCR_UPRT \| LPCR_HR)
fda2d27d AK	111	andc r3, r3, r4
8d1b48ef	112	li r4,0 /* LPES = 0 */
700b7ead	113	bl __init_LPCR_ISA300
c3ab300e	114	bl __init_HFSCR
393eb79a	115	bl __init_PMU_HV
c3ab300e MN	116	mtlr r11
	117	blr
	118
	119	_GLOBAL(__restore_cpu_power9)
	120	mflr r11
	121	bl __init_FSCR
393eb79a	122	bl __init_PMU
c3ab300e MN	123	mfmsr r3
	124	rldicl. r0,r3,4,63
	125	mtlr r11
	126	beqlr
	127	li r0,0
378f96d3	128	mtspr SPRN_PSSCR,r0
c3ab300e	129	mtspr SPRN_LPID,r0
371b8044	130	mtspr SPRN_PID,r0
13c7bb3c	131	LOAD_REG_IMMEDIATE(r0, PCR_MASK)
faf37c44	132	mtspr SPRN_PCR,r0
c3ab300e	133	mfspr r3,SPRN_LPCR
08a1e650	134	LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH \| LPCR_PECE_HVEE \| LPCR_HVICE \| LPCR_HEIC)
7a43906f	135	or r3, r3, r4
fda2d27d AK	136	LOAD_REG_IMMEDIATE(r4, LPCR_UPRT \| LPCR_HR)
fda2d27d AK	137	andc r3, r3, r4
8d1b48ef	138	li r4,0 /* LPES = 0 */
700b7ead	139	bl __init_LPCR_ISA300
c3ab300e	140	bl __init_HFSCR
393eb79a	141	bl __init_PMU_HV
c3ab300e MN	142	mtlr r11
	143	blr
	144
24cc67de	145	__init_hvmode_206:
969391c5	146	/* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
24cc67de BH	147	mfmsr r3
	148	rldicl. r0,r3,4,63
	149	bnelr
	150	ld r5,CPU_SPEC_FEATURES(r4)
e7b17d50 PM	151	LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE \| CPU_FTR_P9_TM_HV_ASSIST)
e7b17d50 PM	152	andc r5,r5,r6
24cc67de BH	153	std r5,CPU_SPEC_FEATURES(r4)
	154	blr
	155
700b7ead	156	__init_LPCR_ISA206:
24cc67de	157	/* Setup a sane LPCR:
08a1e650	158	* Called with initial LPCR in R3 and desired LPES 2-bit value in R4
24cc67de	159	*
a5d4f3ad	160	* LPES = 0b01 (HSRR0/1 used for 0x500)
24cc67de	161	* PECE = 0b111
895796a8	162	* DPFD = 4
923c53ca PM	163	* HDICE = 0
	164	* VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
	165	* VRMASD = 0b10000 (L=1, LP=00)
24cc67de BH	166	*
	167	* Other bits untouched for now
	168	*/
700b7ead NP	169	li r5,0x10
	170	rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
	171
	172	/* POWER9 has no VRMASD */
	173	__init_LPCR_ISA300:
08a1e650	174	rldimi r3,r4, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
24cc67de	175	ori r3,r3,(LPCR_PECE0\|LPCR_PECE1\|LPCR_PECE2)
895796a8	176	li r5,4
923c53ca PM	177	rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
	178	clrrdi r3,r3,1 /* clear HDICE */
	179	li r5,4
	180	rldimi r3,r5, LPCR_VC_SH, 0
24cc67de BH	181	mtspr SPRN_LPCR,r3
	182	isync
	183	blr
b144871c	184
2468dcf6 IM	185	__init_FSCR:
2468dcf6 IM	186	mfspr r3,SPRN_FSCR
1ddf499e	187	ori r3,r3,FSCR_TAR\|FSCR_DSCR\|FSCR_EBB
2468dcf6 IM	188	mtspr SPRN_FSCR,r3
	189	blr
	190
2a3563b0 MN	191	__init_HFSCR:
2a3563b0 MN	192	mfspr r3,SPRN_HFSCR
53b56ca0	193	ori r3,r3,HFSCR_TAR\|HFSCR_TM\|HFSCR_BHRB\|HFSCR_PM\|\
02ed21ae	194	HFSCR_DSCR\|HFSCR_VECVSX\|HFSCR_FP\|HFSCR_EBB\|HFSCR_MSGP
2a3563b0 MN	195	mtspr SPRN_HFSCR,r3
	196	blr
	197
240686c1 ME	198	__init_PMU_HV:
	199	li r5,0
	200	mtspr SPRN_MMCRC,r5
393eb79a MS	201	blr
	202
	203	__init_PMU_HV_ISA207:
	204	li r5,0
240686c1 ME	205	mtspr SPRN_MMCRH,r5
	206	blr
	207
	208	__init_PMU:
	209	li r5,0
240686c1 ME	210	mtspr SPRN_MMCRA,r5
	211	mtspr SPRN_MMCR0,r5
	212	mtspr SPRN_MMCR1,r5
	213	mtspr SPRN_MMCR2,r5
	214	blr
393eb79a MS	215
	216	__init_PMU_ISA207:
	217	li r5,0
	218	mtspr SPRN_MMCRS,r5
	219	blr