[linux-2.6-block.git] / arch / powerpc / kernel / cpu_setup_6xx.S

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * This file contains low level CPU setup functions.
 *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
 */

#include <asm/processor.h>
#include <asm/page.h>
#include <asm/cputable.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <asm/feature-fixups.h>

_GLOBAL(__setup_cpu_603)
	mflr	r5
BEGIN_MMU_FTR_SECTION
	li	r10,0
	mtspr	SPRN_SPRG_603_LRU,r10		/* init SW LRU tracking */
END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)

BEGIN_FTR_SECTION
	bl	__init_fpu_registers
END_FTR_SECTION_IFCLR(CPU_FTR_FPU_UNAVAILABLE)
	bl	setup_common_caches
	mtlr	r5
	blr
_GLOBAL(__setup_cpu_604)
	mflr	r5
	bl	setup_common_caches
	bl	setup_604_hid0
	mtlr	r5
	blr
_GLOBAL(__setup_cpu_750)
	mflr	r5
	bl	__init_fpu_registers
	bl	setup_common_caches
	bl	setup_750_7400_hid0
	mtlr	r5
	blr
_GLOBAL(__setup_cpu_750cx)
	mflr	r5
	bl	__init_fpu_registers
	bl	setup_common_caches
	bl	setup_750_7400_hid0
	bl	setup_750cx
	mtlr	r5
	blr
_GLOBAL(__setup_cpu_750fx)
	mflr	r5
	bl	__init_fpu_registers
	bl	setup_common_caches
	bl	setup_750_7400_hid0
	bl	setup_750fx
	mtlr	r5
	blr
_GLOBAL(__setup_cpu_7400)
	mflr	r5
	bl	__init_fpu_registers
	bl	setup_7400_workarounds
	bl	setup_common_caches
	bl	setup_750_7400_hid0
	mtlr	r5
	blr
_GLOBAL(__setup_cpu_7410)
	mflr	r5
	bl	__init_fpu_registers
	bl	setup_7410_workarounds
	bl	setup_common_caches
	bl	setup_750_7400_hid0
	li	r3,0
	mtspr	SPRN_L2CR2,r3
	mtlr	r5
	blr
_GLOBAL(__setup_cpu_745x)
	mflr	r5
	bl	setup_common_caches
	bl	setup_745x_specifics
	mtlr	r5
	blr

/* Enable caches for 603's, 604, 750 & 7400 */
setup_common_caches:
	mfspr	r11,SPRN_HID0
	andi.	r0,r11,HID0_DCE
	ori	r11,r11,HID0_ICE|HID0_DCE
	ori	r8,r11,HID0_ICFI
	bne	1f			/* don't invalidate the D-cache */
	ori	r8,r8,HID0_DCI		/* unless it wasn't enabled */
1:	sync
	mtspr	SPRN_HID0,r8		/* enable and invalidate caches */
	sync
	mtspr	SPRN_HID0,r11		/* enable caches */
	sync
	isync
	blr

/* 604, 604e, 604ev, ...
 * Enable superscalar execution & branch history table
 */
setup_604_hid0:
	mfspr	r11,SPRN_HID0
	ori	r11,r11,HID0_SIED|HID0_BHTE
	ori	r8,r11,HID0_BTCD
	sync
	mtspr	SPRN_HID0,r8	/* flush branch target address cache */
	sync			/* on 604e/604r */
	mtspr	SPRN_HID0,r11
	sync
	isync
	blr

/* 7400 <= rev 2.7 and 7410 rev = 1.0 suffer from some
 * erratas we work around here.
 * Moto MPC710CE.pdf describes them, those are errata
 * #3, #4 and #5
 * Note that we assume the firmware didn't choose to
 * apply other workarounds (there are other ones documented
 * in the .pdf). It appear that Apple firmware only works
 * around #3 and with the same fix we use. We may want to
 * check if the CPU is using 60x bus mode in which case
 * the workaround for errata #4 is useless. Also, we may
 * want to explicitly clear HID0_NOPDST as this is not
 * needed once we have applied workaround #5 (though it's
 * not set by Apple's firmware at least).
 */
setup_7400_workarounds:
	mfpvr	r3
	rlwinm	r3,r3,0,20,31
	cmpwi	0,r3,0x0207
	ble	1f
	blr
setup_7410_workarounds:
	mfpvr	r3
	rlwinm	r3,r3,0,20,31
	cmpwi	0,r3,0x0100
	bnelr
1:
	mfspr	r11,SPRN_MSSSR0
	/* Errata #3: Set L1OPQ_SIZE to 0x10 */
	rlwinm	r11,r11,0,9,6
	oris	r11,r11,0x0100
	/* Errata #4: Set L2MQ_SIZE to 1 (check for MPX mode first ?) */
	oris	r11,r11,0x0002
	/* Errata #5: Set DRLT_SIZE to 0x01 */
	rlwinm	r11,r11,0,5,2
	oris	r11,r11,0x0800
	sync
	mtspr	SPRN_MSSSR0,r11
	sync
	isync
	blr

/* 740/750/7400/7410
 * Enable Store Gathering (SGE), Address Broadcast (ABE),
 * Branch History Table (BHTE), Branch Target ICache (BTIC)
 * Dynamic Power Management (DPM), Speculative (SPD)
 * Clear Instruction cache throttling (ICTC)
 */
setup_750_7400_hid0:
	mfspr	r11,SPRN_HID0
	ori	r11,r11,HID0_SGE | HID0_ABE | HID0_BHTE | HID0_BTIC
	oris	r11,r11,HID0_DPM@h
BEGIN_FTR_SECTION
	xori	r11,r11,HID0_BTIC
END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)
BEGIN_FTR_SECTION
	xoris	r11,r11,HID0_DPM@h	/* disable dynamic power mgmt */
END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
	li	r3,HID0_SPD
	andc	r11,r11,r3		/* clear SPD: enable speculative */
 	li	r3,0
 	mtspr	SPRN_ICTC,r3		/* Instruction Cache Throttling off */
	isync
	mtspr	SPRN_HID0,r11
	sync
	isync
	blr

/* 750cx specific
 * Looks like we have to disable NAP feature for some PLL settings...
 * (waiting for confirmation)
 */
setup_750cx:
	mfspr	r10, SPRN_HID1
	rlwinm	r10,r10,4,28,31
	cmpwi	cr0,r10,7
	cmpwi	cr1,r10,9
	cmpwi	cr2,r10,11
	cror	4*cr0+eq,4*cr0+eq,4*cr1+eq
	cror	4*cr0+eq,4*cr0+eq,4*cr2+eq
	bnelr
	lwz	r6,CPU_SPEC_FEATURES(r4)
	li	r7,CPU_FTR_CAN_NAP
	andc	r6,r6,r7
	stw	r6,CPU_SPEC_FEATURES(r4)
	blr

/* 750fx specific
 */
setup_750fx:
	blr

/* MPC 745x
 * Enable Store Gathering (SGE), Branch Folding (FOLD)
 * Branch History Table (BHTE), Branch Target ICache (BTIC)
 * Dynamic Power Management (DPM), Speculative (SPD)
 * Ensure our data cache instructions really operate.
 * Timebase has to be running or we wouldn't have made it here,
 * just ensure we don't disable it.
 * Clear Instruction cache throttling (ICTC)
 * Enable L2 HW prefetch
 */
setup_745x_specifics:
	/* We check for the presence of an L3 cache setup by
	 * the firmware. If any, we disable NAP capability as
	 * it's known to be bogus on rev 2.1 and earlier
	 */
BEGIN_FTR_SECTION
	mfspr	r11,SPRN_L3CR
	andis.	r11,r11,L3CR_L3E@h
	beq	1f
END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
	lwz	r6,CPU_SPEC_FEATURES(r4)
	andis.	r0,r6,CPU_FTR_L3_DISABLE_NAP@h
	beq	1f
	li	r7,CPU_FTR_CAN_NAP
	andc	r6,r6,r7
	stw	r6,CPU_SPEC_FEATURES(r4)
1:
	mfspr	r11,SPRN_HID0

	/* All of the bits we have to set.....
	 */
	ori	r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE
	ori	r11,r11,HID0_LRSTK | HID0_BTIC
	oris	r11,r11,HID0_DPM@h
BEGIN_MMU_FTR_SECTION
	oris	r11,r11,HID0_HIGH_BAT@h
END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
BEGIN_FTR_SECTION
	xori	r11,r11,HID0_BTIC
END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)
BEGIN_FTR_SECTION
	xoris	r11,r11,HID0_DPM@h	/* disable dynamic power mgmt */
END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)

	/* All of the bits we have to clear....
	 */
	li	r3,HID0_SPD | HID0_NOPDST | HID0_NOPTI
	andc	r11,r11,r3		/* clear SPD: enable speculative */
 	li	r3,0

 	mtspr	SPRN_ICTC,r3		/* Instruction Cache Throttling off */
	isync
	mtspr	SPRN_HID0,r11
	sync
	isync

	/* Enable L2 HW prefetch, if L2 is enabled
	 */
	mfspr	r3,SPRN_L2CR
	andis.	r3,r3,L2CR_L2E@h
	beqlr
	mfspr	r3,SPRN_MSSCR0
	ori	r3,r3,3
	sync
	mtspr	SPRN_MSSCR0,r3
	sync
	isync
	blr

/*
 * Initialize the FPU registers. This is needed to work around an errata
 * in some 750 cpus where using a not yet initialized FPU register after
 * power on reset may hang the CPU
 */
_GLOBAL(__init_fpu_registers)
	mfmsr	r10
	ori	r11,r10,MSR_FP
	mtmsr	r11
	isync
	addis	r9,r3,empty_zero_page@ha
	addi	r9,r9,empty_zero_page@l
	REST_32FPRS(0,r9)
	sync
	mtmsr	r10
	isync
	blr


/* Definitions for the table use to save CPU states */
#define CS_HID0		0
#define CS_HID1		4
#define CS_HID2		8
#define	CS_MSSCR0	12
#define CS_MSSSR0	16
#define CS_ICTRL	20
#define CS_LDSTCR	24
#define CS_LDSTDB	28
#define CS_SIZE		32

	.data
	.balign	L1_CACHE_BYTES
cpu_state_storage:
	.space	CS_SIZE
	.balign	L1_CACHE_BYTES,0
	.text

/* Called in normal context to backup CPU 0 state. This
 * does not include cache settings. This function is also
 * called for machine sleep. This does not include the MMU
 * setup, BATs, etc... but rather the "special" registers
 * like HID0, HID1, MSSCR0, etc...
 */
_GLOBAL(__save_cpu_setup)
	/* Some CR fields are volatile, we back it up all */
	mfcr	r7

	/* Get storage ptr */
	lis	r5,cpu_state_storage@h
	ori	r5,r5,cpu_state_storage@l

	/* Save HID0 (common to all CONFIG_PPC_BOOK3S_32 cpus) */
	mfspr	r3,SPRN_HID0
	stw	r3,CS_HID0(r5)

	/* Now deal with CPU type dependent registers */
	mfspr	r3,SPRN_PVR
	srwi	r3,r3,16
	cmplwi	cr0,r3,0x8000	/* 7450 */
	cmplwi	cr1,r3,0x000c	/* 7400 */
	cmplwi	cr2,r3,0x800c	/* 7410 */
	cmplwi	cr3,r3,0x8001	/* 7455 */
	cmplwi	cr4,r3,0x8002	/* 7457 */
	cmplwi	cr5,r3,0x8003	/* 7447A */
	cmplwi	cr6,r3,0x7000	/* 750FX */
	cmplwi	cr7,r3,0x8004	/* 7448 */
	/* cr1 is 7400 || 7410 */
	cror	4*cr1+eq,4*cr1+eq,4*cr2+eq
	/* cr0 is 74xx */
	cror	4*cr0+eq,4*cr0+eq,4*cr3+eq
	cror	4*cr0+eq,4*cr0+eq,4*cr4+eq
	cror	4*cr0+eq,4*cr0+eq,4*cr1+eq
	cror	4*cr0+eq,4*cr0+eq,4*cr5+eq
	cror	4*cr0+eq,4*cr0+eq,4*cr7+eq
	bne	1f
	/* Backup 74xx specific regs */
	mfspr	r4,SPRN_MSSCR0
	stw	r4,CS_MSSCR0(r5)
	mfspr	r4,SPRN_MSSSR0
	stw	r4,CS_MSSSR0(r5)
	beq	cr1,1f
	/* Backup 745x specific registers */
	mfspr	r4,SPRN_HID1
	stw	r4,CS_HID1(r5)
	mfspr	r4,SPRN_ICTRL
	stw	r4,CS_ICTRL(r5)
	mfspr	r4,SPRN_LDSTCR
	stw	r4,CS_LDSTCR(r5)
	mfspr	r4,SPRN_LDSTDB
	stw	r4,CS_LDSTDB(r5)
1:
	bne	cr6,1f
	/* Backup 750FX specific registers */
	mfspr	r4,SPRN_HID1
	stw	r4,CS_HID1(r5)
	/* If rev 2.x, backup HID2 */
	mfspr	r3,SPRN_PVR
	andi.	r3,r3,0xff00
	cmpwi	cr0,r3,0x0200
	bne	1f
	mfspr	r4,SPRN_HID2
	stw	r4,CS_HID2(r5)
1:
	mtcr	r7
	blr

/* Called with no MMU context (typically MSR:IR/DR off) to
 * restore CPU state as backed up by the previous
 * function. This does not include cache setting
 */
_GLOBAL(__restore_cpu_setup)
	/* Some CR fields are volatile, we back it up all */
	mfcr	r7

	/* Get storage ptr */
	lis	r5,(cpu_state_storage-KERNELBASE)@h
	ori	r5,r5,cpu_state_storage@l

	/* Restore HID0 */
	lwz	r3,CS_HID0(r5)
	sync
	isync
	mtspr	SPRN_HID0,r3
	sync
	isync

	/* Now deal with CPU type dependent registers */
	mfspr	r3,SPRN_PVR
	srwi	r3,r3,16
	cmplwi	cr0,r3,0x8000	/* 7450 */
	cmplwi	cr1,r3,0x000c	/* 7400 */
	cmplwi	cr2,r3,0x800c	/* 7410 */
	cmplwi	cr3,r3,0x8001	/* 7455 */
	cmplwi	cr4,r3,0x8002	/* 7457 */
	cmplwi	cr5,r3,0x8003	/* 7447A */
	cmplwi	cr6,r3,0x7000	/* 750FX */
	cmplwi	cr7,r3,0x8004	/* 7448 */
	/* cr1 is 7400 || 7410 */
	cror	4*cr1+eq,4*cr1+eq,4*cr2+eq
	/* cr0 is 74xx */
	cror	4*cr0+eq,4*cr0+eq,4*cr3+eq
	cror	4*cr0+eq,4*cr0+eq,4*cr4+eq
	cror	4*cr0+eq,4*cr0+eq,4*cr1+eq
	cror	4*cr0+eq,4*cr0+eq,4*cr5+eq
	cror	4*cr0+eq,4*cr0+eq,4*cr7+eq
	bne	2f
	/* Restore 74xx specific regs */
	lwz	r4,CS_MSSCR0(r5)
	sync
	mtspr	SPRN_MSSCR0,r4
	sync
	isync
	lwz	r4,CS_MSSSR0(r5)
	sync
	mtspr	SPRN_MSSSR0,r4
	sync
	isync
	bne	cr2,1f
	/* Clear 7410 L2CR2 */
	li	r4,0
	mtspr	SPRN_L2CR2,r4
1:	beq	cr1,2f
	/* Restore 745x specific registers */
	lwz	r4,CS_HID1(r5)
	sync
	mtspr	SPRN_HID1,r4
	isync
	sync
	lwz	r4,CS_ICTRL(r5)
	sync
	mtspr	SPRN_ICTRL,r4
	isync
	sync
	lwz	r4,CS_LDSTCR(r5)
	sync
	mtspr	SPRN_LDSTCR,r4
	isync
	sync
	lwz	r4,CS_LDSTDB(r5)
	sync
	mtspr	SPRN_LDSTDB,r4
	isync
	sync
2:	bne	cr6,1f
	/* Restore 750FX specific registers
	 * that is restore HID2 on rev 2.x and PLL config & switch
	 * to PLL 0 on all
	 */
	/* If rev 2.x, restore HID2 with low voltage bit cleared */
	mfspr	r3,SPRN_PVR
	andi.	r3,r3,0xff00
	cmpwi	cr0,r3,0x0200
	bne	4f
	lwz	r4,CS_HID2(r5)
	rlwinm	r4,r4,0,19,17
	mtspr	SPRN_HID2,r4
	sync
4:
	lwz	r4,CS_HID1(r5)
	rlwinm  r5,r4,0,16,14
	mtspr	SPRN_HID1,r5
		/* Wait for PLL to stabilize */
	mftbl	r5
3:	mftbl	r6
	sub	r6,r6,r5
	cmplwi	cr0,r6,10000
	ble	3b
	/* Setup final PLL */
	mtspr	SPRN_HID1,r4
1:
	mtcr	r7
	blr
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
1da177e4 LT	2	/*
	3	* This file contains low level CPU setup functions.
	4	* Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
1da177e4 LT	5	*/
1da177e4 LT	6
1da177e4 LT	7	#include <asm/processor.h>
1da177e4 LT	8	#include <asm/page.h>
1da177e4 LT	9	#include <asm/cputable.h>
1da177e4 LT	10	#include <asm/ppc_asm.h>
0013a854	11	#include <asm/asm-offsets.h>
1da177e4	12	#include <asm/cache.h>
2319f123	13	#include <asm/mmu.h>
2c86cd18	14	#include <asm/feature-fixups.h>
1da177e4	15
1da177e4	16	_GLOBAL(__setup_cpu_603)
1f1936ff	17	mflr r5
2319f123 KG	18	BEGIN_MMU_FTR_SECTION
2319f123 KG	19	li r10,0
ee43eb78	20	mtspr SPRN_SPRG_603_LRU,r10 /* init SW LRU tracking */
2319f123	21	END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
93c4a162	22
fc215fe7 KG	23	BEGIN_FTR_SECTION
	24	bl __init_fpu_registers
	25	END_FTR_SECTION_IFCLR(CPU_FTR_FPU_UNAVAILABLE)
	26	bl setup_common_caches
1f1936ff	27	mtlr r5
fc215fe7	28	blr
1da177e4	29	_GLOBAL(__setup_cpu_604)
1f1936ff	30	mflr r5
1da177e4 LT	31	bl setup_common_caches
1da177e4 LT	32	bl setup_604_hid0
1f1936ff	33	mtlr r5
1da177e4 LT	34	blr
1da177e4 LT	35	_GLOBAL(__setup_cpu_750)
1f1936ff	36	mflr r5
f1c55dea	37	bl __init_fpu_registers
1da177e4 LT	38	bl setup_common_caches
1da177e4 LT	39	bl setup_750_7400_hid0
1f1936ff	40	mtlr r5
1da177e4 LT	41	blr
1da177e4 LT	42	_GLOBAL(__setup_cpu_750cx)
1f1936ff	43	mflr r5
f1c55dea	44	bl __init_fpu_registers
1da177e4 LT	45	bl setup_common_caches
	46	bl setup_750_7400_hid0
	47	bl setup_750cx
1f1936ff	48	mtlr r5
1da177e4 LT	49	blr
1da177e4 LT	50	_GLOBAL(__setup_cpu_750fx)
1f1936ff	51	mflr r5
f1c55dea	52	bl __init_fpu_registers
1da177e4 LT	53	bl setup_common_caches
	54	bl setup_750_7400_hid0
	55	bl setup_750fx
1f1936ff	56	mtlr r5
1da177e4 LT	57	blr
1da177e4 LT	58	_GLOBAL(__setup_cpu_7400)
1f1936ff	59	mflr r5
f1c55dea	60	bl __init_fpu_registers
1da177e4 LT	61	bl setup_7400_workarounds
	62	bl setup_common_caches
	63	bl setup_750_7400_hid0
1f1936ff	64	mtlr r5
1da177e4 LT	65	blr
1da177e4 LT	66	_GLOBAL(__setup_cpu_7410)
1f1936ff	67	mflr r5
f1c55dea	68	bl __init_fpu_registers
1da177e4 LT	69	bl setup_7410_workarounds
	70	bl setup_common_caches
	71	bl setup_750_7400_hid0
	72	li r3,0
	73	mtspr SPRN_L2CR2,r3
1f1936ff	74	mtlr r5
1da177e4 LT	75	blr
1da177e4 LT	76	_GLOBAL(__setup_cpu_745x)
1f1936ff	77	mflr r5
1da177e4 LT	78	bl setup_common_caches
1da177e4 LT	79	bl setup_745x_specifics
1f1936ff	80	mtlr r5
1da177e4 LT	81	blr
	82
	83	/* Enable caches for 603's, 604, 750 & 7400 */
	84	setup_common_caches:
	85	mfspr r11,SPRN_HID0
	86	andi. r0,r11,HID0_DCE
	87	ori r11,r11,HID0_ICE\|HID0_DCE
	88	ori r8,r11,HID0_ICFI
	89	bne 1f /* don't invalidate the D-cache */
	90	ori r8,r8,HID0_DCI /* unless it wasn't enabled */
	91	1: sync
f1c55dea	92	mtspr SPRN_HID0,r8 /* enable and invalidate caches */
1da177e4 LT	93	sync
	94	mtspr SPRN_HID0,r11 /* enable caches */
	95	sync
	96	isync
	97	blr
	98
	99	/* 604, 604e, 604ev, ...
	100	* Enable superscalar execution & branch history table
	101	*/
	102	setup_604_hid0:
	103	mfspr r11,SPRN_HID0
	104	ori r11,r11,HID0_SIED\|HID0_BHTE
	105	ori r8,r11,HID0_BTCD
	106	sync
	107	mtspr SPRN_HID0,r8 /* flush branch target address cache */
	108	sync /* on 604e/604r */
	109	mtspr SPRN_HID0,r11
	110	sync
	111	isync
	112	blr
	113
	114	/* 7400 <= rev 2.7 and 7410 rev = 1.0 suffer from some
	115	* erratas we work around here.
	116	* Moto MPC710CE.pdf describes them, those are errata
	117	* #3, #4 and #5
	118	* Note that we assume the firmware didn't choose to
	119	* apply other workarounds (there are other ones documented
	120	* in the .pdf). It appear that Apple firmware only works
	121	* around #3 and with the same fix we use. We may want to
	122	* check if the CPU is using 60x bus mode in which case
	123	* the workaround for errata #4 is useless. Also, we may
c03983ac	124	* want to explicitly clear HID0_NOPDST as this is not
1da177e4 LT	125	* needed once we have applied workaround #5 (though it's
	126	* not set by Apple's firmware at least).
	127	*/
	128	setup_7400_workarounds:
	129	mfpvr r3
	130	rlwinm r3,r3,0,20,31
	131	cmpwi 0,r3,0x0207
	132	ble 1f
	133	blr
	134	setup_7410_workarounds:
	135	mfpvr r3
	136	rlwinm r3,r3,0,20,31
	137	cmpwi 0,r3,0x0100
	138	bnelr
	139	1:
	140	mfspr r11,SPRN_MSSSR0
	141	/* Errata #3: Set L1OPQ_SIZE to 0x10 */
	142	rlwinm r11,r11,0,9,6
	143	oris r11,r11,0x0100
	144	/* Errata #4: Set L2MQ_SIZE to 1 (check for MPX mode first ?) */
	145	oris r11,r11,0x0002
	146	/* Errata #5: Set DRLT_SIZE to 0x01 */
	147	rlwinm r11,r11,0,5,2
	148	oris r11,r11,0x0800
	149	sync
	150	mtspr SPRN_MSSSR0,r11
	151	sync
	152	isync
	153	blr
	154
	155	/* 740/750/7400/7410
027dfac6	156	* Enable Store Gathering (SGE), Address Broadcast (ABE),
1da177e4 LT	157	* Branch History Table (BHTE), Branch Target ICache (BTIC)
	158	* Dynamic Power Management (DPM), Speculative (SPD)
	159	* Clear Instruction cache throttling (ICTC)
	160	*/
	161	setup_750_7400_hid0:
	162	mfspr r11,SPRN_HID0
	163	ori r11,r11,HID0_SGE \| HID0_ABE \| HID0_BHTE \| HID0_BTIC
f1c55dea	164	oris r11,r11,HID0_DPM@h
1da177e4	165	BEGIN_FTR_SECTION
f1c55dea BH	166	xori r11,r11,HID0_BTIC
	167	END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)
	168	BEGIN_FTR_SECTION
	169	xoris r11,r11,HID0_DPM@h /* disable dynamic power mgmt */
	170	END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
1da177e4 LT	171	li r3,HID0_SPD
	172	andc r11,r11,r3 /* clear SPD: enable speculative */
	173	li r3,0
	174	mtspr SPRN_ICTC,r3 /* Instruction Cache Throttling off */
	175	isync
	176	mtspr SPRN_HID0,r11
	177	sync
	178	isync
	179	blr
	180
	181	/* 750cx specific
	182	* Looks like we have to disable NAP feature for some PLL settings...
	183	* (waiting for confirmation)
	184	*/
	185	setup_750cx:
	186	mfspr r10, SPRN_HID1
	187	rlwinm r10,r10,4,28,31
	188	cmpwi cr0,r10,7
	189	cmpwi cr1,r10,9
	190	cmpwi cr2,r10,11
	191	cror 4cr0+eq,4cr0+eq,4*cr1+eq
	192	cror 4cr0+eq,4cr0+eq,4*cr2+eq
	193	bnelr
1f1936ff	194	lwz r6,CPU_SPEC_FEATURES(r4)
1da177e4 LT	195	li r7,CPU_FTR_CAN_NAP
1da177e4 LT	196	andc r6,r6,r7
1f1936ff	197	stw r6,CPU_SPEC_FEATURES(r4)
1da177e4 LT	198	blr
	199
	200	/* 750fx specific
	201	*/
	202	setup_750fx:
	203	blr
	204
	205	/* MPC 745x
	206	* Enable Store Gathering (SGE), Branch Folding (FOLD)
	207	* Branch History Table (BHTE), Branch Target ICache (BTIC)
	208	* Dynamic Power Management (DPM), Speculative (SPD)
	209	* Ensure our data cache instructions really operate.
	210	* Timebase has to be running or we wouldn't have made it here,
	211	* just ensure we don't disable it.
	212	* Clear Instruction cache throttling (ICTC)
	213	* Enable L2 HW prefetch
	214	*/
	215	setup_745x_specifics:
	216	/* We check for the presence of an L3 cache setup by
	217	* the firmware. If any, we disable NAP capability as
	218	* it's known to be bogus on rev 2.1 and earlier
	219	*/
2198c070	220	BEGIN_FTR_SECTION
1da177e4 LT	221	mfspr r11,SPRN_L3CR
	222	andis. r11,r11,L3CR_L3E@h
	223	beq 1f
2198c070	224	END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
1f1936ff	225	lwz r6,CPU_SPEC_FEATURES(r4)
9bbf0b57	226	andis. r0,r6,CPU_FTR_L3_DISABLE_NAP@h
1da177e4 LT	227	beq 1f
	228	li r7,CPU_FTR_CAN_NAP
	229	andc r6,r6,r7
1f1936ff	230	stw r6,CPU_SPEC_FEATURES(r4)
1da177e4 LT	231	1:
	232	mfspr r11,SPRN_HID0
	233
	234	/* All of the bits we have to set.....
	235	*/
f1c55dea BH	236	ori r11,r11,HID0_SGE \| HID0_FOLD \| HID0_BHTE
	237	ori r11,r11,HID0_LRSTK \| HID0_BTIC
	238	oris r11,r11,HID0_DPM@h
f1f8b494 GP	239	BEGIN_MMU_FTR_SECTION
	240	oris r11,r11,HID0_HIGH_BAT@h
	241	END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
1da177e4 LT	242	BEGIN_FTR_SECTION
	243	xori r11,r11,HID0_BTIC
	244	END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)
	245	BEGIN_FTR_SECTION
f1c55dea BH	246	xoris r11,r11,HID0_DPM@h /* disable dynamic power mgmt */
f1c55dea BH	247	END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
1da177e4 LT	248
	249	/* All of the bits we have to clear....
	250	*/
	251	li r3,HID0_SPD \| HID0_NOPDST \| HID0_NOPTI
	252	andc r11,r11,r3 /* clear SPD: enable speculative */
	253	li r3,0
	254
	255	mtspr SPRN_ICTC,r3 /* Instruction Cache Throttling off */
	256	isync
	257	mtspr SPRN_HID0,r11
	258	sync
	259	isync
	260
80ac2912	261	/* Enable L2 HW prefetch, if L2 is enabled
1da177e4	262	*/
80ac2912 KG	263	mfspr r3,SPRN_L2CR
	264	andis. r3,r3,L2CR_L2E@h
	265	beqlr
1da177e4 LT	266	mfspr r3,SPRN_MSSCR0
	267	ori r3,r3,3
	268	sync
	269	mtspr SPRN_MSSCR0,r3
	270	sync
	271	isync
	272	blr
	273
f1c55dea BH	274	/*
	275	* Initialize the FPU registers. This is needed to work around an errata
	276	* in some 750 cpus where using a not yet initialized FPU register after
	277	* power on reset may hang the CPU
	278	*/
	279	_GLOBAL(__init_fpu_registers)
	280	mfmsr r10
	281	ori r11,r10,MSR_FP
	282	mtmsr r11
	283	isync
	284	addis r9,r3,empty_zero_page@ha
	285	addi r9,r9,empty_zero_page@l
	286	REST_32FPRS(0,r9)
	287	sync
	288	mtmsr r10
	289	isync
	290	blr
	291
	292
1da177e4 LT	293	/* Definitions for the table use to save CPU states */
	294	#define CS_HID0 0
	295	#define CS_HID1 4
	296	#define CS_HID2 8
	297	#define CS_MSSCR0 12
	298	#define CS_MSSSR0 16
	299	#define CS_ICTRL 20
	300	#define CS_LDSTCR 24
	301	#define CS_LDSTDB 28
	302	#define CS_SIZE 32
	303
	304	.data
7dffb720	305	.balign L1_CACHE_BYTES
1da177e4 LT	306	cpu_state_storage:
1da177e4 LT	307	.space CS_SIZE
7dffb720	308	.balign L1_CACHE_BYTES,0
1da177e4 LT	309	.text
	310
	311	/* Called in normal context to backup CPU 0 state. This
	312	* does not include cache settings. This function is also
	313	* called for machine sleep. This does not include the MMU
	314	* setup, BATs, etc... but rather the "special" registers
	315	* like HID0, HID1, MSSCR0, etc...
	316	*/
	317	_GLOBAL(__save_cpu_setup)
	318	/* Some CR fields are volatile, we back it up all */
	319	mfcr r7
	320
	321	/* Get storage ptr */
	322	lis r5,cpu_state_storage@h
	323	ori r5,r5,cpu_state_storage@l
	324
d7cceda9	325	/* Save HID0 (common to all CONFIG_PPC_BOOK3S_32 cpus) */
1da177e4 LT	326	mfspr r3,SPRN_HID0
	327	stw r3,CS_HID0(r5)
	328
	329	/* Now deal with CPU type dependent registers */
	330	mfspr r3,SPRN_PVR
	331	srwi r3,r3,16
	332	cmplwi cr0,r3,0x8000 /* 7450 */
	333	cmplwi cr1,r3,0x000c /* 7400 */
	334	cmplwi cr2,r3,0x800c /* 7410 */
	335	cmplwi cr3,r3,0x8001 /* 7455 */
	336	cmplwi cr4,r3,0x8002 /* 7457 */
	337	cmplwi cr5,r3,0x8003 /* 7447A */
	338	cmplwi cr6,r3,0x7000 /* 750FX */
bbde630b	339	cmplwi cr7,r3,0x8004 /* 7448 */
1da177e4 LT	340	/* cr1 is 7400 \|\| 7410 */
	341	cror 4cr1+eq,4cr1+eq,4*cr2+eq
	342	/* cr0 is 74xx */
	343	cror 4cr0+eq,4cr0+eq,4*cr3+eq
	344	cror 4cr0+eq,4cr0+eq,4*cr4+eq
	345	cror 4cr0+eq,4cr0+eq,4*cr1+eq
	346	cror 4cr0+eq,4cr0+eq,4*cr5+eq
bbde630b	347	cror 4cr0+eq,4cr0+eq,4*cr7+eq
1da177e4 LT	348	bne 1f
	349	/* Backup 74xx specific regs */
	350	mfspr r4,SPRN_MSSCR0
	351	stw r4,CS_MSSCR0(r5)
	352	mfspr r4,SPRN_MSSSR0
	353	stw r4,CS_MSSSR0(r5)
	354	beq cr1,1f
	355	/* Backup 745x specific registers */
	356	mfspr r4,SPRN_HID1
	357	stw r4,CS_HID1(r5)
	358	mfspr r4,SPRN_ICTRL
	359	stw r4,CS_ICTRL(r5)
	360	mfspr r4,SPRN_LDSTCR
	361	stw r4,CS_LDSTCR(r5)
	362	mfspr r4,SPRN_LDSTDB
	363	stw r4,CS_LDSTDB(r5)
	364	1:
	365	bne cr6,1f
	366	/* Backup 750FX specific registers */
	367	mfspr r4,SPRN_HID1
	368	stw r4,CS_HID1(r5)
	369	/* If rev 2.x, backup HID2 */
	370	mfspr r3,SPRN_PVR
	371	andi. r3,r3,0xff00
	372	cmpwi cr0,r3,0x0200
	373	bne 1f
	374	mfspr r4,SPRN_HID2
	375	stw r4,CS_HID2(r5)
	376	1:
	377	mtcr r7
	378	blr
	379
	380	/* Called with no MMU context (typically MSR:IR/DR off) to
	381	* restore CPU state as backed up by the previous
	382	* function. This does not include cache setting
	383	*/
	384	_GLOBAL(__restore_cpu_setup)
	385	/* Some CR fields are volatile, we back it up all */
	386	mfcr r7
	387
	388	/* Get storage ptr */
	389	lis r5,(cpu_state_storage-KERNELBASE)@h
	390	ori r5,r5,cpu_state_storage@l
	391
	392	/* Restore HID0 */
	393	lwz r3,CS_HID0(r5)
	394	sync
	395	isync
	396	mtspr SPRN_HID0,r3
	397	sync
	398	isync
	399
	400	/* Now deal with CPU type dependent registers */
	401	mfspr r3,SPRN_PVR
	402	srwi r3,r3,16
	403	cmplwi cr0,r3,0x8000 /* 7450 */
	404	cmplwi cr1,r3,0x000c /* 7400 */
	405	cmplwi cr2,r3,0x800c /* 7410 */
	406	cmplwi cr3,r3,0x8001 /* 7455 */
	407	cmplwi cr4,r3,0x8002 /* 7457 */
	408	cmplwi cr5,r3,0x8003 /* 7447A */
	409	cmplwi cr6,r3,0x7000 /* 750FX */
bbde630b	410	cmplwi cr7,r3,0x8004 /* 7448 */
1da177e4 LT	411	/* cr1 is 7400 \|\| 7410 */
	412	cror 4cr1+eq,4cr1+eq,4*cr2+eq
	413	/* cr0 is 74xx */
	414	cror 4cr0+eq,4cr0+eq,4*cr3+eq
	415	cror 4cr0+eq,4cr0+eq,4*cr4+eq
	416	cror 4cr0+eq,4cr0+eq,4*cr1+eq
	417	cror 4cr0+eq,4cr0+eq,4*cr5+eq
bbde630b	418	cror 4cr0+eq,4cr0+eq,4*cr7+eq
1da177e4 LT	419	bne 2f
	420	/* Restore 74xx specific regs */
	421	lwz r4,CS_MSSCR0(r5)
	422	sync
	423	mtspr SPRN_MSSCR0,r4
	424	sync
	425	isync
	426	lwz r4,CS_MSSSR0(r5)
	427	sync
	428	mtspr SPRN_MSSSR0,r4
	429	sync
	430	isync
	431	bne cr2,1f
	432	/* Clear 7410 L2CR2 */
	433	li r4,0
	434	mtspr SPRN_L2CR2,r4
	435	1: beq cr1,2f
	436	/* Restore 745x specific registers */
	437	lwz r4,CS_HID1(r5)
	438	sync
	439	mtspr SPRN_HID1,r4
	440	isync
	441	sync
	442	lwz r4,CS_ICTRL(r5)
	443	sync
	444	mtspr SPRN_ICTRL,r4
	445	isync
	446	sync
	447	lwz r4,CS_LDSTCR(r5)
	448	sync
	449	mtspr SPRN_LDSTCR,r4
	450	isync
	451	sync
	452	lwz r4,CS_LDSTDB(r5)
	453	sync
	454	mtspr SPRN_LDSTDB,r4
	455	isync
	456	sync
	457	2: bne cr6,1f
	458	/* Restore 750FX specific registers
	459	* that is restore HID2 on rev 2.x and PLL config & switch
	460	* to PLL 0 on all
	461	*/
	462	/* If rev 2.x, restore HID2 with low voltage bit cleared */
	463	mfspr r3,SPRN_PVR
	464	andi. r3,r3,0xff00
	465	cmpwi cr0,r3,0x0200
	466	bne 4f
	467	lwz r4,CS_HID2(r5)
	468	rlwinm r4,r4,0,19,17
	469	mtspr SPRN_HID2,r4
	470	sync
	471	4:
	472	lwz r4,CS_HID1(r5)
	473	rlwinm r5,r4,0,16,14
	474	mtspr SPRN_HID1,r5
	475	/* Wait for PLL to stabilize */
	476	mftbl r5
	477	3: mftbl r6
	478	sub r6,r6,r5
	479	cmplwi cr0,r6,10000
	480	ble 3b
	481	/* Setup final PLL */
	482	mtspr SPRN_HID1,r4
483	1:
484	mtcr r7
485	blr
486