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powerpc, KVM: Split HVMODE_206 cpu feature bit into separate HV and architecture...
[linux-2.6-block.git] / arch / powerpc / kernel / asm-offsets.c
CommitLineData
14cf11af
PM		 1/*
2 * This program is used to generate definitions needed by
3 * assembly language modules.
4 *
5 * We use the technique used in the OSF Mach kernel code:
6 * generate asm statements containing #defines,
7 * compile this file to assembler, and then extract the
8 * #defines from the assembly-language output.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
14cf11af
PM		 16#include <linux/signal.h>
17#include <linux/sched.h>
18#include <linux/kernel.h>
19#include <linux/errno.h>
20#include <linux/string.h>
21#include <linux/types.h>
14cf11af
PM		 22#include <linux/mman.h>
23#include <linux/mm.h>
543b9fd3 24#include <linux/suspend.h>
ad7f7167 25#include <linux/hrtimer.h>
d1dead5c 26#ifdef CONFIG_PPC64
14cf11af
PM		 27#include <linux/time.h>
28#include <linux/hardirq.h>
d1dead5c 29#endif
d4d298fe 30#include <linux/kbuild.h>
d1dead5c 31
14cf11af
PM		 32#include <asm/io.h>
33#include <asm/page.h>
34#include <asm/pgtable.h>
35#include <asm/processor.h>
14cf11af
PM		 36#include <asm/cputable.h>
37#include <asm/thread_info.h>
033ef338 38#include <asm/rtas.h>
a7f290da 39#include <asm/vdso_datapage.h>
14cf11af
PM		 40#ifdef CONFIG_PPC64
41#include <asm/paca.h>
42#include <asm/lppaca.h>
14cf11af 43#include <asm/cache.h>
14cf11af 44#include <asm/compat.h>
11a27ad7 45#include <asm/mmu.h>
f04da0bc 46#include <asm/hvcall.h>
14cf11af 47#endif
3eb9cf07
SR		 48#ifdef CONFIG_PPC_ISERIES
49#include <asm/iseries/alpaca.h>
50#endif
989044ee 51#if defined(CONFIG_KVM) || defined(CONFIG_KVM_GUEST)
366d4b9b 52#include <linux/kvm_host.h>
0604675f 53#endif
989044ee
AG		 54#if defined(CONFIG_KVM) && defined(CONFIG_PPC_BOOK3S)
55#include <asm/kvm_book3s.h>
db93f574 56#endif
14cf11af 57
57e2a99f 58#ifdef CONFIG_PPC32
fca622c5
KG		 59#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
60#include "head_booke.h"
61#endif
57e2a99f 62#endif
fca622c5 63
55fd766b 64#if defined(CONFIG_PPC_FSL_BOOK3E)
19f5465e
TP		 65#include "../mm/mmu_decl.h"
66#endif
67
14cf11af
PM		 68int main(void)
69{
d1dead5c
SR		 70 DEFINE(THREAD, offsetof(struct task_struct, thread));
71 DEFINE(MM, offsetof(struct task_struct, mm));
5e696617 72 DEFINE(MMCONTEXTID, offsetof(struct mm_struct, context.id));
14cf11af 73#ifdef CONFIG_PPC64
d1dead5c 74 DEFINE(AUDITCONTEXT, offsetof(struct task_struct, audit_context));
9c1e1052
PM		 75 DEFINE(SIGSEGV, SIGSEGV);
76 DEFINE(NMI_MASK, NMI_MASK);
efcac658 77 DEFINE(THREAD_DSCR, offsetof(struct thread_struct, dscr));
d1dead5c 78#else
f7e4217b 79 DEFINE(THREAD_INFO, offsetof(struct task_struct, stack));
d1dead5c
SR		 80#endif /* CONFIG_PPC64 */
81
14cf11af 82 DEFINE(KSP, offsetof(struct thread_struct, ksp));
85218827 83 DEFINE(KSP_LIMIT, offsetof(struct thread_struct, ksp_limit));
14cf11af
PM		 84 DEFINE(PT_REGS, offsetof(struct thread_struct, regs));
85 DEFINE(THREAD_FPEXC_MODE, offsetof(struct thread_struct, fpexc_mode));
86 DEFINE(THREAD_FPR0, offsetof(struct thread_struct, fpr[0]));
87 DEFINE(THREAD_FPSCR, offsetof(struct thread_struct, fpscr));
14cf11af
PM		 88#ifdef CONFIG_ALTIVEC
89 DEFINE(THREAD_VR0, offsetof(struct thread_struct, vr[0]));
90 DEFINE(THREAD_VRSAVE, offsetof(struct thread_struct, vrsave));
91 DEFINE(THREAD_VSCR, offsetof(struct thread_struct, vscr));
92 DEFINE(THREAD_USED_VR, offsetof(struct thread_struct, used_vr));
93#endif /* CONFIG_ALTIVEC */
c6e6771b
MN		 94#ifdef CONFIG_VSX
95 DEFINE(THREAD_VSR0, offsetof(struct thread_struct, fpr));
96 DEFINE(THREAD_USED_VSR, offsetof(struct thread_struct, used_vsr));
97#endif /* CONFIG_VSX */
d1dead5c
SR		 98#ifdef CONFIG_PPC64
99 DEFINE(KSP_VSID, offsetof(struct thread_struct, ksp_vsid));
100#else /* CONFIG_PPC64 */
101 DEFINE(PGDIR, offsetof(struct thread_struct, pgdir));
d1dead5c
SR		 102#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
103 DEFINE(THREAD_DBCR0, offsetof(struct thread_struct, dbcr0));
d1dead5c 104#endif
14cf11af
PM		 105#ifdef CONFIG_SPE
106 DEFINE(THREAD_EVR0, offsetof(struct thread_struct, evr[0]));
107 DEFINE(THREAD_ACC, offsetof(struct thread_struct, acc));
108 DEFINE(THREAD_SPEFSCR, offsetof(struct thread_struct, spefscr));
109 DEFINE(THREAD_USED_SPE, offsetof(struct thread_struct, used_spe));
110#endif /* CONFIG_SPE */
d1dead5c 111#endif /* CONFIG_PPC64 */
97e49255
AG		 112#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
113 DEFINE(THREAD_KVM_SVCPU, offsetof(struct thread_struct, kvm_shadow_vcpu));
114#endif
d1dead5c
SR		 115
116 DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
f39224a8 117 DEFINE(TI_LOCAL_FLAGS, offsetof(struct thread_info, local_flags));
d1dead5c 118 DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count));
d1dead5c 119 DEFINE(TI_TASK, offsetof(struct thread_info, task));
d1dead5c 120 DEFINE(TI_CPU, offsetof(struct thread_info, cpu));
d1dead5c
SR		 121
122#ifdef CONFIG_PPC64
123 DEFINE(DCACHEL1LINESIZE, offsetof(struct ppc64_caches, dline_size));
124 DEFINE(DCACHEL1LOGLINESIZE, offsetof(struct ppc64_caches, log_dline_size));
125 DEFINE(DCACHEL1LINESPERPAGE, offsetof(struct ppc64_caches, dlines_per_page));
126 DEFINE(ICACHEL1LINESIZE, offsetof(struct ppc64_caches, iline_size));
127 DEFINE(ICACHEL1LOGLINESIZE, offsetof(struct ppc64_caches, log_iline_size));
128 DEFINE(ICACHEL1LINESPERPAGE, offsetof(struct ppc64_caches, ilines_per_page));
d1dead5c
SR		 129 /* paca */
130 DEFINE(PACA_SIZE, sizeof(struct paca_struct));
131 DEFINE(PACAPACAINDEX, offsetof(struct paca_struct, paca_index));
132 DEFINE(PACAPROCSTART, offsetof(struct paca_struct, cpu_start));
133 DEFINE(PACAKSAVE, offsetof(struct paca_struct, kstack));
134 DEFINE(PACACURRENT, offsetof(struct paca_struct, __current));
135 DEFINE(PACASAVEDMSR, offsetof(struct paca_struct, saved_msr));
d1dead5c
SR		 136 DEFINE(PACASTABRR, offsetof(struct paca_struct, stab_rr));
137 DEFINE(PACAR1, offsetof(struct paca_struct, saved_r1));
138 DEFINE(PACATOC, offsetof(struct paca_struct, kernel_toc));
1f6a93e4
PM		 139 DEFINE(PACAKBASE, offsetof(struct paca_struct, kernelbase));
140 DEFINE(PACAKMSR, offsetof(struct paca_struct, kernel_msr));
d04c56f7
PM		 141 DEFINE(PACASOFTIRQEN, offsetof(struct paca_struct, soft_enabled));
142 DEFINE(PACAHARDIRQEN, offsetof(struct paca_struct, hard_enabled));
d1dead5c 143 DEFINE(PACACONTEXTID, offsetof(struct paca_struct, context.id));
d0f13e3c
BH		 144#ifdef CONFIG_PPC_MM_SLICES
145 DEFINE(PACALOWSLICESPSIZE, offsetof(struct paca_struct,
146 context.low_slices_psize));
147 DEFINE(PACAHIGHSLICEPSIZE, offsetof(struct paca_struct,
148 context.high_slices_psize));
149 DEFINE(MMUPSIZEDEFSIZE, sizeof(struct mmu_psize_def));
91c60b5b 150#endif /* CONFIG_PPC_MM_SLICES */
dce6670a
BH		 151
152#ifdef CONFIG_PPC_BOOK3E
153 DEFINE(PACAPGD, offsetof(struct paca_struct, pgd));
154 DEFINE(PACA_KERNELPGD, offsetof(struct paca_struct, kernel_pgd));
155 DEFINE(PACA_EXGEN, offsetof(struct paca_struct, exgen));
156 DEFINE(PACA_EXTLB, offsetof(struct paca_struct, extlb));
157 DEFINE(PACA_EXMC, offsetof(struct paca_struct, exmc));
158 DEFINE(PACA_EXCRIT, offsetof(struct paca_struct, excrit));
159 DEFINE(PACA_EXDBG, offsetof(struct paca_struct, exdbg));
160 DEFINE(PACA_MC_STACK, offsetof(struct paca_struct, mc_kstack));
161 DEFINE(PACA_CRIT_STACK, offsetof(struct paca_struct, crit_kstack));
162 DEFINE(PACA_DBG_STACK, offsetof(struct paca_struct, dbg_kstack));
163#endif /* CONFIG_PPC_BOOK3E */
164
91c60b5b
BH		 165#ifdef CONFIG_PPC_STD_MMU_64
166 DEFINE(PACASTABREAL, offsetof(struct paca_struct, stab_real));
167 DEFINE(PACASTABVIRT, offsetof(struct paca_struct, stab_addr));
168 DEFINE(PACASLBCACHE, offsetof(struct paca_struct, slb_cache));
169 DEFINE(PACASLBCACHEPTR, offsetof(struct paca_struct, slb_cache_ptr));
170 DEFINE(PACAVMALLOCSLLP, offsetof(struct paca_struct, vmalloc_sllp));
171#ifdef CONFIG_PPC_MM_SLICES
d0f13e3c
BH		 172 DEFINE(MMUPSIZESLLP, offsetof(struct mmu_psize_def, sllp));
173#else
174 DEFINE(PACACONTEXTSLLP, offsetof(struct paca_struct, context.sllp));
d0f13e3c 175#endif /* CONFIG_PPC_MM_SLICES */
d1dead5c
SR		 176 DEFINE(PACA_EXGEN, offsetof(struct paca_struct, exgen));
177 DEFINE(PACA_EXMC, offsetof(struct paca_struct, exmc));
178 DEFINE(PACA_EXSLB, offsetof(struct paca_struct, exslb));
3356bb9f 179 DEFINE(PACALPPACAPTR, offsetof(struct paca_struct, lppaca_ptr));
2f6093c8 180 DEFINE(PACA_SLBSHADOWPTR, offsetof(struct paca_struct, slb_shadow_ptr));
11a27ad7
MN		 181 DEFINE(SLBSHADOW_STACKVSID,
182 offsetof(struct slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid));
183 DEFINE(SLBSHADOW_STACKESID,
184 offsetof(struct slb_shadow, save_area[SLB_NUM_BOLTED - 1].esid));
cf9efce0 185 DEFINE(SLBSHADOW_SAVEAREA, offsetof(struct slb_shadow, save_area));
d1dead5c
SR		 186 DEFINE(LPPACASRR0, offsetof(struct lppaca, saved_srr0));
187 DEFINE(LPPACASRR1, offsetof(struct lppaca, saved_srr1));
188 DEFINE(LPPACAANYINT, offsetof(struct lppaca, int_dword.any_int));
189 DEFINE(LPPACADECRINT, offsetof(struct lppaca, int_dword.fields.decr_int));
de56a948 190 DEFINE(LPPACA_PMCINUSE, offsetof(struct lppaca, pmcregs_in_use));
cf9efce0 191 DEFINE(LPPACA_DTLIDX, offsetof(struct lppaca, dtl_idx));
a8606e20 192 DEFINE(LPPACA_YIELDCOUNT, offsetof(struct lppaca, yield_count));
cf9efce0 193 DEFINE(PACA_DTL_RIDX, offsetof(struct paca_struct, dtl_ridx));
91c60b5b
BH		 194#endif /* CONFIG_PPC_STD_MMU_64 */
195 DEFINE(PACAEMERGSP, offsetof(struct paca_struct, emergency_sp));
196 DEFINE(PACAHWCPUID, offsetof(struct paca_struct, hw_cpu_id));
1fc711f7 197 DEFINE(PACAKEXECSTATE, offsetof(struct paca_struct, kexec_state));
cf9efce0
PM		 198 DEFINE(PACA_STARTTIME, offsetof(struct paca_struct, starttime));
199 DEFINE(PACA_STARTTIME_USER, offsetof(struct paca_struct, starttime_user));
91c60b5b
BH		 200 DEFINE(PACA_USER_TIME, offsetof(struct paca_struct, user_time));
201 DEFINE(PACA_SYSTEM_TIME, offsetof(struct paca_struct, system_time));
91c60b5b 202 DEFINE(PACA_TRAP_SAVE, offsetof(struct paca_struct, trap_save));
033ef338 203#endif /* CONFIG_PPC64 */
d1dead5c
SR		 204
205 /* RTAS */
206 DEFINE(RTASBASE, offsetof(struct rtas_t, base));
207 DEFINE(RTASENTRY, offsetof(struct rtas_t, entry));
d1dead5c 208
14cf11af 209 /* Interrupt register frame */
91120cc8 210 DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE);
14cf11af 211 DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs));
218d169c 212#ifdef CONFIG_PPC64
d1dead5c
SR		 213 /* Create extra stack space for SRR0 and SRR1 when calling prom/rtas. */
214 DEFINE(PROM_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16);
215 DEFINE(RTAS_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16);
57852a85
MK		 216
217 /* hcall statistics */
218 DEFINE(HCALL_STAT_SIZE, sizeof(struct hcall_stats));
219 DEFINE(HCALL_STAT_CALLS, offsetof(struct hcall_stats, num_calls));
220 DEFINE(HCALL_STAT_TB, offsetof(struct hcall_stats, tb_total));
221 DEFINE(HCALL_STAT_PURR, offsetof(struct hcall_stats, purr_total));
d1dead5c 222#endif /* CONFIG_PPC64 */
14cf11af
PM		 223 DEFINE(GPR0, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[0]));
224 DEFINE(GPR1, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[1]));
225 DEFINE(GPR2, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[2]));
226 DEFINE(GPR3, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[3]));
227 DEFINE(GPR4, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[4]));
228 DEFINE(GPR5, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[5]));
229 DEFINE(GPR6, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[6]));
230 DEFINE(GPR7, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[7]));
231 DEFINE(GPR8, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[8]));
232 DEFINE(GPR9, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[9]));
233 DEFINE(GPR10, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[10]));
234 DEFINE(GPR11, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[11]));
235 DEFINE(GPR12, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[12]));
236 DEFINE(GPR13, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[13]));
d1dead5c 237#ifndef CONFIG_PPC64
14cf11af
PM		 238 DEFINE(GPR14, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[14]));
239 DEFINE(GPR15, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[15]));
240 DEFINE(GPR16, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[16]));
241 DEFINE(GPR17, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[17]));
242 DEFINE(GPR18, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[18]));
243 DEFINE(GPR19, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[19]));
244 DEFINE(GPR20, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[20]));
245 DEFINE(GPR21, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[21]));
246 DEFINE(GPR22, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[22]));
247 DEFINE(GPR23, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[23]));
248 DEFINE(GPR24, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[24]));
249 DEFINE(GPR25, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[25]));
250 DEFINE(GPR26, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[26]));
251 DEFINE(GPR27, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[27]));
252 DEFINE(GPR28, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[28]));
253 DEFINE(GPR29, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[29]));
254 DEFINE(GPR30, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[30]));
255 DEFINE(GPR31, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[31]));
d1dead5c 256#endif /* CONFIG_PPC64 */
14cf11af
PM		 257 /*
258 * Note: these symbols include _ because they overlap with special
259 * register names
260 */
261 DEFINE(_NIP, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, nip));
262 DEFINE(_MSR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, msr));
263 DEFINE(_CTR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, ctr));
264 DEFINE(_LINK, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, link));
265 DEFINE(_CCR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, ccr));
14cf11af
PM		 266 DEFINE(_XER, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, xer));
267 DEFINE(_DAR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dar));
268 DEFINE(_DSISR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dsisr));
d1dead5c
SR		 269 DEFINE(ORIG_GPR3, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, orig_gpr3));
270 DEFINE(RESULT, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, result));
d73e0c99 271 DEFINE(_TRAP, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, trap));
d1dead5c
SR		 272#ifndef CONFIG_PPC64
273 DEFINE(_MQ, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, mq));
274 /*
275 * The PowerPC 400-class & Book-E processors have neither the DAR
276 * nor the DSISR SPRs. Hence, we overload them to hold the similar
277 * DEAR and ESR SPRs for such processors. For critical interrupts
278 * we use them to hold SRR0 and SRR1.
14cf11af
PM		 279 */
280 DEFINE(_DEAR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dar));
281 DEFINE(_ESR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dsisr));
d1dead5c 282#else /* CONFIG_PPC64 */
d1dead5c
SR		 283 DEFINE(SOFTE, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, softe));
284
285 /* These _only_ to be used with {PROM,RTAS}_FRAME_SIZE!!! */
286 DEFINE(_SRR0, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs));
287 DEFINE(_SRR1, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs)+8);
288#endif /* CONFIG_PPC64 */
289
57e2a99f 290#if defined(CONFIG_PPC32)
fca622c5
KG		 291#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
292 DEFINE(EXC_LVL_SIZE, STACK_EXC_LVL_FRAME_SIZE);
293 DEFINE(MAS0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
294 /* we overload MMUCR for 44x on MAS0 since they are mutually exclusive */
295 DEFINE(MMUCR, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
296 DEFINE(MAS1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas1));
297 DEFINE(MAS2, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas2));
298 DEFINE(MAS3, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas3));
299 DEFINE(MAS6, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas6));
300 DEFINE(MAS7, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas7));
301 DEFINE(_SRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr0));
302 DEFINE(_SRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr1));
303 DEFINE(_CSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr0));
304 DEFINE(_CSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr1));
305 DEFINE(_DSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr0));
306 DEFINE(_DSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr1));
307 DEFINE(SAVED_KSP_LIMIT, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, saved_ksp_limit));
308#endif
57e2a99f 309#endif
14cf11af
PM		 310 DEFINE(CLONE_VM, CLONE_VM);
311 DEFINE(CLONE_UNTRACED, CLONE_UNTRACED);
d1dead5c
SR		 312
313#ifndef CONFIG_PPC64
14cf11af 314 DEFINE(MM_PGD, offsetof(struct mm_struct, pgd));
d1dead5c 315#endif /* ! CONFIG_PPC64 */
14cf11af
PM		 316
317 /* About the CPU features table */
14cf11af
PM		 318 DEFINE(CPU_SPEC_FEATURES, offsetof(struct cpu_spec, cpu_features));
319 DEFINE(CPU_SPEC_SETUP, offsetof(struct cpu_spec, cpu_setup));
f39b7a55 320 DEFINE(CPU_SPEC_RESTORE, offsetof(struct cpu_spec, cpu_restore));
14cf11af 321
d1dead5c
SR		 322 DEFINE(pbe_address, offsetof(struct pbe, address));
323 DEFINE(pbe_orig_address, offsetof(struct pbe, orig_address));
324 DEFINE(pbe_next, offsetof(struct pbe, next));
14cf11af 325
543b9fd3 326#ifndef CONFIG_PPC64
fd582ec8 327 DEFINE(TASK_SIZE, TASK_SIZE);
d1dead5c 328 DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28);
a7f290da 329#endif /* ! CONFIG_PPC64 */
14cf11af 330
a7f290da
BH		 331 /* datapage offsets for use by vdso */
332 DEFINE(CFG_TB_ORIG_STAMP, offsetof(struct vdso_data, tb_orig_stamp));
333 DEFINE(CFG_TB_TICKS_PER_SEC, offsetof(struct vdso_data, tb_ticks_per_sec));
334 DEFINE(CFG_TB_TO_XS, offsetof(struct vdso_data, tb_to_xs));
335 DEFINE(CFG_STAMP_XSEC, offsetof(struct vdso_data, stamp_xsec));
336 DEFINE(CFG_TB_UPDATE_COUNT, offsetof(struct vdso_data, tb_update_count));
337 DEFINE(CFG_TZ_MINUTEWEST, offsetof(struct vdso_data, tz_minuteswest));
338 DEFINE(CFG_TZ_DSTTIME, offsetof(struct vdso_data, tz_dsttime));
339 DEFINE(CFG_SYSCALL_MAP32, offsetof(struct vdso_data, syscall_map_32));
340 DEFINE(WTOM_CLOCK_SEC, offsetof(struct vdso_data, wtom_clock_sec));
341 DEFINE(WTOM_CLOCK_NSEC, offsetof(struct vdso_data, wtom_clock_nsec));
597bc5c0 342 DEFINE(STAMP_XTIME, offsetof(struct vdso_data, stamp_xtime));
8fd63a9e 343 DEFINE(STAMP_SEC_FRAC, offsetof(struct vdso_data, stamp_sec_fraction));
fbe48175
OJ		 344 DEFINE(CFG_ICACHE_BLOCKSZ, offsetof(struct vdso_data, icache_block_size));
345 DEFINE(CFG_DCACHE_BLOCKSZ, offsetof(struct vdso_data, dcache_block_size));
346 DEFINE(CFG_ICACHE_LOGBLOCKSZ, offsetof(struct vdso_data, icache_log_block_size));
347 DEFINE(CFG_DCACHE_LOGBLOCKSZ, offsetof(struct vdso_data, dcache_log_block_size));
a7f290da
BH		 348#ifdef CONFIG_PPC64
349 DEFINE(CFG_SYSCALL_MAP64, offsetof(struct vdso_data, syscall_map_64));
14cf11af
PM		 350 DEFINE(TVAL64_TV_SEC, offsetof(struct timeval, tv_sec));
351 DEFINE(TVAL64_TV_USEC, offsetof(struct timeval, tv_usec));
352 DEFINE(TVAL32_TV_SEC, offsetof(struct compat_timeval, tv_sec));
353 DEFINE(TVAL32_TV_USEC, offsetof(struct compat_timeval, tv_usec));
0c37ec2a
BH		 354 DEFINE(TSPC64_TV_SEC, offsetof(struct timespec, tv_sec));
355 DEFINE(TSPC64_TV_NSEC, offsetof(struct timespec, tv_nsec));
a7f290da
BH		 356 DEFINE(TSPC32_TV_SEC, offsetof(struct compat_timespec, tv_sec));
357 DEFINE(TSPC32_TV_NSEC, offsetof(struct compat_timespec, tv_nsec));
358#else
359 DEFINE(TVAL32_TV_SEC, offsetof(struct timeval, tv_sec));
360 DEFINE(TVAL32_TV_USEC, offsetof(struct timeval, tv_usec));
0c37ec2a
BH		 361 DEFINE(TSPC32_TV_SEC, offsetof(struct timespec, tv_sec));
362 DEFINE(TSPC32_TV_NSEC, offsetof(struct timespec, tv_nsec));
a7f290da
BH		 363#endif
364 /* timeval/timezone offsets for use by vdso */
14cf11af
PM		 365 DEFINE(TZONE_TZ_MINWEST, offsetof(struct timezone, tz_minuteswest));
366 DEFINE(TZONE_TZ_DSTTIME, offsetof(struct timezone, tz_dsttime));
a7f290da
BH		 367
368 /* Other bits used by the vdso */
369 DEFINE(CLOCK_REALTIME, CLOCK_REALTIME);
370 DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC);
371 DEFINE(NSEC_PER_SEC, NSEC_PER_SEC);
151db1fc 372 DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
a7f290da 373
007d88d0
DW		 374#ifdef CONFIG_BUG
375 DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry));
376#endif
16a15a30
SR		 377
378#ifdef CONFIG_PPC_ISERIES
379 /* the assembler miscalculates the VSID values */
380 DEFINE(PAGE_OFFSET_ESID, GET_ESID(PAGE_OFFSET));
381 DEFINE(PAGE_OFFSET_VSID, KERNEL_VSID(PAGE_OFFSET));
382 DEFINE(VMALLOC_START_ESID, GET_ESID(VMALLOC_START));
383 DEFINE(VMALLOC_START_VSID, KERNEL_VSID(VMALLOC_START));
3eb9cf07
SR		 384
385 /* alpaca */
386 DEFINE(ALPACA_SIZE, sizeof(struct alpaca));
16a15a30 387#endif
ee7a76da 388
ee7a76da 389 DEFINE(PGD_TABLE_SIZE, PGD_TABLE_SIZE);
4ee7084e 390 DEFINE(PTE_SIZE, sizeof(pte_t));
bee86f14 391
bbf45ba5 392#ifdef CONFIG_KVM
bbf45ba5
HB		 393 DEFINE(VCPU_HOST_STACK, offsetof(struct kvm_vcpu, arch.host_stack));
394 DEFINE(VCPU_HOST_PID, offsetof(struct kvm_vcpu, arch.host_pid));
bbf45ba5 395 DEFINE(VCPU_GPRS, offsetof(struct kvm_vcpu, arch.gpr));
eab17672 396 DEFINE(VCPU_VRSAVE, offsetof(struct kvm_vcpu, arch.vrsave));
de56a948
PM		 397 DEFINE(VCPU_FPRS, offsetof(struct kvm_vcpu, arch.fpr));
398 DEFINE(VCPU_FPSCR, offsetof(struct kvm_vcpu, arch.fpscr));
399#ifdef CONFIG_ALTIVEC
400 DEFINE(VCPU_VRS, offsetof(struct kvm_vcpu, arch.vr));
401 DEFINE(VCPU_VSCR, offsetof(struct kvm_vcpu, arch.vscr));
402#endif
403#ifdef CONFIG_VSX
404 DEFINE(VCPU_VSRS, offsetof(struct kvm_vcpu, arch.vsr));
405#endif
406 DEFINE(VCPU_XER, offsetof(struct kvm_vcpu, arch.xer));
407 DEFINE(VCPU_CTR, offsetof(struct kvm_vcpu, arch.ctr));
408 DEFINE(VCPU_LR, offsetof(struct kvm_vcpu, arch.lr));
409 DEFINE(VCPU_CR, offsetof(struct kvm_vcpu, arch.cr));
410 DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.pc));
411#ifdef CONFIG_KVM_BOOK3S_64_HV
412 DEFINE(VCPU_MSR, offsetof(struct kvm_vcpu, arch.shregs.msr));
413 DEFINE(VCPU_SRR0, offsetof(struct kvm_vcpu, arch.shregs.srr0));
414 DEFINE(VCPU_SRR1, offsetof(struct kvm_vcpu, arch.shregs.srr1));
415 DEFINE(VCPU_SPRG0, offsetof(struct kvm_vcpu, arch.shregs.sprg0));
416 DEFINE(VCPU_SPRG1, offsetof(struct kvm_vcpu, arch.shregs.sprg1));
417 DEFINE(VCPU_SPRG2, offsetof(struct kvm_vcpu, arch.shregs.sprg2));
418 DEFINE(VCPU_SPRG3, offsetof(struct kvm_vcpu, arch.shregs.sprg3));
419#endif
bbf45ba5
HB		 420 DEFINE(VCPU_SPRG4, offsetof(struct kvm_vcpu, arch.sprg4));
421 DEFINE(VCPU_SPRG5, offsetof(struct kvm_vcpu, arch.sprg5));
422 DEFINE(VCPU_SPRG6, offsetof(struct kvm_vcpu, arch.sprg6));
423 DEFINE(VCPU_SPRG7, offsetof(struct kvm_vcpu, arch.sprg7));
49dd2c49 424 DEFINE(VCPU_SHADOW_PID, offsetof(struct kvm_vcpu, arch.shadow_pid));
dd9ebf1f 425 DEFINE(VCPU_SHADOW_PID1, offsetof(struct kvm_vcpu, arch.shadow_pid1));
96bc451a 426 DEFINE(VCPU_SHARED, offsetof(struct kvm_vcpu, arch.shared));
666e7252 427 DEFINE(VCPU_SHARED_MSR, offsetof(struct kvm_vcpu_arch_shared, msr));
ecee273f 428 DEFINE(VCPU_SHADOW_MSR, offsetof(struct kvm_vcpu, arch.shadow_msr));
bbf45ba5 429
00c3a37c 430 /* book3s */
de56a948
PM		 431#ifdef CONFIG_KVM_BOOK3S_64_HV
432 DEFINE(KVM_LPID, offsetof(struct kvm, arch.lpid));
433 DEFINE(KVM_SDR1, offsetof(struct kvm, arch.sdr1));
434 DEFINE(KVM_HOST_LPID, offsetof(struct kvm, arch.host_lpid));
435 DEFINE(KVM_HOST_LPCR, offsetof(struct kvm, arch.host_lpcr));
436 DEFINE(KVM_HOST_SDR1, offsetof(struct kvm, arch.host_sdr1));
437 DEFINE(KVM_TLBIE_LOCK, offsetof(struct kvm, arch.tlbie_lock));
438 DEFINE(KVM_ONLINE_CPUS, offsetof(struct kvm, online_vcpus.counter));
439 DEFINE(KVM_LAST_VCPU, offsetof(struct kvm, arch.last_vcpu));
aa04b4cc
PM		 440 DEFINE(KVM_LPCR, offsetof(struct kvm, arch.lpcr));
441 DEFINE(KVM_RMOR, offsetof(struct kvm, arch.rmor));
de56a948
PM		 442 DEFINE(VCPU_DSISR, offsetof(struct kvm_vcpu, arch.shregs.dsisr));
443 DEFINE(VCPU_DAR, offsetof(struct kvm_vcpu, arch.shregs.dar));
444#endif
00c3a37c 445#ifdef CONFIG_PPC_BOOK3S
de56a948
PM		 446 DEFINE(VCPU_KVM, offsetof(struct kvm_vcpu, kvm));
447 DEFINE(VCPU_VCPUID, offsetof(struct kvm_vcpu, vcpu_id));
62908905 448 DEFINE(VCPU_HOST_RETIP, offsetof(struct kvm_vcpu, arch.host_retip));
62908905 449 DEFINE(VCPU_HOST_MSR, offsetof(struct kvm_vcpu, arch.host_msr));
de56a948
PM		 450 DEFINE(VCPU_PURR, offsetof(struct kvm_vcpu, arch.purr));
451 DEFINE(VCPU_SPURR, offsetof(struct kvm_vcpu, arch.spurr));
452 DEFINE(VCPU_DSCR, offsetof(struct kvm_vcpu, arch.dscr));
453 DEFINE(VCPU_AMR, offsetof(struct kvm_vcpu, arch.amr));
454 DEFINE(VCPU_UAMOR, offsetof(struct kvm_vcpu, arch.uamor));
455 DEFINE(VCPU_CTRL, offsetof(struct kvm_vcpu, arch.ctrl));
456 DEFINE(VCPU_DABR, offsetof(struct kvm_vcpu, arch.dabr));
62908905
AG		 457 DEFINE(VCPU_TRAMPOLINE_LOWMEM, offsetof(struct kvm_vcpu, arch.trampoline_lowmem));
458 DEFINE(VCPU_TRAMPOLINE_ENTER, offsetof(struct kvm_vcpu, arch.trampoline_enter));
459 DEFINE(VCPU_HIGHMEM_HANDLER, offsetof(struct kvm_vcpu, arch.highmem_handler));
021ec9c6 460 DEFINE(VCPU_RMCALL, offsetof(struct kvm_vcpu, arch.rmcall));
62908905 461 DEFINE(VCPU_HFLAGS, offsetof(struct kvm_vcpu, arch.hflags));
de56a948
PM		 462 DEFINE(VCPU_DEC, offsetof(struct kvm_vcpu, arch.dec));
463 DEFINE(VCPU_DEC_EXPIRES, offsetof(struct kvm_vcpu, arch.dec_expires));
aa04b4cc 464 DEFINE(VCPU_PENDING_EXC, offsetof(struct kvm_vcpu, arch.pending_exceptions));
a8606e20 465 DEFINE(VCPU_VPA, offsetof(struct kvm_vcpu, arch.vpa));
de56a948
PM		 466 DEFINE(VCPU_MMCR, offsetof(struct kvm_vcpu, arch.mmcr));
467 DEFINE(VCPU_PMC, offsetof(struct kvm_vcpu, arch.pmc));
468 DEFINE(VCPU_SLB, offsetof(struct kvm_vcpu, arch.slb));
469 DEFINE(VCPU_SLB_MAX, offsetof(struct kvm_vcpu, arch.slb_max));
470 DEFINE(VCPU_SLB_NR, offsetof(struct kvm_vcpu, arch.slb_nr));
471 DEFINE(VCPU_LAST_CPU, offsetof(struct kvm_vcpu, arch.last_cpu));
472 DEFINE(VCPU_FAULT_DSISR, offsetof(struct kvm_vcpu, arch.fault_dsisr));
473 DEFINE(VCPU_FAULT_DAR, offsetof(struct kvm_vcpu, arch.fault_dar));
474 DEFINE(VCPU_LAST_INST, offsetof(struct kvm_vcpu, arch.last_inst));
475 DEFINE(VCPU_TRAP, offsetof(struct kvm_vcpu, arch.trap));
371fefd6
PM		 476 DEFINE(VCPU_PTID, offsetof(struct kvm_vcpu, arch.ptid));
477 DEFINE(VCORE_ENTRY_EXIT, offsetof(struct kvmppc_vcore, entry_exit_count));
478 DEFINE(VCORE_NAP_COUNT, offsetof(struct kvmppc_vcore, nap_count));
479 DEFINE(VCORE_IN_GUEST, offsetof(struct kvmppc_vcore, in_guest));
de56a948
PM		 480 DEFINE(VCPU_SVCPU, offsetof(struct kvmppc_vcpu_book3s, shadow_vcpu) -
481 offsetof(struct kvmppc_vcpu_book3s, vcpu));
482 DEFINE(VCPU_SLB_E, offsetof(struct kvmppc_slb, orige));
483 DEFINE(VCPU_SLB_V, offsetof(struct kvmppc_slb, origv));
484 DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb));
3c42bf8a
PM		 485
486#ifdef CONFIG_PPC_BOOK3S_64
de56a948 487#ifdef CONFIG_KVM_BOOK3S_PR
3c42bf8a 488# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, shadow_vcpu.f))
de56a948
PM		 489#else
490# define SVCPU_FIELD(x, f)
491#endif
3c42bf8a
PM		 492# define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, kvm_hstate.f))
493#else /* 32-bit */
494# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, f))
495# define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, hstate.f))
496#endif
497
498 SVCPU_FIELD(SVCPU_CR, cr);
499 SVCPU_FIELD(SVCPU_XER, xer);
500 SVCPU_FIELD(SVCPU_CTR, ctr);
501 SVCPU_FIELD(SVCPU_LR, lr);
502 SVCPU_FIELD(SVCPU_PC, pc);
503 SVCPU_FIELD(SVCPU_R0, gpr[0]);
504 SVCPU_FIELD(SVCPU_R1, gpr[1]);
505 SVCPU_FIELD(SVCPU_R2, gpr[2]);
506 SVCPU_FIELD(SVCPU_R3, gpr[3]);
507 SVCPU_FIELD(SVCPU_R4, gpr[4]);
508 SVCPU_FIELD(SVCPU_R5, gpr[5]);
509 SVCPU_FIELD(SVCPU_R6, gpr[6]);
510 SVCPU_FIELD(SVCPU_R7, gpr[7]);
511 SVCPU_FIELD(SVCPU_R8, gpr[8]);
512 SVCPU_FIELD(SVCPU_R9, gpr[9]);
513 SVCPU_FIELD(SVCPU_R10, gpr[10]);
514 SVCPU_FIELD(SVCPU_R11, gpr[11]);
515 SVCPU_FIELD(SVCPU_R12, gpr[12]);
516 SVCPU_FIELD(SVCPU_R13, gpr[13]);
517 SVCPU_FIELD(SVCPU_FAULT_DSISR, fault_dsisr);
518 SVCPU_FIELD(SVCPU_FAULT_DAR, fault_dar);
519 SVCPU_FIELD(SVCPU_LAST_INST, last_inst);
520 SVCPU_FIELD(SVCPU_SHADOW_SRR1, shadow_srr1);
0604675f 521#ifdef CONFIG_PPC_BOOK3S_32
3c42bf8a 522 SVCPU_FIELD(SVCPU_SR, sr);
0604675f 523#endif
3c42bf8a
PM		 524#ifdef CONFIG_PPC64
525 SVCPU_FIELD(SVCPU_SLB, slb);
526 SVCPU_FIELD(SVCPU_SLB_MAX, slb_max);
527#endif
528
529 HSTATE_FIELD(HSTATE_HOST_R1, host_r1);
530 HSTATE_FIELD(HSTATE_HOST_R2, host_r2);
de56a948 531 HSTATE_FIELD(HSTATE_HOST_MSR, host_msr);
3c42bf8a
PM		 532 HSTATE_FIELD(HSTATE_VMHANDLER, vmhandler);
533 HSTATE_FIELD(HSTATE_SCRATCH0, scratch0);
534 HSTATE_FIELD(HSTATE_SCRATCH1, scratch1);
535 HSTATE_FIELD(HSTATE_IN_GUEST, in_guest);
536
de56a948
PM		 537#ifdef CONFIG_KVM_BOOK3S_64_HV
538 HSTATE_FIELD(HSTATE_KVM_VCPU, kvm_vcpu);
371fefd6
PM		 539 HSTATE_FIELD(HSTATE_KVM_VCORE, kvm_vcore);
540 HSTATE_FIELD(HSTATE_XICS_PHYS, xics_phys);
de56a948
PM		 541 HSTATE_FIELD(HSTATE_MMCR, host_mmcr);
542 HSTATE_FIELD(HSTATE_PMC, host_pmc);
543 HSTATE_FIELD(HSTATE_PURR, host_purr);
544 HSTATE_FIELD(HSTATE_SPURR, host_spurr);
545 HSTATE_FIELD(HSTATE_DSCR, host_dscr);
546 HSTATE_FIELD(HSTATE_DABR, dabr);
547 HSTATE_FIELD(HSTATE_DECEXP, dec_expires);
548#endif /* CONFIG_KVM_BOOK3S_64_HV */
549
3c42bf8a 550#else /* CONFIG_PPC_BOOK3S */
7e57cba0
AG		 551 DEFINE(VCPU_CR, offsetof(struct kvm_vcpu, arch.cr));
552 DEFINE(VCPU_XER, offsetof(struct kvm_vcpu, arch.xer));
0604675f
AG		 553 DEFINE(VCPU_LR, offsetof(struct kvm_vcpu, arch.lr));
554 DEFINE(VCPU_CTR, offsetof(struct kvm_vcpu, arch.ctr));
555 DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.pc));
556 DEFINE(VCPU_LAST_INST, offsetof(struct kvm_vcpu, arch.last_inst));
557 DEFINE(VCPU_FAULT_DEAR, offsetof(struct kvm_vcpu, arch.fault_dear));
558 DEFINE(VCPU_FAULT_ESR, offsetof(struct kvm_vcpu, arch.fault_esr));
00c3a37c 559#endif /* CONFIG_PPC_BOOK3S */
3c42bf8a 560#endif /* CONFIG_KVM */
d17051cb
AG		 561
562#ifdef CONFIG_KVM_GUEST
563 DEFINE(KVM_MAGIC_SCRATCH1, offsetof(struct kvm_vcpu_arch_shared,
564 scratch1));
565 DEFINE(KVM_MAGIC_SCRATCH2, offsetof(struct kvm_vcpu_arch_shared,
566 scratch2));
567 DEFINE(KVM_MAGIC_SCRATCH3, offsetof(struct kvm_vcpu_arch_shared,
568 scratch3));
569 DEFINE(KVM_MAGIC_INT, offsetof(struct kvm_vcpu_arch_shared,
570 int_pending));
571 DEFINE(KVM_MAGIC_MSR, offsetof(struct kvm_vcpu_arch_shared, msr));
572 DEFINE(KVM_MAGIC_CRITICAL, offsetof(struct kvm_vcpu_arch_shared,
573 critical));
cbe487fa 574 DEFINE(KVM_MAGIC_SR, offsetof(struct kvm_vcpu_arch_shared, sr));
d17051cb
AG		 575#endif
576
ca9153a3
IY		 577#ifdef CONFIG_44x
578 DEFINE(PGD_T_LOG2, PGD_T_LOG2);
579 DEFINE(PTE_T_LOG2, PTE_T_LOG2);
580#endif
55fd766b 581#ifdef CONFIG_PPC_FSL_BOOK3E
78f62237
KG		 582 DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
583 DEFINE(TLBCAM_MAS0, offsetof(struct tlbcam, MAS0));
584 DEFINE(TLBCAM_MAS1, offsetof(struct tlbcam, MAS1));
585 DEFINE(TLBCAM_MAS2, offsetof(struct tlbcam, MAS2));
586 DEFINE(TLBCAM_MAS3, offsetof(struct tlbcam, MAS3));
587 DEFINE(TLBCAM_MAS7, offsetof(struct tlbcam, MAS7));
588#endif
bbf45ba5 589
4cd35f67
SW		 590#if defined(CONFIG_KVM) && defined(CONFIG_SPE)
591 DEFINE(VCPU_EVR, offsetof(struct kvm_vcpu, arch.evr[0]));
592 DEFINE(VCPU_ACC, offsetof(struct kvm_vcpu, arch.acc));
593 DEFINE(VCPU_SPEFSCR, offsetof(struct kvm_vcpu, arch.spefscr));
594 DEFINE(VCPU_HOST_SPEFSCR, offsetof(struct kvm_vcpu, arch.host_spefscr));
595#endif
596
73e75b41
HB		 597#ifdef CONFIG_KVM_EXIT_TIMING
598 DEFINE(VCPU_TIMING_EXIT_TBU, offsetof(struct kvm_vcpu,
599 arch.timing_exit.tv32.tbu));
600 DEFINE(VCPU_TIMING_EXIT_TBL, offsetof(struct kvm_vcpu,
601 arch.timing_exit.tv32.tbl));
602 DEFINE(VCPU_TIMING_LAST_ENTER_TBU, offsetof(struct kvm_vcpu,
603 arch.timing_last_enter.tv32.tbu));
604 DEFINE(VCPU_TIMING_LAST_ENTER_TBL, offsetof(struct kvm_vcpu,
605 arch.timing_last_enter.tv32.tbl));
606#endif
607
14cf11af
PM		 608 return 0;
609}
Linux 6.x block layer and io_uring tree(s)