[linux-block.git] / arch / powerpc / kernel / align.c

// SPDX-License-Identifier: GPL-2.0-or-later
/* align.c - handle alignment exceptions for the Power PC.
 *
 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
 * Copyright (c) 1998-1999 TiVo, Inc.
 *   PowerPC 403GCX modifications.
 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
 *   PowerPC 403GCX/405GP modifications.
 * Copyright (c) 2001-2002 PPC64 team, IBM Corp
 *   64-bit and Power4 support
 * Copyright (c) 2005 Benjamin Herrenschmidt, IBM Corp
 *                    <benh@kernel.crashing.org>
 *   Merge ppc32 and ppc64 implementations
 */

#include <linux/kernel.h>
#include <linux/mm.h>
#include <asm/processor.h>
#include <linux/uaccess.h>
#include <asm/cache.h>
#include <asm/cputable.h>
#include <asm/emulated_ops.h>
#include <asm/switch_to.h>
#include <asm/disassemble.h>
#include <asm/cpu_has_feature.h>
#include <asm/sstep.h>
#include <asm/inst.h>

struct aligninfo {
	unsigned char len;
	unsigned char flags;
};


#define INVALID	{ 0, 0 }

/* Bits in the flags field */
#define LD	0	/* load */
#define ST	1	/* store */
#define SE	2	/* sign-extend value, or FP ld/st as word */
#define SW	0x20	/* byte swap */
#define E4	0x40	/* SPE endianness is word */
#define E8	0x80	/* SPE endianness is double word */

#ifdef CONFIG_SPE

static struct aligninfo spe_aligninfo[32] = {
	{ 8, LD+E8 },		/* 0 00 00: evldd[x] */
	{ 8, LD+E4 },		/* 0 00 01: evldw[x] */
	{ 8, LD },		/* 0 00 10: evldh[x] */
	INVALID,		/* 0 00 11 */
	{ 2, LD },		/* 0 01 00: evlhhesplat[x] */
	INVALID,		/* 0 01 01 */
	{ 2, LD },		/* 0 01 10: evlhhousplat[x] */
	{ 2, LD+SE },		/* 0 01 11: evlhhossplat[x] */
	{ 4, LD },		/* 0 10 00: evlwhe[x] */
	INVALID,		/* 0 10 01 */
	{ 4, LD },		/* 0 10 10: evlwhou[x] */
	{ 4, LD+SE },		/* 0 10 11: evlwhos[x] */
	{ 4, LD+E4 },		/* 0 11 00: evlwwsplat[x] */
	INVALID,		/* 0 11 01 */
	{ 4, LD },		/* 0 11 10: evlwhsplat[x] */
	INVALID,		/* 0 11 11 */

	{ 8, ST+E8 },		/* 1 00 00: evstdd[x] */
	{ 8, ST+E4 },		/* 1 00 01: evstdw[x] */
	{ 8, ST },		/* 1 00 10: evstdh[x] */
	INVALID,		/* 1 00 11 */
	INVALID,		/* 1 01 00 */
	INVALID,		/* 1 01 01 */
	INVALID,		/* 1 01 10 */
	INVALID,		/* 1 01 11 */
	{ 4, ST },		/* 1 10 00: evstwhe[x] */
	INVALID,		/* 1 10 01 */
	{ 4, ST },		/* 1 10 10: evstwho[x] */
	INVALID,		/* 1 10 11 */
	{ 4, ST+E4 },		/* 1 11 00: evstwwe[x] */
	INVALID,		/* 1 11 01 */
	{ 4, ST+E4 },		/* 1 11 10: evstwwo[x] */
	INVALID,		/* 1 11 11 */
};

#define	EVLDD		0x00
#define	EVLDW		0x01
#define	EVLDH		0x02
#define	EVLHHESPLAT	0x04
#define	EVLHHOUSPLAT	0x06
#define	EVLHHOSSPLAT	0x07
#define	EVLWHE		0x08
#define	EVLWHOU		0x0A
#define	EVLWHOS		0x0B
#define	EVLWWSPLAT	0x0C
#define	EVLWHSPLAT	0x0E
#define	EVSTDD		0x10
#define	EVSTDW		0x11
#define	EVSTDH		0x12
#define	EVSTWHE		0x18
#define	EVSTWHO		0x1A
#define	EVSTWWE		0x1C
#define	EVSTWWO		0x1E

/*
 * Emulate SPE loads and stores.
 * Only Book-E has these instructions, and it does true little-endian,
 * so we don't need the address swizzling.
 */
static int emulate_spe(struct pt_regs *regs, unsigned int reg,
		       struct ppc_inst ppc_instr)
{
	int ret;
	union {
		u64 ll;
		u32 w[2];
		u16 h[4];
		u8 v[8];
	} data, temp;
	unsigned char __user *p, *addr;
	unsigned long *evr = &current->thread.evr[reg];
	unsigned int nb, flags, instr;

	instr = ppc_inst_val(ppc_instr);
	instr = (instr >> 1) & 0x1f;

	/* DAR has the operand effective address */
	addr = (unsigned char __user *)regs->dar;

	nb = spe_aligninfo[instr].len;
	flags = spe_aligninfo[instr].flags;

	/* Verify the address of the operand */
	if (unlikely(user_mode(regs) &&
		     !access_ok(addr, nb)))
		return -EFAULT;

	/* userland only */
	if (unlikely(!user_mode(regs)))
		return 0;

	flush_spe_to_thread(current);

	/* If we are loading, get the data from user space, else
	 * get it from register values
	 */
	if (flags & ST) {
		data.ll = 0;
		switch (instr) {
		case EVSTDD:
		case EVSTDW:
		case EVSTDH:
			data.w[0] = *evr;
			data.w[1] = regs->gpr[reg];
			break;
		case EVSTWHE:
			data.h[2] = *evr >> 16;
			data.h[3] = regs->gpr[reg] >> 16;
			break;
		case EVSTWHO:
			data.h[2] = *evr & 0xffff;
			data.h[3] = regs->gpr[reg] & 0xffff;
			break;
		case EVSTWWE:
			data.w[1] = *evr;
			break;
		case EVSTWWO:
			data.w[1] = regs->gpr[reg];
			break;
		default:
			return -EINVAL;
		}
	} else {
		temp.ll = data.ll = 0;
		ret = 0;
		p = addr;

		switch (nb) {
		case 8:
			ret |= __get_user_inatomic(temp.v[0], p++);
			ret |= __get_user_inatomic(temp.v[1], p++);
			ret |= __get_user_inatomic(temp.v[2], p++);
			ret |= __get_user_inatomic(temp.v[3], p++);
			fallthrough;
		case 4:
			ret |= __get_user_inatomic(temp.v[4], p++);
			ret |= __get_user_inatomic(temp.v[5], p++);
			fallthrough;
		case 2:
			ret |= __get_user_inatomic(temp.v[6], p++);
			ret |= __get_user_inatomic(temp.v[7], p++);
			if (unlikely(ret))
				return -EFAULT;
		}

		switch (instr) {
		case EVLDD:
		case EVLDW:
		case EVLDH:
			data.ll = temp.ll;
			break;
		case EVLHHESPLAT:
			data.h[0] = temp.h[3];
			data.h[2] = temp.h[3];
			break;
		case EVLHHOUSPLAT:
		case EVLHHOSSPLAT:
			data.h[1] = temp.h[3];
			data.h[3] = temp.h[3];
			break;
		case EVLWHE:
			data.h[0] = temp.h[2];
			data.h[2] = temp.h[3];
			break;
		case EVLWHOU:
		case EVLWHOS:
			data.h[1] = temp.h[2];
			data.h[3] = temp.h[3];
			break;
		case EVLWWSPLAT:
			data.w[0] = temp.w[1];
			data.w[1] = temp.w[1];
			break;
		case EVLWHSPLAT:
			data.h[0] = temp.h[2];
			data.h[1] = temp.h[2];
			data.h[2] = temp.h[3];
			data.h[3] = temp.h[3];
			break;
		default:
			return -EINVAL;
		}
	}

	if (flags & SW) {
		switch (flags & 0xf0) {
		case E8:
			data.ll = swab64(data.ll);
			break;
		case E4:
			data.w[0] = swab32(data.w[0]);
			data.w[1] = swab32(data.w[1]);
			break;
		/* Its half word endian */
		default:
			data.h[0] = swab16(data.h[0]);
			data.h[1] = swab16(data.h[1]);
			data.h[2] = swab16(data.h[2]);
			data.h[3] = swab16(data.h[3]);
			break;
		}
	}

	if (flags & SE) {
		data.w[0] = (s16)data.h[1];
		data.w[1] = (s16)data.h[3];
	}

	/* Store result to memory or update registers */
	if (flags & ST) {
		ret = 0;
		p = addr;
		switch (nb) {
		case 8:
			ret |= __put_user_inatomic(data.v[0], p++);
			ret |= __put_user_inatomic(data.v[1], p++);
			ret |= __put_user_inatomic(data.v[2], p++);
			ret |= __put_user_inatomic(data.v[3], p++);
			fallthrough;
		case 4:
			ret |= __put_user_inatomic(data.v[4], p++);
			ret |= __put_user_inatomic(data.v[5], p++);
			fallthrough;
		case 2:
			ret |= __put_user_inatomic(data.v[6], p++);
			ret |= __put_user_inatomic(data.v[7], p++);
		}
		if (unlikely(ret))
			return -EFAULT;
	} else {
		*evr = data.w[0];
		regs->gpr[reg] = data.w[1];
	}

	return 1;
}
#endif /* CONFIG_SPE */

/*
 * Called on alignment exception. Attempts to fixup
 *
 * Return 1 on success
 * Return 0 if unable to handle the interrupt
 * Return -EFAULT if data address is bad
 * Other negative return values indicate that the instruction can't
 * be emulated, and the process should be given a SIGBUS.
 */

int fix_alignment(struct pt_regs *regs)
{
	struct ppc_inst instr;
	struct instruction_op op;
	int r, type;

	/*
	 * We require a complete register set, if not, then our assembly
	 * is broken
	 */
	CHECK_FULL_REGS(regs);

	if (unlikely(__get_user_instr(instr, (void __user *)regs->nip)))
		return -EFAULT;
	if ((regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE)) {
		/* We don't handle PPC little-endian any more... */
		if (cpu_has_feature(CPU_FTR_PPC_LE))
			return -EIO;
		instr = ppc_inst_swab(instr);
	}

#ifdef CONFIG_SPE
	if (ppc_inst_primary_opcode(instr) == 0x4) {
		int reg = (ppc_inst_val(instr) >> 21) & 0x1f;
		PPC_WARN_ALIGNMENT(spe, regs);
		return emulate_spe(regs, reg, instr);
	}
#endif


	/*
	 * ISA 3.0 (such as P9) copy, copy_first, paste and paste_last alignment
	 * check.
	 *
	 * Send a SIGBUS to the process that caused the fault.
	 *
	 * We do not emulate these because paste may contain additional metadata
	 * when pasting to a co-processor. Furthermore, paste_last is the
	 * synchronisation point for preceding copy/paste sequences.
	 */
	if ((ppc_inst_val(instr) & 0xfc0006fe) == (PPC_INST_COPY & 0xfc0006fe))
		return -EIO;

	r = analyse_instr(&op, regs, instr);
	if (r < 0)
		return -EINVAL;

	type = GETTYPE(op.type);
	if (!OP_IS_LOAD_STORE(type)) {
		if (op.type != CACHEOP + DCBZ)
			return -EINVAL;
		PPC_WARN_ALIGNMENT(dcbz, regs);
		r = emulate_dcbz(op.ea, regs);
	} else {
		if (type == LARX || type == STCX)
			return -EIO;
		PPC_WARN_ALIGNMENT(unaligned, regs);
		r = emulate_loadstore(regs, &op);
	}

	if (!r)
		return 1;
	return r;
}
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4 LT	2	/* align.c - handle alignment exceptions for the Power PC.
	3	*
	4	* Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
	5	* Copyright (c) 1998-1999 TiVo, Inc.
	6	* PowerPC 403GCX modifications.
	7	* Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
	8	* PowerPC 403GCX/405GP modifications.
	9	* Copyright (c) 2001-2002 PPC64 team, IBM Corp
	10	* 64-bit and Power4 support
5daf9071 BH	11	* Copyright (c) 2005 Benjamin Herrenschmidt, IBM Corp
	12	* <benh@kernel.crashing.org>
	13	* Merge ppc32 and ppc64 implementations
1da177e4 LT	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/mm.h>
	18	#include <asm/processor.h>
7c0f6ba6	19	#include <linux/uaccess.h>
1da177e4 LT	20	#include <asm/cache.h>
1da177e4 LT	21	#include <asm/cputable.h>
80947e7c	22	#include <asm/emulated_ops.h>
ae3a197e	23	#include <asm/switch_to.h>
ddca156a	24	#include <asm/disassemble.h>
b92a226e	25	#include <asm/cpu_has_feature.h>
31bfdb03	26	#include <asm/sstep.h>
75346251	27	#include <asm/inst.h>
1da177e4 LT	28
	29	struct aligninfo {
	30	unsigned char len;
	31	unsigned char flags;
	32	};
	33
1da177e4 LT	34
	35	#define INVALID { 0, 0 }
	36
fab5db97 PM	37	/* Bits in the flags field */
	38	#define LD 0 /* load */
	39	#define ST 1 /* store */
c6d4267e	40	#define SE 2 /* sign-extend value, or FP ld/st as word */
fab5db97	41	#define SW 0x20 /* byte swap */
26caeb2e KG	42	#define E4 0x40 /* SPE endianness is word */
26caeb2e KG	43	#define E8 0x80 /* SPE endianness is double word */
f83319d7	44
26caeb2e KG	45	#ifdef CONFIG_SPE
	46
	47	static struct aligninfo spe_aligninfo[32] = {
	48	{ 8, LD+E8 }, /* 0 00 00: evldd[x] */
	49	{ 8, LD+E4 }, /* 0 00 01: evldw[x] */
	50	{ 8, LD }, /* 0 00 10: evldh[x] */
	51	INVALID, /* 0 00 11 */
	52	{ 2, LD }, /* 0 01 00: evlhhesplat[x] */
	53	INVALID, /* 0 01 01 */
	54	{ 2, LD }, /* 0 01 10: evlhhousplat[x] */
	55	{ 2, LD+SE }, /* 0 01 11: evlhhossplat[x] */
	56	{ 4, LD }, /* 0 10 00: evlwhe[x] */
	57	INVALID, /* 0 10 01 */
	58	{ 4, LD }, /* 0 10 10: evlwhou[x] */
	59	{ 4, LD+SE }, /* 0 10 11: evlwhos[x] */
	60	{ 4, LD+E4 }, /* 0 11 00: evlwwsplat[x] */
	61	INVALID, /* 0 11 01 */
	62	{ 4, LD }, /* 0 11 10: evlwhsplat[x] */
	63	INVALID, /* 0 11 11 */
	64
	65	{ 8, ST+E8 }, /* 1 00 00: evstdd[x] */
	66	{ 8, ST+E4 }, /* 1 00 01: evstdw[x] */
	67	{ 8, ST }, /* 1 00 10: evstdh[x] */
	68	INVALID, /* 1 00 11 */
	69	INVALID, /* 1 01 00 */
	70	INVALID, /* 1 01 01 */
	71	INVALID, /* 1 01 10 */
	72	INVALID, /* 1 01 11 */
	73	{ 4, ST }, /* 1 10 00: evstwhe[x] */
	74	INVALID, /* 1 10 01 */
	75	{ 4, ST }, /* 1 10 10: evstwho[x] */
	76	INVALID, /* 1 10 11 */
	77	{ 4, ST+E4 }, /* 1 11 00: evstwwe[x] */
	78	INVALID, /* 1 11 01 */
	79	{ 4, ST+E4 }, /* 1 11 10: evstwwo[x] */
	80	INVALID, /* 1 11 11 */
	81	};
	82
	83	#define EVLDD 0x00
	84	#define EVLDW 0x01
	85	#define EVLDH 0x02
	86	#define EVLHHESPLAT 0x04
	87	#define EVLHHOUSPLAT 0x06
	88	#define EVLHHOSSPLAT 0x07
	89	#define EVLWHE 0x08
	90	#define EVLWHOU 0x0A
	91	#define EVLWHOS 0x0B
	92	#define EVLWWSPLAT 0x0C
	93	#define EVLWHSPLAT 0x0E
	94	#define EVSTDD 0x10
	95	#define EVSTDW 0x11
	96	#define EVSTDH 0x12
	97	#define EVSTWHE 0x18
	98	#define EVSTWHO 0x1A
	99	#define EVSTWWE 0x1C
	100	#define EVSTWWO 0x1E
	101
	102	/*
	103	* Emulate SPE loads and stores.
	104	* Only Book-E has these instructions, and it does true little-endian,
	105	* so we don't need the address swizzling.
	106	*/
	107	static int emulate_spe(struct pt_regs *regs, unsigned int reg,
94afd069	108	struct ppc_inst ppc_instr)
26caeb2e	109	{
f626190d	110	int ret;
26caeb2e KG	111	union {
	112	u64 ll;
	113	u32 w[2];
	114	u16 h[4];
	115	u8 v[8];
	116	} data, temp;
	117	unsigned char __user p, addr;
	118	unsigned long *evr = &current->thread.evr[reg];
94afd069	119	unsigned int nb, flags, instr;
26caeb2e	120
94afd069	121	instr = ppc_inst_val(ppc_instr);
26caeb2e KG	122	instr = (instr >> 1) & 0x1f;
	123
	124	/* DAR has the operand effective address */
	125	addr = (unsigned char __user *)regs->dar;
	126
	127	nb = spe_aligninfo[instr].len;
	128	flags = spe_aligninfo[instr].flags;
	129
	130	/* Verify the address of the operand */
	131	if (unlikely(user_mode(regs) &&
96d4f267	132	!access_ok(addr, nb)))
26caeb2e KG	133	return -EFAULT;
	134
	135	/* userland only */
	136	if (unlikely(!user_mode(regs)))
	137	return 0;
	138
	139	flush_spe_to_thread(current);
	140
	141	/* If we are loading, get the data from user space, else
	142	* get it from register values
	143	*/
	144	if (flags & ST) {
	145	data.ll = 0;
	146	switch (instr) {
	147	case EVSTDD:
	148	case EVSTDW:
	149	case EVSTDH:
	150	data.w[0] = *evr;
	151	data.w[1] = regs->gpr[reg];
	152	break;
	153	case EVSTWHE:
	154	data.h[2] = *evr >> 16;
	155	data.h[3] = regs->gpr[reg] >> 16;
	156	break;
	157	case EVSTWHO:
	158	data.h[2] = *evr & 0xffff;
	159	data.h[3] = regs->gpr[reg] & 0xffff;
	160	break;
	161	case EVSTWWE:
	162	data.w[1] = *evr;
	163	break;
	164	case EVSTWWO:
	165	data.w[1] = regs->gpr[reg];
	166	break;
	167	default:
	168	return -EINVAL;
	169	}
	170	} else {
	171	temp.ll = data.ll = 0;
	172	ret = 0;
	173	p = addr;
	174
	175	switch (nb) {
	176	case 8:
	177	ret \|= __get_user_inatomic(temp.v[0], p++);
	178	ret \|= __get_user_inatomic(temp.v[1], p++);
	179	ret \|= __get_user_inatomic(temp.v[2], p++);
	180	ret \|= __get_user_inatomic(temp.v[3], p++);
5e66a0cb	181	fallthrough;
26caeb2e KG	182	case 4:
	183	ret \|= __get_user_inatomic(temp.v[4], p++);
	184	ret \|= __get_user_inatomic(temp.v[5], p++);
5e66a0cb	185	fallthrough;
26caeb2e KG	186	case 2:
	187	ret \|= __get_user_inatomic(temp.v[6], p++);
	188	ret \|= __get_user_inatomic(temp.v[7], p++);
	189	if (unlikely(ret))
	190	return -EFAULT;
	191	}
	192
	193	switch (instr) {
	194	case EVLDD:
	195	case EVLDW:
	196	case EVLDH:
	197	data.ll = temp.ll;
	198	break;
	199	case EVLHHESPLAT:
	200	data.h[0] = temp.h[3];
	201	data.h[2] = temp.h[3];
	202	break;
	203	case EVLHHOUSPLAT:
	204	case EVLHHOSSPLAT:
	205	data.h[1] = temp.h[3];
	206	data.h[3] = temp.h[3];
	207	break;
	208	case EVLWHE:
	209	data.h[0] = temp.h[2];
	210	data.h[2] = temp.h[3];
	211	break;
	212	case EVLWHOU:
	213	case EVLWHOS:
	214	data.h[1] = temp.h[2];
	215	data.h[3] = temp.h[3];
	216	break;
	217	case EVLWWSPLAT:
	218	data.w[0] = temp.w[1];
	219	data.w[1] = temp.w[1];
	220	break;
	221	case EVLWHSPLAT:
	222	data.h[0] = temp.h[2];
	223	data.h[1] = temp.h[2];
	224	data.h[2] = temp.h[3];
	225	data.h[3] = temp.h[3];
	226	break;
	227	default:
	228	return -EINVAL;
	229	}
	230	}
	231
	232	if (flags & SW) {
	233	switch (flags & 0xf0) {
	234	case E8:
f626190d	235	data.ll = swab64(data.ll);
26caeb2e KG	236	break;
26caeb2e KG	237	case E4:
f626190d AB	238	data.w[0] = swab32(data.w[0]);
f626190d AB	239	data.w[1] = swab32(data.w[1]);
26caeb2e KG	240	break;
	241	/* Its half word endian */
	242	default:
f626190d AB	243	data.h[0] = swab16(data.h[0]);
	244	data.h[1] = swab16(data.h[1]);
	245	data.h[2] = swab16(data.h[2]);
	246	data.h[3] = swab16(data.h[3]);
26caeb2e KG	247	break;
	248	}
	249	}
	250
	251	if (flags & SE) {
	252	data.w[0] = (s16)data.h[1];
	253	data.w[1] = (s16)data.h[3];
	254	}
	255
	256	/* Store result to memory or update registers */
	257	if (flags & ST) {
	258	ret = 0;
	259	p = addr;
	260	switch (nb) {
	261	case 8:
	262	ret \|= __put_user_inatomic(data.v[0], p++);
	263	ret \|= __put_user_inatomic(data.v[1], p++);
	264	ret \|= __put_user_inatomic(data.v[2], p++);
	265	ret \|= __put_user_inatomic(data.v[3], p++);
5e66a0cb	266	fallthrough;
26caeb2e KG	267	case 4:
	268	ret \|= __put_user_inatomic(data.v[4], p++);
	269	ret \|= __put_user_inatomic(data.v[5], p++);
5e66a0cb	270	fallthrough;
26caeb2e KG	271	case 2:
	272	ret \|= __put_user_inatomic(data.v[6], p++);
	273	ret \|= __put_user_inatomic(data.v[7], p++);
	274	}
	275	if (unlikely(ret))
	276	return -EFAULT;
	277	} else {
	278	*evr = data.w[0];
	279	regs->gpr[reg] = data.w[1];
	280	}
	281
	282	return 1;
	283	}
	284	#endif /* CONFIG_SPE */
5daf9071 BH	285
	286	/*
	287	* Called on alignment exception. Attempts to fixup
	288	*
	289	* Return 1 on success
	290	* Return 0 if unable to handle the interrupt
	291	* Return -EFAULT if data address is bad
31bfdb03 PM	292	* Other negative return values indicate that the instruction can't
31bfdb03 PM	293	* be emulated, and the process should be given a SIGBUS.
5daf9071 BH	294	*/
	295
	296	int fix_alignment(struct pt_regs *regs)
1da177e4	297	{
94afd069	298	struct ppc_inst instr;
31bfdb03 PM	299	struct instruction_op op;
31bfdb03 PM	300	int r, type;
1da177e4 LT	301
1da177e4 LT	302	/*
5daf9071 BH	303	* We require a complete register set, if not, then our assembly
5daf9071 BH	304	* is broken
1da177e4	305	*/
5daf9071	306	CHECK_FULL_REGS(regs);
1da177e4	307
5249385a	308	if (unlikely(__get_user_instr(instr, (void __user *)regs->nip)))
31bfdb03 PM	309	return -EFAULT;
	310	if ((regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE)) {
	311	/* We don't handle PPC little-endian any more... */
	312	if (cpu_has_feature(CPU_FTR_PPC_LE))
	313	return -EIO;
aabd2233	314	instr = ppc_inst_swab(instr);
1da177e4 LT	315	}
1da177e4 LT	316
26caeb2e	317	#ifdef CONFIG_SPE
8094892d	318	if (ppc_inst_primary_opcode(instr) == 0x4) {
777e26f0	319	int reg = (ppc_inst_val(instr) >> 21) & 0x1f;
eecff81d	320	PPC_WARN_ALIGNMENT(spe, regs);
26caeb2e	321	return emulate_spe(regs, reg, instr);
80947e7c	322	}
26caeb2e KG	323	#endif
26caeb2e KG	324
ae26b36f CS	325
	326	/*
	327	* ISA 3.0 (such as P9) copy, copy_first, paste and paste_last alignment
	328	* check.
	329	*
	330	* Send a SIGBUS to the process that caused the fault.
	331	*
	332	* We do not emulate these because paste may contain additional metadata
	333	* when pasting to a co-processor. Furthermore, paste_last is the
	334	* synchronisation point for preceding copy/paste sequences.
	335	*/
777e26f0	336	if ((ppc_inst_val(instr) & 0xfc0006fe) == (PPC_INST_COPY & 0xfc0006fe))
ae26b36f CS	337	return -EIO;
ae26b36f CS	338
31bfdb03 PM	339	r = analyse_instr(&op, regs, instr);
	340	if (r < 0)
	341	return -EINVAL;
5daf9071	342
e6684d07	343	type = GETTYPE(op.type);
31bfdb03	344	if (!OP_IS_LOAD_STORE(type)) {
1bc944ce	345	if (op.type != CACHEOP + DCBZ)
31bfdb03 PM	346	return -EINVAL;
	347	PPC_WARN_ALIGNMENT(dcbz, regs);
	348	r = emulate_dcbz(op.ea, regs);
	349	} else {
	350	if (type == LARX \|\| type == STCX)
	351	return -EIO;
	352	PPC_WARN_ALIGNMENT(unaligned, regs);
	353	r = emulate_loadstore(regs, &op);
1da177e4	354	}
5daf9071	355
31bfdb03 PM	356	if (!r)
	357	return 1;
	358	return r;
1da177e4	359	}