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1970282f SR |
1 | #ifndef _ASM_POWERPC_TLBFLUSH_H |
2 | #define _ASM_POWERPC_TLBFLUSH_H | |
e701d269 | 3 | |
1970282f SR |
4 | /* |
5 | * TLB flushing: | |
6 | * | |
7 | * - flush_tlb_mm(mm) flushes the specified mm context TLB's | |
8 | * - flush_tlb_page(vma, vmaddr) flushes one page | |
df3b8611 | 9 | * - local_flush_tlb_page(vmaddr) flushes one page on the local processor |
1970282f SR |
10 | * - flush_tlb_page_nohash(vma, vmaddr) flushes one page if SW loaded TLB |
11 | * - flush_tlb_range(vma, start, end) flushes a range of pages | |
12 | * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages | |
1970282f SR |
13 | * |
14 | * This program is free software; you can redistribute it and/or | |
15 | * modify it under the terms of the GNU General Public License | |
16 | * as published by the Free Software Foundation; either version | |
17 | * 2 of the License, or (at your option) any later version. | |
18 | */ | |
19 | #ifdef __KERNEL__ | |
20 | ||
62102307 DG |
21 | #if defined(CONFIG_4xx) || defined(CONFIG_8xx) || defined(CONFIG_FSL_BOOKE) |
22 | /* | |
23 | * TLB flushing for software loaded TLB chips | |
24 | * | |
25 | * TODO: (CONFIG_FSL_BOOKE) determine if flush_tlb_range & | |
26 | * flush_tlb_kernel_range are best implemented as tlbia vs | |
27 | * specific tlbie's | |
28 | */ | |
29 | ||
e701d269 BH |
30 | #include <linux/mm.h> |
31 | ||
32 | extern void _tlbie(unsigned long address, unsigned int pid); | |
0ba3418b KG |
33 | extern void _tlbil_all(void); |
34 | extern void _tlbil_pid(unsigned int pid); | |
35 | extern void _tlbil_va(unsigned long address, unsigned int pid); | |
62102307 DG |
36 | |
37 | #if defined(CONFIG_40x) || defined(CONFIG_8xx) | |
38 | #define _tlbia() asm volatile ("tlbia; sync" : : : "memory") | |
39 | #else /* CONFIG_44x || CONFIG_FSL_BOOKE */ | |
40 | extern void _tlbia(void); | |
41 | #endif | |
1970282f | 42 | |
62102307 DG |
43 | static inline void flush_tlb_mm(struct mm_struct *mm) |
44 | { | |
0ba3418b | 45 | _tlbil_pid(mm->context.id); |
62102307 DG |
46 | } |
47 | ||
df3b8611 KG |
48 | static inline void local_flush_tlb_page(unsigned long vmaddr) |
49 | { | |
50 | _tlbil_va(vmaddr, 0); | |
51 | } | |
52 | ||
62102307 DG |
53 | static inline void flush_tlb_page(struct vm_area_struct *vma, |
54 | unsigned long vmaddr) | |
55 | { | |
0ba3418b | 56 | _tlbil_va(vmaddr, vma ? vma->vm_mm->context.id : 0); |
62102307 DG |
57 | } |
58 | ||
59 | static inline void flush_tlb_page_nohash(struct vm_area_struct *vma, | |
60 | unsigned long vmaddr) | |
61 | { | |
0ba3418b | 62 | flush_tlb_page(vma, vmaddr); |
62102307 DG |
63 | } |
64 | ||
65 | static inline void flush_tlb_range(struct vm_area_struct *vma, | |
66 | unsigned long start, unsigned long end) | |
67 | { | |
0ba3418b | 68 | _tlbil_pid(vma->vm_mm->context.id); |
62102307 DG |
69 | } |
70 | ||
71 | static inline void flush_tlb_kernel_range(unsigned long start, | |
72 | unsigned long end) | |
73 | { | |
0ba3418b | 74 | _tlbil_pid(0); |
62102307 DG |
75 | } |
76 | ||
77 | #elif defined(CONFIG_PPC32) | |
78 | /* | |
79 | * TLB flushing for "classic" hash-MMMU 32-bit CPUs, 6xx, 7xx, 7xxx | |
80 | */ | |
81 | extern void _tlbie(unsigned long address); | |
82 | extern void _tlbia(void); | |
83 | ||
84 | extern void flush_tlb_mm(struct mm_struct *mm); | |
85 | extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr); | |
86 | extern void flush_tlb_page_nohash(struct vm_area_struct *vma, unsigned long addr); | |
87 | extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, | |
88 | unsigned long end); | |
89 | extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); | |
df3b8611 KG |
90 | static inline void local_flush_tlb_page(unsigned long vmaddr) |
91 | { | |
92 | flush_tlb_page(NULL, vmaddr); | |
93 | } | |
62102307 DG |
94 | |
95 | #else | |
96 | /* | |
97 | * TLB flushing for 64-bit has-MMU CPUs | |
98 | */ | |
1970282f SR |
99 | |
100 | #include <linux/percpu.h> | |
101 | #include <asm/page.h> | |
102 | ||
103 | #define PPC64_TLB_BATCH_NR 192 | |
104 | ||
105 | struct ppc64_tlb_batch { | |
a741e679 BH |
106 | int active; |
107 | unsigned long index; | |
108 | struct mm_struct *mm; | |
109 | real_pte_t pte[PPC64_TLB_BATCH_NR]; | |
110 | unsigned long vaddr[PPC64_TLB_BATCH_NR]; | |
111 | unsigned int psize; | |
1189be65 | 112 | int ssize; |
1970282f SR |
113 | }; |
114 | DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch); | |
115 | ||
116 | extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch); | |
117 | ||
a741e679 BH |
118 | extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr, |
119 | pte_t *ptep, unsigned long pte, int huge); | |
120 | ||
121 | #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE | |
122 | ||
123 | static inline void arch_enter_lazy_mmu_mode(void) | |
124 | { | |
125 | struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch); | |
126 | ||
127 | batch->active = 1; | |
128 | } | |
129 | ||
130 | static inline void arch_leave_lazy_mmu_mode(void) | |
1970282f | 131 | { |
a741e679 | 132 | struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch); |
1970282f SR |
133 | |
134 | if (batch->index) | |
135 | __flush_tlb_pending(batch); | |
a741e679 | 136 | batch->active = 0; |
1970282f SR |
137 | } |
138 | ||
a741e679 BH |
139 | #define arch_flush_lazy_mmu_mode() do {} while (0) |
140 | ||
141 | ||
3c726f8d | 142 | extern void flush_hash_page(unsigned long va, real_pte_t pte, int psize, |
1189be65 | 143 | int ssize, int local); |
3c726f8d | 144 | extern void flush_hash_range(unsigned long number, int local); |
1970282f | 145 | |
1970282f SR |
146 | |
147 | static inline void flush_tlb_mm(struct mm_struct *mm) | |
148 | { | |
1970282f SR |
149 | } |
150 | ||
df3b8611 KG |
151 | static inline void local_flush_tlb_page(unsigned long vmaddr) |
152 | { | |
153 | } | |
154 | ||
1970282f | 155 | static inline void flush_tlb_page(struct vm_area_struct *vma, |
62102307 | 156 | unsigned long vmaddr) |
1970282f | 157 | { |
1970282f SR |
158 | } |
159 | ||
160 | static inline void flush_tlb_page_nohash(struct vm_area_struct *vma, | |
161 | unsigned long vmaddr) | |
162 | { | |
1970282f SR |
163 | } |
164 | ||
165 | static inline void flush_tlb_range(struct vm_area_struct *vma, | |
62102307 | 166 | unsigned long start, unsigned long end) |
1970282f | 167 | { |
1970282f SR |
168 | } |
169 | ||
170 | static inline void flush_tlb_kernel_range(unsigned long start, | |
62102307 | 171 | unsigned long end) |
1970282f | 172 | { |
1970282f SR |
173 | } |
174 | ||
3d5134ee BH |
175 | /* Private function for use by PCI IO mapping code */ |
176 | extern void __flush_hash_table_range(struct mm_struct *mm, unsigned long start, | |
177 | unsigned long end); | |
178 | ||
179 | ||
1970282f SR |
180 | #endif |
181 | ||
1970282f SR |
182 | #endif /*__KERNEL__ */ |
183 | #endif /* _ASM_POWERPC_TLBFLUSH_H */ |