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2874c5fd | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
f2783c15 PM |
2 | /* |
3 | * Common time prototypes and such for all ppc machines. | |
4 | * | |
5 | * Written by Cort Dougan (cort@cs.nmt.edu) to merge | |
6 | * Paul Mackerras' version and mine for PReP and Pmac. | |
f2783c15 PM |
7 | */ |
8 | ||
9 | #ifndef __POWERPC_TIME_H | |
10 | #define __POWERPC_TIME_H | |
11 | ||
12 | #ifdef __KERNEL__ | |
f2783c15 PM |
13 | #include <linux/types.h> |
14 | #include <linux/percpu.h> | |
15 | ||
16 | #include <asm/processor.h> | |
b92a226e | 17 | #include <asm/cpu_has_feature.h> |
f2783c15 PM |
18 | |
19 | /* time.c */ | |
20 | extern unsigned long tb_ticks_per_jiffy; | |
21 | extern unsigned long tb_ticks_per_usec; | |
22 | extern unsigned long tb_ticks_per_sec; | |
6e35994d | 23 | extern struct clock_event_device decrementer_clockevent; |
f2783c15 | 24 | |
f2783c15 PM |
25 | |
26 | extern void generic_calibrate_decr(void); | |
8b604faf | 27 | extern void hdec_interrupt(struct pt_regs *regs); |
f2783c15 PM |
28 | |
29 | /* Some sane defaults: 125 MHz timebase, 1GHz processor */ | |
30 | extern unsigned long ppc_proc_freq; | |
31 | #define DEFAULT_PROC_FREQ (DEFAULT_TB_FREQ * 8) | |
32 | extern unsigned long ppc_tb_freq; | |
33 | #define DEFAULT_TB_FREQ 125000000UL | |
34 | ||
de269129 MS |
35 | extern bool tb_invalid; |
36 | ||
f2783c15 PM |
37 | struct div_result { |
38 | u64 result_high; | |
39 | u64 result_low; | |
40 | }; | |
41 | ||
42 | /* Accessor functions for the timebase (RTC on 601) registers. */ | |
43 | /* If one day CONFIG_POWER is added just define __USE_RTC as 1 */ | |
88fb3094 | 44 | #define __USE_RTC() (IS_ENABLED(CONFIG_PPC_BOOK3S_601)) |
f2783c15 | 45 | |
859deea9 BH |
46 | #ifdef CONFIG_PPC64 |
47 | ||
48 | /* For compatibility, get_tbl() is defined as get_tb() on ppc64 */ | |
49 | #define get_tbl get_tb | |
50 | ||
51 | #else | |
52 | ||
f2783c15 PM |
53 | static inline unsigned long get_tbl(void) |
54 | { | |
f2783c15 | 55 | #if defined(CONFIG_403GCX) |
859deea9 | 56 | unsigned long tbl; |
f2783c15 | 57 | asm volatile("mfspr %0, 0x3dd" : "=r" (tbl)); |
859deea9 | 58 | return tbl; |
f2783c15 | 59 | #else |
859deea9 | 60 | return mftbl(); |
f2783c15 | 61 | #endif |
f2783c15 PM |
62 | } |
63 | ||
64 | static inline unsigned int get_tbu(void) | |
65 | { | |
859deea9 | 66 | #ifdef CONFIG_403GCX |
f2783c15 | 67 | unsigned int tbu; |
f2783c15 | 68 | asm volatile("mfspr %0, 0x3dc" : "=r" (tbu)); |
859deea9 | 69 | return tbu; |
f2783c15 | 70 | #else |
859deea9 | 71 | return mftbu(); |
f2783c15 | 72 | #endif |
f2783c15 | 73 | } |
859deea9 | 74 | #endif /* !CONFIG_PPC64 */ |
f2783c15 PM |
75 | |
76 | static inline unsigned int get_rtcl(void) | |
77 | { | |
78 | unsigned int rtcl; | |
79 | ||
80 | asm volatile("mfrtcl %0" : "=r" (rtcl)); | |
81 | return rtcl; | |
82 | } | |
83 | ||
96c44507 PM |
84 | static inline u64 get_rtc(void) |
85 | { | |
86 | unsigned int hi, lo, hi2; | |
87 | ||
88 | do { | |
89 | asm volatile("mfrtcu %0; mfrtcl %1; mfrtcu %2" | |
90 | : "=r" (hi), "=r" (lo), "=r" (hi2)); | |
91 | } while (hi2 != hi); | |
92 | return (u64)hi * 1000000000 + lo; | |
93 | } | |
94 | ||
8f42ab27 AK |
95 | static inline u64 get_vtb(void) |
96 | { | |
97 | #ifdef CONFIG_PPC_BOOK3S_64 | |
98 | if (cpu_has_feature(CPU_FTR_ARCH_207S)) | |
905259e3 | 99 | return mfspr(SPRN_VTB); |
8f42ab27 AK |
100 | #endif |
101 | return 0; | |
102 | } | |
103 | ||
f2783c15 PM |
104 | #ifdef CONFIG_PPC64 |
105 | static inline u64 get_tb(void) | |
106 | { | |
107 | return mftb(); | |
108 | } | |
859deea9 | 109 | #else /* CONFIG_PPC64 */ |
f2783c15 PM |
110 | static inline u64 get_tb(void) |
111 | { | |
112 | unsigned int tbhi, tblo, tbhi2; | |
113 | ||
114 | do { | |
115 | tbhi = get_tbu(); | |
116 | tblo = get_tbl(); | |
117 | tbhi2 = get_tbu(); | |
118 | } while (tbhi != tbhi2); | |
119 | ||
120 | return ((u64)tbhi << 32) | tblo; | |
121 | } | |
859deea9 | 122 | #endif /* !CONFIG_PPC64 */ |
f2783c15 | 123 | |
c27da339 BH |
124 | static inline u64 get_tb_or_rtc(void) |
125 | { | |
126 | return __USE_RTC() ? get_rtc() : get_tb(); | |
127 | } | |
128 | ||
f2783c15 PM |
129 | static inline void set_tb(unsigned int upper, unsigned int lower) |
130 | { | |
131 | mtspr(SPRN_TBWL, 0); | |
132 | mtspr(SPRN_TBWU, upper); | |
133 | mtspr(SPRN_TBWL, lower); | |
134 | } | |
135 | ||
136 | /* Accessor functions for the decrementer register. | |
137 | * The 4xx doesn't even have a decrementer. I tried to use the | |
138 | * generic timer interrupt code, which seems OK, with the 4xx PIT | |
139 | * in auto-reload mode. The problem is PIT stops counting when it | |
140 | * hits zero. If it would wrap, we could use it just like a decrementer. | |
141 | */ | |
79901024 | 142 | static inline u64 get_dec(void) |
f2783c15 PM |
143 | { |
144 | #if defined(CONFIG_40x) | |
145 | return (mfspr(SPRN_PIT)); | |
146 | #else | |
147 | return (mfspr(SPRN_DEC)); | |
148 | #endif | |
149 | } | |
150 | ||
43875cc0 PM |
151 | /* |
152 | * Note: Book E and 4xx processors differ from other PowerPC processors | |
153 | * in when the decrementer generates its interrupt: on the 1 to 0 | |
154 | * transition for Book E/4xx, but on the 0 to -1 transition for others. | |
155 | */ | |
79901024 | 156 | static inline void set_dec(u64 val) |
f2783c15 PM |
157 | { |
158 | #if defined(CONFIG_40x) | |
79901024 | 159 | mtspr(SPRN_PIT, (u32) val); |
f2783c15 | 160 | #else |
43875cc0 PM |
161 | #ifndef CONFIG_BOOKE |
162 | --val; | |
f2783c15 | 163 | #endif |
43875cc0 | 164 | mtspr(SPRN_DEC, val); |
63e9e1c2 | 165 | #endif /* not 40x */ |
f2783c15 PM |
166 | } |
167 | ||
168 | static inline unsigned long tb_ticks_since(unsigned long tstamp) | |
169 | { | |
170 | if (__USE_RTC()) { | |
171 | int delta = get_rtcl() - (unsigned int) tstamp; | |
172 | return delta < 0 ? delta + 1000000000 : delta; | |
173 | } | |
174 | return get_tbl() - tstamp; | |
175 | } | |
176 | ||
177 | #define mulhwu(x,y) \ | |
178 | ({unsigned z; asm ("mulhwu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;}) | |
179 | ||
180 | #ifdef CONFIG_PPC64 | |
181 | #define mulhdu(x,y) \ | |
182 | ({unsigned long z; asm ("mulhdu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;}) | |
183 | #else | |
184 | extern u64 mulhdu(u64, u64); | |
185 | #endif | |
186 | ||
a5b518ed PM |
187 | extern void div128_by_32(u64 dividend_high, u64 dividend_low, |
188 | unsigned divisor, struct div_result *dr); | |
f2783c15 | 189 | |
d831d0b8 | 190 | extern void secondary_cpu_time_init(void); |
848092fa | 191 | extern void __init time_init(void); |
71712b45 | 192 | |
7df10275 | 193 | DECLARE_PER_CPU(u64, decrementers_next_tb); |
37fb9a02 | 194 | |
b6c295df PM |
195 | /* Convert timebase ticks to nanoseconds */ |
196 | unsigned long long tb_to_ns(unsigned long long tb_ticks); | |
197 | ||
f2783c15 | 198 | #endif /* __KERNEL__ */ |
7a69af63 | 199 | #endif /* __POWERPC_TIME_H */ |