[linux-2.6-block.git] / arch / powerpc / include / asm / sstep.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
 */

struct pt_regs;

/*
 * We don't allow single-stepping an mtmsrd that would clear
 * MSR_RI, since that would make the exception unrecoverable.
 * Since we need to single-step to proceed from a breakpoint,
 * we don't allow putting a breakpoint on an mtmsrd instruction.
 * Similarly we don't allow breakpoints on rfid instructions.
 * These macros tell us if an instruction is a mtmsrd or rfid.
 * Note that IS_MTMSRD returns true for both an mtmsr (32-bit)
 * and an mtmsrd (64-bit).
 */
#define IS_MTMSRD(instr)	(((instr) & 0xfc0007be) == 0x7c000124)
#define IS_RFID(instr)		(((instr) & 0xfc0007fe) == 0x4c000024)
#define IS_RFI(instr)		(((instr) & 0xfc0007fe) == 0x4c000064)

enum instruction_type {
	COMPUTE,		/* arith/logical/CR op, etc. */
	LOAD,			/* load and store types need to be contiguous */
	LOAD_MULTI,
	LOAD_FP,
	LOAD_VMX,
	LOAD_VSX,
	STORE,
	STORE_MULTI,
	STORE_FP,
	STORE_VMX,
	STORE_VSX,
	LARX,
	STCX,
	BRANCH,
	MFSPR,
	MTSPR,
	CACHEOP,
	BARRIER,
	SYSCALL,
	MFMSR,
	MTMSR,
	RFI,
	INTERRUPT,
	UNKNOWN
};

#define INSTR_TYPE_MASK	0x1f

#define OP_IS_LOAD_STORE(type)	(LOAD <= (type) && (type) <= STCX)

/* Compute flags, ORed in with type */
#define SETREG		0x20
#define SETCC		0x40
#define SETXER		0x80

/* Branch flags, ORed in with type */
#define SETLK		0x20
#define BRTAKEN		0x40
#define DECCTR		0x80

/* Load/store flags, ORed in with type */
#define SIGNEXT		0x20
#define UPDATE		0x40	/* matches bit in opcode 31 instructions */
#define BYTEREV		0x80
#define FPCONV		0x100

/* Barrier type field, ORed in with type */
#define BARRIER_MASK	0xe0
#define BARRIER_SYNC	0x00
#define BARRIER_ISYNC	0x20
#define BARRIER_EIEIO	0x40
#define BARRIER_LWSYNC	0x60
#define BARRIER_PTESYNC	0x80

/* Cacheop values, ORed in with type */
#define CACHEOP_MASK	0x700
#define DCBST		0
#define DCBF		0x100
#define DCBTST		0x200
#define DCBT		0x300
#define ICBI		0x400
#define DCBZ		0x500

/* VSX flags values */
#define VSX_FPCONV	1	/* do floating point SP/DP conversion */
#define VSX_SPLAT	2	/* store loaded value into all elements */
#define VSX_LDLEFT	4	/* load VSX register from left */
#define VSX_CHECK_VEC	8	/* check MSR_VEC not MSR_VSX for reg >= 32 */

/* Size field in type word */
#define SIZE(n)		((n) << 12)
#define GETSIZE(w)	((w) >> 12)

#define GETTYPE(t)	((t) & INSTR_TYPE_MASK)

#define MKOP(t, f, s)	((t) | (f) | SIZE(s))

struct instruction_op {
	int type;
	int reg;
	unsigned long val;
	/* For LOAD/STORE/LARX/STCX */
	unsigned long ea;
	int update_reg;
	/* For MFSPR */
	int spr;
	u32 ccval;
	u32 xerval;
	u8 element_size;	/* for VSX/VMX loads/stores */
	u8 vsx_flags;
};

union vsx_reg {
	u8	b[16];
	u16	h[8];
	u32	w[4];
	unsigned long d[2];
	float	fp[4];
	double	dp[2];
	__vector128 v;
};

/*
 * Decode an instruction, and return information about it in *op
 * without changing *regs.
 *
 * Return value is 1 if the instruction can be emulated just by
 * updating *regs with the information in *op, -1 if we need the
 * GPRs but *regs doesn't contain the full register set, or 0
 * otherwise.
 */
extern int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
			 unsigned int instr);

/*
 * Emulate an instruction that can be executed just by updating
 * fields in *regs.
 */
void emulate_update_regs(struct pt_regs *reg, struct instruction_op *op);

/*
 * Emulate instructions that cause a transfer of control,
 * arithmetic/logical instructions, loads and stores,
 * cache operations and barriers.
 *
 * Returns 1 if the instruction was emulated successfully,
 * 0 if it could not be emulated, or -1 for an instruction that
 * should not be emulated (rfid, mtmsrd clearing MSR_RI, etc.).
 */
extern int emulate_step(struct pt_regs *regs, unsigned int instr);

/*
 * Emulate a load or store instruction by reading/writing the
 * memory of the current process.  FP/VMX/VSX registers are assumed
 * to hold live values if the appropriate enable bit in regs->msr is
 * set; otherwise this will use the saved values in the thread struct
 * for user-mode accesses.
 */
extern int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op);

extern void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
			     const void *mem, bool cross_endian);
extern void emulate_vsx_store(struct instruction_op *op,
			      const union vsx_reg *reg, void *mem,
			      bool cross_endian);
extern int emulate_dcbz(unsigned long ea, struct pt_regs *regs);
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
1da177e4 LT	2	/*
1da177e4 LT	3	* Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
1da177e4 LT	4	*/
	5
	6	struct pt_regs;
	7
	8	/*
	9	* We don't allow single-stepping an mtmsrd that would clear
	10	* MSR_RI, since that would make the exception unrecoverable.
	11	* Since we need to single-step to proceed from a breakpoint,
	12	* we don't allow putting a breakpoint on an mtmsrd instruction.
	13	* Similarly we don't allow breakpoints on rfid instructions.
	14	* These macros tell us if an instruction is a mtmsrd or rfid.
c032524f PM	15	* Note that IS_MTMSRD returns true for both an mtmsr (32-bit)
c032524f PM	16	* and an mtmsrd (64-bit).
1da177e4	17	*/
c032524f	18	#define IS_MTMSRD(instr) (((instr) & 0xfc0007be) == 0x7c000124)
1da177e4	19	#define IS_RFID(instr) (((instr) & 0xfc0007fe) == 0x4c000024)
82090035	20	#define IS_RFI(instr) (((instr) & 0xfc0007fe) == 0x4c000064)
1da177e4	21
be96f633 PM	22	enum instruction_type {
be96f633 PM	23	COMPUTE, /* arith/logical/CR op, etc. */
d120cdbc	24	LOAD, /* load and store types need to be contiguous */
be96f633 PM	25	LOAD_MULTI,
	26	LOAD_FP,
	27	LOAD_VMX,
	28	LOAD_VSX,
	29	STORE,
	30	STORE_MULTI,
	31	STORE_FP,
	32	STORE_VMX,
	33	STORE_VSX,
	34	LARX,
	35	STCX,
	36	BRANCH,
	37	MFSPR,
	38	MTSPR,
	39	CACHEOP,
	40	BARRIER,
	41	SYSCALL,
	42	MFMSR,
	43	MTMSR,
	44	RFI,
	45	INTERRUPT,
	46	UNKNOWN
	47	};
	48
	49	#define INSTR_TYPE_MASK 0x1f
	50
d120cdbc PM	51	#define OP_IS_LOAD_STORE(type) (LOAD <= (type) && (type) <= STCX)
d120cdbc PM	52
3cdfcbfd PM	53	/* Compute flags, ORed in with type */
	54	#define SETREG 0x20
	55	#define SETCC 0x40
	56	#define SETXER 0x80
	57
	58	/* Branch flags, ORed in with type */
	59	#define SETLK 0x20
	60	#define BRTAKEN 0x40
	61	#define DECCTR 0x80
	62
be96f633 PM	63	/* Load/store flags, ORed in with type */
	64	#define SIGNEXT 0x20
	65	#define UPDATE 0x40 /* matches bit in opcode 31 instructions */
	66	#define BYTEREV 0x80
d2b65ac6	67	#define FPCONV 0x100
be96f633	68
3cdfcbfd PM	69	/* Barrier type field, ORed in with type */
	70	#define BARRIER_MASK 0xe0
	71	#define BARRIER_SYNC 0x00
	72	#define BARRIER_ISYNC 0x20
	73	#define BARRIER_EIEIO 0x40
	74	#define BARRIER_LWSYNC 0x60
	75	#define BARRIER_PTESYNC 0x80
	76
be96f633 PM	77	/* Cacheop values, ORed in with type */
	78	#define CACHEOP_MASK 0x700
	79	#define DCBST 0
	80	#define DCBF 0x100
	81	#define DCBTST 0x200
	82	#define DCBT 0x300
cf87c3f6	83	#define ICBI 0x400
b2543f7b	84	#define DCBZ 0x500
be96f633	85
350779a2 PM	86	/* VSX flags values */
	87	#define VSX_FPCONV 1 /* do floating point SP/DP conversion */
	88	#define VSX_SPLAT 2 /* store loaded value into all elements */
	89	#define VSX_LDLEFT 4 /* load VSX register from left */
	90	#define VSX_CHECK_VEC 8 /* check MSR_VEC not MSR_VSX for reg >= 32 */
	91
be96f633	92	/* Size field in type word */
d2b65ac6 PM	93	#define SIZE(n) ((n) << 12)
d2b65ac6 PM	94	#define GETSIZE(w) ((w) >> 12)
be96f633	95
e6684d07 RB	96	#define GETTYPE(t) ((t) & INSTR_TYPE_MASK)
e6684d07 RB	97
be96f633 PM	98	#define MKOP(t, f, s) ((t) \| (f) \| SIZE(s))
	99
	100	struct instruction_op {
	101	int type;
	102	int reg;
	103	unsigned long val;
	104	/* For LOAD/STORE/LARX/STCX */
	105	unsigned long ea;
	106	int update_reg;
	107	/* For MFSPR */
	108	int spr;
3cdfcbfd PM	109	u32 ccval;
3cdfcbfd PM	110	u32 xerval;
350779a2 PM	111	u8 element_size; /* for VSX/VMX loads/stores */
	112	u8 vsx_flags;
	113	};
	114
	115	union vsx_reg {
	116	u8 b[16];
	117	u16 h[8];
	118	u32 w[4];
	119	unsigned long d[2];
	120	float fp[4];
	121	double dp[2];
c22435a5	122	__vector128 v;
be96f633 PM	123	};
be96f633 PM	124
3cdfcbfd PM	125	/*
	126	* Decode an instruction, and return information about it in *op
	127	* without changing *regs.
	128	*
	129	* Return value is 1 if the instruction can be emulated just by
	130	* updating regs with the information in op, -1 if we need the
	131	* GPRs but *regs doesn't contain the full register set, or 0
	132	* otherwise.
	133	*/
	134	extern int analyse_instr(struct instruction_op op, const struct pt_regs regs,
be96f633	135	unsigned int instr);
3cdfcbfd PM	136
	137	/*
	138	* Emulate an instruction that can be executed just by updating
	139	* fields in *regs.
	140	*/
	141	void emulate_update_regs(struct pt_regs reg, struct instruction_op op);
	142
	143	/*
	144	* Emulate instructions that cause a transfer of control,
	145	* arithmetic/logical instructions, loads and stores,
	146	* cache operations and barriers.
	147	*
	148	* Returns 1 if the instruction was emulated successfully,
	149	* 0 if it could not be emulated, or -1 for an instruction that
	150	* should not be emulated (rfid, mtmsrd clearing MSR_RI, etc.).
	151	*/
	152	extern int emulate_step(struct pt_regs *regs, unsigned int instr);
	153
a53d5182 PM	154	/*
	155	* Emulate a load or store instruction by reading/writing the
	156	* memory of the current process. FP/VMX/VSX registers are assumed
	157	* to hold live values if the appropriate enable bit in regs->msr is
	158	* set; otherwise this will use the saved values in the thread struct
	159	* for user-mode accesses.
	160	*/
	161	extern int emulate_loadstore(struct pt_regs regs, struct instruction_op op);
	162
350779a2	163	extern void emulate_vsx_load(struct instruction_op op, union vsx_reg reg,
d955189a PM	164	const void *mem, bool cross_endian);
	165	extern void emulate_vsx_store(struct instruction_op *op,
	166	const union vsx_reg reg, void mem,
	167	bool cross_endian);
b2543f7b	168	extern int emulate_dcbz(unsigned long ea, struct pt_regs *regs);