Commit | Line | Data |
---|---|---|
2874c5fd | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
1da177e4 | 2 | /* |
5ad57078 | 3 | * smp.h: PowerPC-specific SMP code. |
1da177e4 LT |
4 | * |
5 | * Original was a copy of sparc smp.h. Now heavily modified | |
6 | * for PPC. | |
7 | * | |
8 | * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) | |
9 | * Copyright (C) 1996-2001 Cort Dougan <cort@fsmlabs.com> | |
1da177e4 LT |
10 | */ |
11 | ||
5ad57078 PM |
12 | #ifndef _ASM_POWERPC_SMP_H |
13 | #define _ASM_POWERPC_SMP_H | |
1da177e4 | 14 | #ifdef __KERNEL__ |
1da177e4 | 15 | |
1da177e4 LT |
16 | #include <linux/threads.h> |
17 | #include <linux/cpumask.h> | |
18 | #include <linux/kernel.h> | |
23d72bfd | 19 | #include <linux/irqreturn.h> |
1da177e4 LT |
20 | |
21 | #ifndef __ASSEMBLY__ | |
22 | ||
5ad57078 | 23 | #ifdef CONFIG_PPC64 |
1da177e4 | 24 | #include <asm/paca.h> |
5ad57078 | 25 | #endif |
d5a7430d | 26 | #include <asm/percpu.h> |
1da177e4 LT |
27 | |
28 | extern int boot_cpuid; | |
dc222fa7 | 29 | extern int boot_cpu_hwid; /* PPC64 only */ |
0875f1ce | 30 | extern int boot_core_hwid; |
7ac87abb | 31 | extern int spinning_secondaries; |
9f593f13 | 32 | extern u32 *cpu_to_phys_id; |
f9f130ff | 33 | extern bool coregroup_enabled; |
1da177e4 | 34 | |
3eb906c6 | 35 | extern int cpu_to_chip_id(int cpu); |
c1e53367 | 36 | extern int *chip_id_lookup_table; |
1da177e4 | 37 | |
a4bec516 GS |
38 | DECLARE_PER_CPU(cpumask_var_t, thread_group_l1_cache_map); |
39 | DECLARE_PER_CPU(cpumask_var_t, thread_group_l2_cache_map); | |
e9ef81e1 | 40 | DECLARE_PER_CPU(cpumask_var_t, thread_group_l3_cache_map); |
a4bec516 | 41 | |
1da177e4 LT |
42 | #ifdef CONFIG_SMP |
43 | ||
17f9c8a7 MM |
44 | struct smp_ops_t { |
45 | void (*message_pass)(int cpu, int msg); | |
1ece355b | 46 | #ifdef CONFIG_PPC_SMP_MUXED_IPI |
b866cc21 | 47 | void (*cause_ipi)(int cpu); |
1ece355b | 48 | #endif |
c64af645 | 49 | int (*cause_nmi_ipi)(int cpu); |
a7f4ee1f | 50 | void (*probe)(void); |
17f9c8a7 | 51 | int (*kick_cpu)(int nr); |
14d4ae5c | 52 | int (*prepare_cpu)(int nr); |
17f9c8a7 MM |
53 | void (*setup_cpu)(int nr); |
54 | void (*bringup_done)(void); | |
55 | void (*take_timebase)(void); | |
56 | void (*give_timebase)(void); | |
57 | int (*cpu_disable)(void); | |
58 | void (*cpu_die)(unsigned int nr); | |
59 | int (*cpu_bootable)(unsigned int nr); | |
39f87561 ME |
60 | #ifdef CONFIG_HOTPLUG_CPU |
61 | void (*cpu_offline_self)(void); | |
62 | #endif | |
17f9c8a7 MM |
63 | }; |
64 | ||
76222808 CL |
65 | extern struct task_struct *secondary_current; |
66 | ||
67 | void start_secondary(void *unused); | |
2104180a | 68 | extern int smp_send_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us); |
6ba55716 | 69 | extern int smp_send_safe_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us); |
e0476371 | 70 | extern void smp_send_debugger_break(void); |
5e00d69c | 71 | extern void __noreturn start_secondary_resume(void); |
cad5cef6 GKH |
72 | extern void smp_generic_give_timebase(void); |
73 | extern void smp_generic_take_timebase(void); | |
1da177e4 | 74 | |
6b7487fc | 75 | DECLARE_PER_CPU(unsigned int, cpu_pvr); |
1c21a293 | 76 | |
1da177e4 | 77 | #ifdef CONFIG_HOTPLUG_CPU |
1da177e4 | 78 | int generic_cpu_disable(void); |
1da177e4 | 79 | void generic_cpu_die(unsigned int cpu); |
105765f4 | 80 | void generic_set_cpu_dead(unsigned int cpu); |
ae5cab47 | 81 | void generic_set_cpu_up(unsigned int cpu); |
fb82b839 | 82 | int generic_check_cpu_restart(unsigned int cpu); |
2f4f1f81 | 83 | int is_cpu_dead(unsigned int cpu); |
84 | #else | |
85 | #define generic_set_cpu_up(i) do { } while (0) | |
1da177e4 LT |
86 | #endif |
87 | ||
5ad57078 | 88 | #ifdef CONFIG_PPC64 |
048c8bc9 | 89 | #define raw_smp_processor_id() (local_paca->paca_index) |
1da177e4 | 90 | #define hard_smp_processor_id() (get_paca()->hw_cpu_id) |
5ad57078 PM |
91 | #else |
92 | /* 32-bit */ | |
93 | extern int smp_hw_index[]; | |
94 | ||
336868af | 95 | #define raw_smp_processor_id() (current_thread_info()->cpu) |
5ad57078 | 96 | #define hard_smp_processor_id() (smp_hw_index[smp_processor_id()]) |
41eba0ad BH |
97 | |
98 | static inline int get_hard_smp_processor_id(int cpu) | |
99 | { | |
100 | return smp_hw_index[cpu]; | |
101 | } | |
102 | ||
103 | static inline void set_hard_smp_processor_id(int cpu, int phys) | |
104 | { | |
105 | smp_hw_index[cpu] = phys; | |
106 | } | |
5ad57078 | 107 | #endif |
1da177e4 | 108 | |
cc1ba8ea | 109 | DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_map); |
2a636a56 | 110 | DECLARE_PER_CPU(cpumask_var_t, cpu_l2_cache_map); |
cc1ba8ea | 111 | DECLARE_PER_CPU(cpumask_var_t, cpu_core_map); |
425752c6 | 112 | DECLARE_PER_CPU(cpumask_var_t, cpu_smallcore_map); |
cc1ba8ea AB |
113 | |
114 | static inline struct cpumask *cpu_sibling_mask(int cpu) | |
115 | { | |
116 | return per_cpu(cpu_sibling_map, cpu); | |
117 | } | |
118 | ||
c47f892d SD |
119 | static inline struct cpumask *cpu_core_mask(int cpu) |
120 | { | |
121 | return per_cpu(cpu_core_map, cpu); | |
122 | } | |
123 | ||
2a636a56 OH |
124 | static inline struct cpumask *cpu_l2_cache_mask(int cpu) |
125 | { | |
126 | return per_cpu(cpu_l2_cache_map, cpu); | |
127 | } | |
128 | ||
425752c6 GS |
129 | static inline struct cpumask *cpu_smallcore_mask(int cpu) |
130 | { | |
131 | return per_cpu(cpu_smallcore_map, cpu); | |
132 | } | |
133 | ||
e9efed3b | 134 | extern int cpu_to_core_id(int cpu); |
1da177e4 | 135 | |
f3232321 | 136 | extern bool has_big_cores; |
9538abee | 137 | extern bool thread_group_shares_l2; |
e9ef81e1 | 138 | extern bool thread_group_shares_l3; |
f3232321 SD |
139 | |
140 | #define cpu_smt_mask cpu_smt_mask | |
141 | #ifdef CONFIG_SCHED_SMT | |
142 | static inline const struct cpumask *cpu_smt_mask(int cpu) | |
143 | { | |
144 | if (has_big_cores) | |
145 | return per_cpu(cpu_smallcore_map, cpu); | |
146 | ||
147 | return per_cpu(cpu_sibling_map, cpu); | |
148 | } | |
149 | #endif /* CONFIG_SCHED_SMT */ | |
150 | ||
1da177e4 LT |
151 | /* Since OpenPIC has only 4 IPIs, we use slightly different message numbers. |
152 | * | |
153 | * Make sure this matches openpic_request_IPIs in open_pic.c, or what shows up | |
154 | * in /proc/interrupts will be wrong!!! --Troy */ | |
ddd703ca NP |
155 | #define PPC_MSG_CALL_FUNCTION 0 |
156 | #define PPC_MSG_RESCHEDULE 1 | |
1b67bee1 | 157 | #define PPC_MSG_TICK_BROADCAST 2 |
ddd703ca | 158 | #define PPC_MSG_NMI_IPI 3 |
1da177e4 | 159 | |
bd7f561f SW |
160 | /* This is only used by the powernv kernel */ |
161 | #define PPC_MSG_RM_HOST_ACTION 4 | |
162 | ||
ddd703ca NP |
163 | #define NMI_IPI_ALL_OTHERS -2 |
164 | ||
165 | #ifdef CONFIG_NMI_IPI | |
166 | extern int smp_handle_nmi_ipi(struct pt_regs *regs); | |
167 | #else | |
168 | static inline int smp_handle_nmi_ipi(struct pt_regs *regs) { return 0; } | |
169 | #endif | |
170 | ||
23d72bfd | 171 | /* for irq controllers that have dedicated ipis per message (4) */ |
25ddd738 MM |
172 | extern int smp_request_message_ipi(int virq, int message); |
173 | extern const char *smp_ipi_name[]; | |
174 | ||
23d72bfd | 175 | /* for irq controllers with only a single ipi */ |
23d72bfd | 176 | extern void smp_muxed_ipi_message_pass(int cpu, int msg); |
31639c77 | 177 | extern void smp_muxed_ipi_set_message(int cpu, int msg); |
23d72bfd | 178 | extern irqreturn_t smp_ipi_demux(void); |
b87ac021 | 179 | extern irqreturn_t smp_ipi_demux_relaxed(void); |
23d72bfd | 180 | |
1da177e4 | 181 | void smp_init_pSeries(void); |
19fe0475 | 182 | void smp_init_cell(void); |
5ad57078 | 183 | void smp_setup_cpu_maps(void); |
1da177e4 LT |
184 | |
185 | extern int __cpu_disable(void); | |
186 | extern void __cpu_die(unsigned int cpu); | |
5ad57078 PM |
187 | |
188 | #else | |
189 | /* for UP */ | |
78b5b626 | 190 | #define hard_smp_processor_id() get_hard_smp_processor_id(0) |
5ad57078 | 191 | #define smp_setup_cpu_maps() |
9538abee | 192 | #define thread_group_shares_l2 0 |
e9ef81e1 | 193 | #define thread_group_shares_l3 0 |
3be7db6a RJ |
194 | static inline const struct cpumask *cpu_sibling_mask(int cpu) |
195 | { | |
196 | return cpumask_of(cpu); | |
197 | } | |
5ad57078 | 198 | |
425752c6 GS |
199 | static inline const struct cpumask *cpu_smallcore_mask(int cpu) |
200 | { | |
201 | return cpumask_of(cpu); | |
202 | } | |
203 | ||
0be47634 GS |
204 | static inline const struct cpumask *cpu_l2_cache_mask(int cpu) |
205 | { | |
206 | return cpumask_of(cpu); | |
207 | } | |
1da177e4 LT |
208 | #endif /* CONFIG_SMP */ |
209 | ||
5ad57078 | 210 | #ifdef CONFIG_PPC64 |
41eba0ad BH |
211 | static inline int get_hard_smp_processor_id(int cpu) |
212 | { | |
d2e60075 | 213 | return paca_ptrs[cpu]->hw_cpu_id; |
41eba0ad BH |
214 | } |
215 | ||
216 | static inline void set_hard_smp_processor_id(int cpu, int phys) | |
217 | { | |
d2e60075 | 218 | paca_ptrs[cpu]->hw_cpu_id = phys; |
41eba0ad | 219 | } |
5ad57078 PM |
220 | #else |
221 | /* 32-bit */ | |
222 | #ifndef CONFIG_SMP | |
4df20460 | 223 | extern int boot_cpuid_phys; |
41eba0ad BH |
224 | static inline int get_hard_smp_processor_id(int cpu) |
225 | { | |
226 | return boot_cpuid_phys; | |
227 | } | |
228 | ||
229 | static inline void set_hard_smp_processor_id(int cpu, int phys) | |
230 | { | |
78b5b626 | 231 | boot_cpuid_phys = phys; |
41eba0ad BH |
232 | } |
233 | #endif /* !CONFIG_SMP */ | |
234 | #endif /* !CONFIG_PPC64 */ | |
1da177e4 | 235 | |
da665885 | 236 | #if defined(CONFIG_PPC64) && (defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)) |
b1923caa BH |
237 | extern void smp_release_cpus(void); |
238 | #else | |
6c6fdbb2 | 239 | static inline void smp_release_cpus(void) { } |
b1923caa BH |
240 | #endif |
241 | ||
1da177e4 LT |
242 | extern int smt_enabled_at_boot; |
243 | ||
a7f4ee1f | 244 | extern void smp_mpic_probe(void); |
1da177e4 | 245 | extern void smp_mpic_setup_cpu(int cpu); |
de300974 | 246 | extern int smp_generic_kick_cpu(int nr); |
3cd85250 AF |
247 | extern int smp_generic_cpu_bootable(unsigned int nr); |
248 | ||
1da177e4 LT |
249 | |
250 | extern void smp_generic_give_timebase(void); | |
251 | extern void smp_generic_take_timebase(void); | |
252 | ||
253 | extern struct smp_ops_t *smp_ops; | |
254 | ||
b7d7a240 | 255 | extern void arch_send_call_function_single_ipi(int cpu); |
f063ea02 | 256 | extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); |
b7d7a240 | 257 | |
cf54dc7c BH |
258 | /* Definitions relative to the secondary CPU spin loop |
259 | * and entry point. Not all of them exist on both 32 and | |
260 | * 64-bit but defining them all here doesn't harm | |
261 | */ | |
262 | extern void generic_secondary_smp_init(void); | |
263 | extern unsigned long __secondary_hold_spinloop; | |
264 | extern unsigned long __secondary_hold_acknowledge; | |
265 | extern char __secondary_hold; | |
6becef7e | 266 | extern unsigned int booting_thread_hwid; |
cf54dc7c | 267 | |
d0832a75 | 268 | extern void __early_start(void); |
1da177e4 LT |
269 | #endif /* __ASSEMBLY__ */ |
270 | ||
1da177e4 | 271 | #endif /* __KERNEL__ */ |
5ad57078 | 272 | #endif /* _ASM_POWERPC_SMP_H) */ |