powerpc: Merge 32-bit and 64-bit setup_arch()
[linux-2.6-block.git] / arch / powerpc / include / asm / smp.h
CommitLineData
1da177e4 1/*
5ad57078 2 * smp.h: PowerPC-specific SMP code.
1da177e4
LT
3 *
4 * Original was a copy of sparc smp.h. Now heavily modified
5 * for PPC.
6 *
7 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
8 * Copyright (C) 1996-2001 Cort Dougan <cort@fsmlabs.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
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16#ifndef _ASM_POWERPC_SMP_H
17#define _ASM_POWERPC_SMP_H
1da177e4 18#ifdef __KERNEL__
1da177e4 19
1da177e4
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20#include <linux/threads.h>
21#include <linux/cpumask.h>
22#include <linux/kernel.h>
23d72bfd 23#include <linux/irqreturn.h>
1da177e4
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24
25#ifndef __ASSEMBLY__
26
5ad57078 27#ifdef CONFIG_PPC64
1da177e4 28#include <asm/paca.h>
5ad57078 29#endif
d5a7430d 30#include <asm/percpu.h>
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31
32extern int boot_cpuid;
7ac87abb 33extern int spinning_secondaries;
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34
35extern void cpu_die(void);
3eb906c6 36extern int cpu_to_chip_id(int cpu);
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37
38#ifdef CONFIG_SMP
39
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40struct smp_ops_t {
41 void (*message_pass)(int cpu, int msg);
1ece355b 42#ifdef CONFIG_PPC_SMP_MUXED_IPI
23d72bfd 43 void (*cause_ipi)(int cpu, unsigned long data);
1ece355b 44#endif
a7f4ee1f 45 void (*probe)(void);
17f9c8a7
MM
46 int (*kick_cpu)(int nr);
47 void (*setup_cpu)(int nr);
48 void (*bringup_done)(void);
49 void (*take_timebase)(void);
50 void (*give_timebase)(void);
51 int (*cpu_disable)(void);
52 void (*cpu_die)(unsigned int nr);
53 int (*cpu_bootable)(unsigned int nr);
54};
55
e0476371 56extern void smp_send_debugger_break(void);
fa3f82c8 57extern void start_secondary_resume(void);
cad5cef6
GKH
58extern void smp_generic_give_timebase(void);
59extern void smp_generic_take_timebase(void);
1da177e4 60
6b7487fc 61DECLARE_PER_CPU(unsigned int, cpu_pvr);
1c21a293 62
1da177e4 63#ifdef CONFIG_HOTPLUG_CPU
1c91cc57 64extern void migrate_irqs(void);
1da177e4 65int generic_cpu_disable(void);
1da177e4 66void generic_cpu_die(unsigned int cpu);
105765f4 67void generic_set_cpu_dead(unsigned int cpu);
ae5cab47 68void generic_set_cpu_up(unsigned int cpu);
fb82b839 69int generic_check_cpu_restart(unsigned int cpu);
2f4f1f81 70int is_cpu_dead(unsigned int cpu);
71#else
72#define generic_set_cpu_up(i) do { } while (0)
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73#endif
74
5ad57078 75#ifdef CONFIG_PPC64
048c8bc9 76#define raw_smp_processor_id() (local_paca->paca_index)
1da177e4 77#define hard_smp_processor_id() (get_paca()->hw_cpu_id)
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78#else
79/* 32-bit */
80extern int smp_hw_index[];
81
82#define raw_smp_processor_id() (current_thread_info()->cpu)
83#define hard_smp_processor_id() (smp_hw_index[smp_processor_id()])
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84
85static inline int get_hard_smp_processor_id(int cpu)
86{
87 return smp_hw_index[cpu];
88}
89
90static inline void set_hard_smp_processor_id(int cpu, int phys)
91{
92 smp_hw_index[cpu] = phys;
93}
5ad57078 94#endif
1da177e4 95
cc1ba8ea
AB
96DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_map);
97DECLARE_PER_CPU(cpumask_var_t, cpu_core_map);
98
99static inline struct cpumask *cpu_sibling_mask(int cpu)
100{
101 return per_cpu(cpu_sibling_map, cpu);
102}
103
104static inline struct cpumask *cpu_core_mask(int cpu)
105{
106 return per_cpu(cpu_core_map, cpu);
107}
108
e9efed3b 109extern int cpu_to_core_id(int cpu);
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110
111/* Since OpenPIC has only 4 IPIs, we use slightly different message numbers.
112 *
113 * Make sure this matches openpic_request_IPIs in open_pic.c, or what shows up
114 * in /proc/interrupts will be wrong!!! --Troy */
115#define PPC_MSG_CALL_FUNCTION 0
116#define PPC_MSG_RESCHEDULE 1
1b67bee1 117#define PPC_MSG_TICK_BROADCAST 2
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118#define PPC_MSG_DEBUGGER_BREAK 3
119
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SW
120/* This is only used by the powernv kernel */
121#define PPC_MSG_RM_HOST_ACTION 4
122
23d72bfd 123/* for irq controllers that have dedicated ipis per message (4) */
25ddd738
MM
124extern int smp_request_message_ipi(int virq, int message);
125extern const char *smp_ipi_name[];
126
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127/* for irq controllers with only a single ipi */
128extern void smp_muxed_ipi_set_data(int cpu, unsigned long data);
129extern void smp_muxed_ipi_message_pass(int cpu, int msg);
31639c77 130extern void smp_muxed_ipi_set_message(int cpu, int msg);
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131extern irqreturn_t smp_ipi_demux(void);
132
1da177e4 133void smp_init_pSeries(void);
19fe0475 134void smp_init_cell(void);
5ad57078 135void smp_setup_cpu_maps(void);
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136
137extern int __cpu_disable(void);
138extern void __cpu_die(unsigned int cpu);
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139
140#else
141/* for UP */
78b5b626 142#define hard_smp_processor_id() get_hard_smp_processor_id(0)
5ad57078 143#define smp_setup_cpu_maps()
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144static inline void inhibit_secondary_onlining(void) {}
145static inline void uninhibit_secondary_onlining(void) {}
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RJ
146static inline const struct cpumask *cpu_sibling_mask(int cpu)
147{
148 return cpumask_of(cpu);
149}
5ad57078 150
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151#endif /* CONFIG_SMP */
152
5ad57078 153#ifdef CONFIG_PPC64
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154static inline int get_hard_smp_processor_id(int cpu)
155{
156 return paca[cpu].hw_cpu_id;
157}
158
159static inline void set_hard_smp_processor_id(int cpu, int phys)
160{
161 paca[cpu].hw_cpu_id = phys;
162}
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163#else
164/* 32-bit */
165#ifndef CONFIG_SMP
4df20460 166extern int boot_cpuid_phys;
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167static inline int get_hard_smp_processor_id(int cpu)
168{
169 return boot_cpuid_phys;
170}
171
172static inline void set_hard_smp_processor_id(int cpu, int phys)
173{
78b5b626 174 boot_cpuid_phys = phys;
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175}
176#endif /* !CONFIG_SMP */
177#endif /* !CONFIG_PPC64 */
1da177e4 178
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179#if defined(CONFIG_PPC64) && (defined(CONFIG_SMP) || defined(CONFIG_KEXEC))
180extern void smp_release_cpus(void);
181#else
182static inline void smp_release_cpus(void) { };
183#endif
184
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185extern int smt_enabled_at_boot;
186
a7f4ee1f 187extern void smp_mpic_probe(void);
1da177e4 188extern void smp_mpic_setup_cpu(int cpu);
de300974 189extern int smp_generic_kick_cpu(int nr);
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190extern int smp_generic_cpu_bootable(unsigned int nr);
191
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192
193extern void smp_generic_give_timebase(void);
194extern void smp_generic_take_timebase(void);
195
196extern struct smp_ops_t *smp_ops;
197
b7d7a240 198extern void arch_send_call_function_single_ipi(int cpu);
f063ea02 199extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
b7d7a240 200
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201/* Definitions relative to the secondary CPU spin loop
202 * and entry point. Not all of them exist on both 32 and
203 * 64-bit but defining them all here doesn't harm
204 */
205extern void generic_secondary_smp_init(void);
2d27cfd3 206extern void generic_secondary_thread_init(void);
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207extern unsigned long __secondary_hold_spinloop;
208extern unsigned long __secondary_hold_acknowledge;
209extern char __secondary_hold;
6becef7e 210extern unsigned int booting_thread_hwid;
cf54dc7c 211
d0832a75 212extern void __early_start(void);
1da177e4
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213#endif /* __ASSEMBLY__ */
214
1da177e4 215#endif /* __KERNEL__ */
5ad57078 216#endif /* _ASM_POWERPC_SMP_H) */