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9a868f63 ME |
1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | /* | |
3 | * Security related feature bit definitions. | |
4 | * | |
5 | * Copyright 2018, Michael Ellerman, IBM Corporation. | |
6 | */ | |
7 | ||
8 | #ifndef _ASM_POWERPC_SECURITY_FEATURES_H | |
9 | #define _ASM_POWERPC_SECURITY_FEATURES_H | |
10 | ||
11 | ||
12 | extern unsigned long powerpc_security_features; | |
13 | ||
14 | static inline void security_ftr_set(unsigned long feature) | |
15 | { | |
16 | powerpc_security_features |= feature; | |
17 | } | |
18 | ||
19 | static inline void security_ftr_clear(unsigned long feature) | |
20 | { | |
21 | powerpc_security_features &= ~feature; | |
22 | } | |
23 | ||
24 | static inline bool security_ftr_enabled(unsigned long feature) | |
25 | { | |
26 | return !!(powerpc_security_features & feature); | |
27 | } | |
28 | ||
29 | ||
30 | // Features indicating support for Spectre/Meltdown mitigations | |
31 | ||
32 | // The L1-D cache can be flushed with ori r30,r30,0 | |
33 | #define SEC_FTR_L1D_FLUSH_ORI30 0x0000000000000001ull | |
34 | ||
35 | // The L1-D cache can be flushed with mtspr 882,r0 (aka SPRN_TRIG2) | |
36 | #define SEC_FTR_L1D_FLUSH_TRIG2 0x0000000000000002ull | |
37 | ||
38 | // ori r31,r31,0 acts as a speculation barrier | |
39 | #define SEC_FTR_SPEC_BAR_ORI31 0x0000000000000004ull | |
40 | ||
41 | // Speculation past bctr is disabled | |
42 | #define SEC_FTR_BCCTRL_SERIALISED 0x0000000000000008ull | |
43 | ||
44 | // Entries in L1-D are private to a SMT thread | |
45 | #define SEC_FTR_L1D_THREAD_PRIV 0x0000000000000010ull | |
46 | ||
47 | // Indirect branch prediction cache disabled | |
48 | #define SEC_FTR_COUNT_CACHE_DISABLED 0x0000000000000020ull | |
49 | ||
50 | ||
51 | // Features indicating need for Spectre/Meltdown mitigations | |
52 | ||
53 | // The L1-D cache should be flushed on MSR[HV] 1->0 transition (hypervisor to guest) | |
54 | #define SEC_FTR_L1D_FLUSH_HV 0x0000000000000040ull | |
55 | ||
56 | // The L1-D cache should be flushed on MSR[PR] 0->1 transition (kernel to userspace) | |
57 | #define SEC_FTR_L1D_FLUSH_PR 0x0000000000000080ull | |
58 | ||
59 | // A speculation barrier should be used for bounds checks (Spectre variant 1) | |
60 | #define SEC_FTR_BNDS_CHK_SPEC_BAR 0x0000000000000100ull | |
61 | ||
62 | // Firmware configuration indicates user favours security over performance | |
63 | #define SEC_FTR_FAVOUR_SECURITY 0x0000000000000200ull | |
64 | ||
65 | #endif /* _ASM_POWERPC_SECURITY_FEATURES_H */ |