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powerpc/booke: Provide exception macros with interrupt name
[linux-block.git] / arch / powerpc / include / asm / reg.h
CommitLineData
14cf11af
PM		 1/*
2 * Contains the definition of registers common to all PowerPC variants.
3 * If a register definition has been changed in a different PowerPC
4 * variant, we will case it in #ifndef XXX ... #endif, and have the
5 * number used in the Programming Environments Manual For 32-Bit
6 * Implementations of the PowerPC Architecture (a.k.a. Green Book) here.
7 */
8
9f04b9e3
PM		 9#ifndef _ASM_POWERPC_REG_H
10#define _ASM_POWERPC_REG_H
14cf11af 11#ifdef __KERNEL__
14cf11af
PM		 12
13#include <linux/stringify.h>
9f04b9e3 14#include <asm/cputable.h>
14cf11af
PM		 15
16/* Pickup Book E specific registers. */
17#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
18#include <asm/reg_booke.h>
26ef5c09
DG		 19#endif /* CONFIG_BOOKE || CONFIG_40x */
20
39aef685
AF		 21#ifdef CONFIG_FSL_EMB_PERFMON
22#include <asm/reg_fsl_emb.h>
23#endif
24
26ef5c09
DG		 25#ifdef CONFIG_8xx
26#include <asm/reg_8xx.h>
27#endif /* CONFIG_8xx */
14cf11af 28
9f04b9e3
PM		 29#define MSR_SF_LG 63 /* Enable 64 bit mode */
30#define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */
31#define MSR_HV_LG 60 /* Hypervisor state */
32#define MSR_VEC_LG 25 /* Enable AltiVec */
ce48b210 33#define MSR_VSX_LG 23 /* Enable VSX */
9f04b9e3
PM		 34#define MSR_POW_LG 18 /* Enable Power Management */
35#define MSR_WE_LG 18 /* Wait State Enable */
36#define MSR_TGPR_LG 17 /* TLB Update registers in use */
37#define MSR_CE_LG 17 /* Critical Interrupt Enable */
38#define MSR_ILE_LG 16 /* Interrupt Little Endian */
39#define MSR_EE_LG 15 /* External Interrupt Enable */
40#define MSR_PR_LG 14 /* Problem State / Privilege Level */
41#define MSR_FP_LG 13 /* Floating Point enable */
42#define MSR_ME_LG 12 /* Machine Check Enable */
43#define MSR_FE0_LG 11 /* Floating Exception mode 0 */
44#define MSR_SE_LG 10 /* Single Step */
45#define MSR_BE_LG 9 /* Branch Trace */
46#define MSR_DE_LG 9 /* Debug Exception Enable */
47#define MSR_FE1_LG 8 /* Floating Exception mode 1 */
48#define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */
49#define MSR_IR_LG 5 /* Instruction Relocate */
50#define MSR_DR_LG 4 /* Data Relocate */
51#define MSR_PE_LG 3 /* Protection Enable */
52#define MSR_PX_LG 2 /* Protection Exclusive Mode */
53#define MSR_PMM_LG 2 /* Performance monitor */
54#define MSR_RI_LG 1 /* Recoverable Exception */
55#define MSR_LE_LG 0 /* Little Endian */
14cf11af 56
9f04b9e3
PM		 57#ifdef __ASSEMBLY__
58#define __MASK(X) (1<<(X))
59#else
60#define __MASK(X) (1UL<<(X))
61#endif
62
c032524f 63#ifdef CONFIG_PPC64
9f04b9e3
PM		 64#define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */
65#define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */
66#define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */
c032524f
PM		 67#else
68/* so tests for these bits fail on 32-bit */
69#define MSR_SF 0
70#define MSR_ISF 0
71#define MSR_HV 0
72#endif
73
9f04b9e3 74#define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */
ce48b210 75#define MSR_VSX __MASK(MSR_VSX_LG) /* Enable VSX */
9f04b9e3
PM		 76#define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */
77#define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */
78#define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */
79#define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */
80#define MSR_ILE __MASK(MSR_ILE_LG) /* Interrupt Little Endian */
81#define MSR_EE __MASK(MSR_EE_LG) /* External Interrupt Enable */
82#define MSR_PR __MASK(MSR_PR_LG) /* Problem State / Privilege Level */
83#define MSR_FP __MASK(MSR_FP_LG) /* Floating Point enable */
84#define MSR_ME __MASK(MSR_ME_LG) /* Machine Check Enable */
85#define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */
86#define MSR_SE __MASK(MSR_SE_LG) /* Single Step */
87#define MSR_BE __MASK(MSR_BE_LG) /* Branch Trace */
88#define MSR_DE __MASK(MSR_DE_LG) /* Debug Exception Enable */
89#define MSR_FE1 __MASK(MSR_FE1_LG) /* Floating Exception mode 1 */
90#define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */
91#define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */
92#define MSR_DR __MASK(MSR_DR_LG) /* Data Relocate */
93#define MSR_PE __MASK(MSR_PE_LG) /* Protection Enable */
94#define MSR_PX __MASK(MSR_PX_LG) /* Protection Exclusive Mode */
fd582ec8 95#ifndef MSR_PMM
9f04b9e3 96#define MSR_PMM __MASK(MSR_PMM_LG) /* Performance monitor */
fd582ec8 97#endif
9f04b9e3
PM		 98#define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */
99#define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */
100
0257c99c 101#if defined(CONFIG_PPC_BOOK3S_64)
9d4a2925
ME		 102#define MSR_64BIT MSR_SF
103
0257c99c 104/* Server variant */
9e6e3c2c 105#define MSR_ MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV
9d4a2925 106#define MSR_KERNEL MSR_ | MSR_64BIT
9f04b9e3 107#define MSR_USER32 MSR_ | MSR_PR | MSR_EE
9d4a2925 108#define MSR_USER64 MSR_USER32 | MSR_64BIT
0257c99c 109#elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_8xx)
14cf11af 110/* Default MSR for kernel mode. */
14cf11af 111#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
14cf11af 112#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
9f04b9e3 113#endif
14cf11af 114
9d4a2925
ME		 115#ifndef MSR_64BIT
116#define MSR_64BIT 0
117#endif
118
14cf11af
PM		 119/* Floating Point Status and Control Register (FPSCR) Fields */
120#define FPSCR_FX 0x80000000 /* FPU exception summary */
121#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
122#define FPSCR_VX 0x20000000 /* Invalid operation summary */
123#define FPSCR_OX 0x10000000 /* Overflow exception summary */
124#define FPSCR_UX 0x08000000 /* Underflow exception summary */
125#define FPSCR_ZX 0x04000000 /* Zero-divide exception summary */
126#define FPSCR_XX 0x02000000 /* Inexact exception summary */
127#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
128#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
129#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
130#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
131#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
132#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
133#define FPSCR_FR 0x00040000 /* Fraction rounded */
134#define FPSCR_FI 0x00020000 /* Fraction inexact */
135#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
136#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
137#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
138#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
139#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
140#define FPSCR_VE 0x00000080 /* Invalid op exception enable */
141#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
142#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
143#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
144#define FPSCR_XE 0x00000008 /* FP inexact exception enable */
145#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
146#define FPSCR_RN 0x00000003 /* FPU rounding control */
147
39fd0932
KG		 148/* Bit definitions for SPEFSCR. */
149#define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */
150#define SPEFSCR_OVH 0x40000000 /* Integer overflow high */
151#define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */
152#define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */
153#define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */
154#define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */
155#define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */
156#define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */
157#define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */
158#define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */
159#define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */
160#define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */
161#define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */
162#define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */
163#define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */
164#define SPEFSCR_OV 0x00004000 /* Integer overflow */
165#define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */
166#define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */
167#define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */
168#define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */
169#define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */
170#define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */
171#define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */
172#define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */
173#define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */
174#define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */
175#define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */
176#define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */
177
14cf11af 178/* Special Purpose Registers (SPRNs)*/
6edc642e
THFL		 179
180#ifdef CONFIG_40x
181#define SPRN_PID 0x3B1 /* Process ID */
182#else
183#define SPRN_PID 0x030 /* Process ID */
184#ifdef CONFIG_BOOKE
185#define SPRN_PID0 SPRN_PID/* Process ID Register 0 */
186#endif
187#endif
188
14cf11af 189#define SPRN_CTR 0x009 /* Count Register */
4c198557 190#define SPRN_DSCR 0x11
48404f2e 191#define SPRN_CFAR 0x1c /* Come From Address Register */
de56a948
PM		 192#define SPRN_AMR 0x1d /* Authority Mask Register */
193#define SPRN_UAMOR 0x9d /* User Authority Mask Override Register */
194#define SPRN_AMOR 0x15d /* Authority Mask Override Register */
851d2e2f 195#define SPRN_ACOP 0x1F /* Available Coprocessor Register */
9f04b9e3
PM		 196#define SPRN_CTRLF 0x088
197#define SPRN_CTRLT 0x098
c902be71
AB		 198#define CTRL_CT 0xc0000000 /* current thread */
199#define CTRL_CT0 0x80000000 /* thread 0 */
200#define CTRL_CT1 0x40000000 /* thread 1 */
201#define CTRL_TE 0x00c00000 /* thread enable */
9f04b9e3 202#define CTRL_RUNLATCH 0x1
14cf11af
PM		 203#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
204#define DABR_TRANSLATION (1UL << 2)
c9c38320
GL		 205#define DABR_DATA_WRITE (1UL << 1)
206#define DABR_DATA_READ (1UL << 0)
d49747bd 207#define SPRN_DABR2 0x13D /* e300 */
9176c0b1
JO		 208#define SPRN_DABRX 0x3F7 /* Data Address Breakpoint Register Extension */
209#define DABRX_USER (1UL << 0)
210#define DABRX_KERNEL (1UL << 1)
14cf11af 211#define SPRN_DAR 0x013 /* Data Address Register */
d49747bd 212#define SPRN_DBCR 0x136 /* e300 Data Breakpoint Control Reg */
d6b89a19 213#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
14cf11af
PM		 214#define DSISR_NOHPTE 0x40000000 /* no translation found */
215#define DSISR_PROTFAULT 0x08000000 /* protection fault */
216#define DSISR_ISSTORE 0x02000000 /* access was a store */
217#define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */
218#define DSISR_NOSEGMENT 0x00200000 /* STAB/SLB miss */
697d3899 219#define DSISR_KEYFAULT 0x00200000 /* Key fault */
14cf11af
PM		 220#define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */
221#define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */
222#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */
223#define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */
f050982a 224#define SPRN_SPURR 0x134 /* Scaled PURR */
50fb8ebe
BH		 225#define SPRN_HSPRG0 0x130 /* Hypervisor Scratch 0 */
226#define SPRN_HSPRG1 0x131 /* Hypervisor Scratch 1 */
227#define SPRN_HDSISR 0x132
228#define SPRN_HDAR 0x133
229#define SPRN_HDEC 0x136 /* Hypervisor Decrementer */
14cf11af 230#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */
50fb8ebe
BH		 231#define SPRN_RMOR 0x138 /* Real mode offset register */
232#define SPRN_HRMOR 0x139 /* Real mode offset register */
233#define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */
234#define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */
1199919b 235#define SPRN_LPCR 0x13E /* LPAR Control Register */
50fb8ebe
BH		 236#define LPCR_VPM0 (1ul << (63-0))
237#define LPCR_VPM1 (1ul << (63-1))
238#define LPCR_ISL (1ul << (63-2))
923c53ca 239#define LPCR_VC_SH (63-2)
50fb8ebe 240#define LPCR_DPFD_SH (63-11)
da9d1d7f 241#define LPCR_VRMASD (0x1ful << (63-16))
50fb8ebe
BH		 242#define LPCR_VRMA_L (1ul << (63-12))
243#define LPCR_VRMA_LP0 (1ul << (63-15))
244#define LPCR_VRMA_LP1 (1ul << (63-16))
923c53ca 245#define LPCR_VRMASD_SH (63-16)
50fb8ebe 246#define LPCR_RMLS 0x1C000000 /* impl dependent rmo limit sel */
aa04b4cc 247#define LPCR_RMLS_SH (63-37)
50fb8ebe
BH		 248#define LPCR_ILE 0x02000000 /* !HV irqs set MSR:LE */
249#define LPCR_PECE 0x00007000 /* powersave exit cause enable */
250#define LPCR_PECE0 0x00004000 /* ext. exceptions can cause exit */
251#define LPCR_PECE1 0x00002000 /* decrementer can cause exit */
252#define LPCR_PECE2 0x00001000 /* machine check etc can cause exit */
253#define LPCR_MER 0x00000800 /* Mediated External Exception */
923c53ca 254#define LPCR_LPES 0x0000000c
50fb8ebe
BH		 255#define LPCR_LPES0 0x00000008 /* LPAR Env selector 0 */
256#define LPCR_LPES1 0x00000004 /* LPAR Env selector 1 */
923c53ca 257#define LPCR_LPES_SH 2
50fb8ebe
BH		 258#define LPCR_RMI 0x00000002 /* real mode is cache inhibit */
259#define LPCR_HDICE 0x00000001 /* Hyp Decr enable (HV,PR,EE) */
260#define SPRN_LPID 0x13F /* Logical Partition Identifier */
de56a948 261#define LPID_RSVD 0x3ff /* Reserved LPID for partn switching */
50fb8ebe
BH		 262#define SPRN_HMER 0x150 /* Hardware m? error recovery */
263#define SPRN_HMEER 0x151 /* Hardware m? enable error recovery */
264#define SPRN_HEIR 0x153 /* Hypervisor Emulated Instruction Register */
265#define SPRN_TLBINDEXR 0x154 /* P7 TLB control register */
266#define SPRN_TLBVPNR 0x155 /* P7 TLB control register */
267#define SPRN_TLBRPNR 0x156 /* P7 TLB control register */
268#define SPRN_TLBLPIDR 0x157 /* P7 TLB control register */
14cf11af
PM		 269#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
270#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
271#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
272#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
273#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
274#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
275#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
276#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
277#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
278#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
279#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
280#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
281#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
282#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
283#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
284#define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */
285
286#define SPRN_DEC 0x016 /* Decrement Register */
287#define SPRN_DER 0x095 /* Debug Enable Regsiter */
288#define DER_RSTE 0x40000000 /* Reset Interrupt */
289#define DER_CHSTPE 0x20000000 /* Check Stop */
290#define DER_MCIE 0x10000000 /* Machine Check Interrupt */
291#define DER_EXTIE 0x02000000 /* External Interrupt */
292#define DER_ALIE 0x01000000 /* Alignment Interrupt */
293#define DER_PRIE 0x00800000 /* Program Interrupt */
294#define DER_FPUVIE 0x00400000 /* FP Unavailable Interrupt */
295#define DER_DECIE 0x00200000 /* Decrementer Interrupt */
296#define DER_SYSIE 0x00040000 /* System Call Interrupt */
297#define DER_TRE 0x00020000 /* Trace Interrupt */
298#define DER_SEIE 0x00004000 /* FP SW Emulation Interrupt */
299#define DER_ITLBMSE 0x00002000 /* Imp. Spec. Instruction TLB Miss */
300#define DER_ITLBERE 0x00001000 /* Imp. Spec. Instruction TLB Error */
301#define DER_DTLBMSE 0x00000800 /* Imp. Spec. Data TLB Miss */
302#define DER_DTLBERE 0x00000400 /* Imp. Spec. Data TLB Error */
303#define DER_LBRKE 0x00000008 /* Load/Store Breakpoint Interrupt */
304#define DER_IBRKE 0x00000004 /* Instruction Breakpoint Interrupt */
305#define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */
306#define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */
307#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
308#define SPRN_EAR 0x11A /* External Address Register */
309#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
310#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
311#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
969391c5 312#define HID0_HDICE_SH (63 - 23) /* 970 HDEC interrupt enable */
14cf11af
PM		 313#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
314#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
315#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
316#define HID0_SBCLK (1<<27)
317#define HID0_EICE (1<<26)
318#define HID0_TBEN (1<<26) /* Timebase enable - 745x */
319#define HID0_ECLK (1<<25)
320#define HID0_PAR (1<<24)
321#define HID0_STEN (1<<24) /* Software table search enable - 745x */
322#define HID0_HIGH_BAT (1<<23) /* Enable high BATs - 7455 */
323#define HID0_DOZE (1<<23)
324#define HID0_NAP (1<<22)
325#define HID0_SLEEP (1<<21)
326#define HID0_DPM (1<<20)
327#define HID0_BHTCLR (1<<18) /* Clear branch history table - 7450 */
328#define HID0_XAEN (1<<17) /* Extended addressing enable - 7450 */
329#define HID0_NHR (1<<16) /* Not hard reset (software bit-7450)*/
330#define HID0_ICE (1<<15) /* Instruction Cache Enable */
331#define HID0_DCE (1<<14) /* Data Cache Enable */
332#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
333#define HID0_DLOCK (1<<12) /* Data Cache Lock */
334#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
335#define HID0_DCI (1<<10) /* Data Cache Invalidate */
336#define HID0_SPD (1<<9) /* Speculative disable */
337#define HID0_DAPUEN (1<<8) /* Debug APU enable */
338#define HID0_SGE (1<<7) /* Store Gathering Enable */
339#define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */
fc4033b2 340#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
14cf11af
PM		 341#define HID0_LRSTK (1<<4) /* Link register stack - 745x */
342#define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */
343#define HID0_ABE (1<<3) /* Address Broadcast Enable */
344#define HID0_FOLD (1<<3) /* Branch Folding enable - 745x */
345#define HID0_BHTE (1<<2) /* Branch History Table Enable */
346#define HID0_BTCD (1<<1) /* Branch target cache disable */
347#define HID0_NOPDST (1<<1) /* No-op dst, dstt, etc. instr. */
348#define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */
349
350#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
86985db6 351#ifdef CONFIG_6xx
14cf11af
PM		 352#define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */
353#define HID1_DFS (1<<22) /* 7447A Dynamic Frequency Scaling */
354#define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */
355#define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */
356#define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */
357#define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */
358#define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */
359#define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */
360#define HID1_PS (1<<16) /* 750FX PLL selection */
86985db6 361#endif
14cf11af 362#define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */
d6d549b2 363#define SPRN_HID2_GEKKO 0x398 /* Gekko HID2 Register */
14cf11af 364#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
d49747bd
SW		 365#define SPRN_IABR2 0x3FA /* 83xx */
366#define SPRN_IBCR 0x135 /* 83xx Insn Breakpoint Control Reg */
14cf11af 367#define SPRN_HID4 0x3F4 /* 970 HID4 */
969391c5
PM		 368#define HID4_LPES0 (1ul << (63-0)) /* LPAR env. sel. bit 0 */
369#define HID4_RMLS2_SH (63 - 2) /* Real mode limit bottom 2 bits */
370#define HID4_LPID5_SH (63 - 6) /* partition ID bottom 4 bits */
371#define HID4_RMOR_SH (63 - 22) /* real mode offset (16 bits) */
372#define HID4_LPES1 (1 << (63-57)) /* LPAR env. sel. bit 1 */
373#define HID4_RMLS0_SH (63 - 58) /* Real mode limit top bit */
374#define HID4_LPID1_SH 0 /* partition ID top 2 bits */
d6d549b2 375#define SPRN_HID4_GEKKO 0x3F3 /* Gekko HID4 */
14cf11af 376#define SPRN_HID5 0x3F6 /* 970 HID5 */
d6b89a19
MN		 377#define SPRN_HID6 0x3F9 /* BE HID 6 */
378#define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */
379#define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */
380#define SPRN_TSC_CELL 0x399 /* Thread switch control on Cell */
381#define TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */
382#define TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */
383#define TSC_CELL_EE_ENABLE 0x100000 /* External Interrupt */
384#define TSC_CELL_EE_BOOST 0x080000 /* External Interrupt Boost */
385#define SPRN_TSC 0x3FD /* Thread switch control on others */
386#define SPRN_TST 0x3FC /* Thread switch timeout on others */
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PM		 387#if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
388#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
389#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
390#endif
391#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
392#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
393#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
394#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
395#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
396#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
397#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
398#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
399#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
400#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
401#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
402#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
403#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
404#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
405#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
406#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
407#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
408#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
409#define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */
410#define ICTRL_EICE 0x08000000 /* enable icache parity errs */
411#define ICTRL_EDC 0x04000000 /* enable dcache parity errs */
412#define ICTRL_EICP 0x00000100 /* enable icache par. check */
413#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
414#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
415#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
416#define SPRN_L2CR2 0x3f8
417#define L2CR_L2E 0x80000000 /* L2 enable */
418#define L2CR_L2PE 0x40000000 /* L2 parity enable */
419#define L2CR_L2SIZ_MASK 0x30000000 /* L2 size mask */
420#define L2CR_L2SIZ_256KB 0x10000000 /* L2 size 256KB */
421#define L2CR_L2SIZ_512KB 0x20000000 /* L2 size 512KB */
422#define L2CR_L2SIZ_1MB 0x30000000 /* L2 size 1MB */
423#define L2CR_L2CLK_MASK 0x0e000000 /* L2 clock mask */
424#define L2CR_L2CLK_DISABLED 0x00000000 /* L2 clock disabled */
425#define L2CR_L2CLK_DIV1 0x02000000 /* L2 clock / 1 */
426#define L2CR_L2CLK_DIV1_5 0x04000000 /* L2 clock / 1.5 */
427#define L2CR_L2CLK_DIV2 0x08000000 /* L2 clock / 2 */
428#define L2CR_L2CLK_DIV2_5 0x0a000000 /* L2 clock / 2.5 */
429#define L2CR_L2CLK_DIV3 0x0c000000 /* L2 clock / 3 */
430#define L2CR_L2RAM_MASK 0x01800000 /* L2 RAM type mask */
431#define L2CR_L2RAM_FLOW 0x00000000 /* L2 RAM flow through */
432#define L2CR_L2RAM_PIPE 0x01000000 /* L2 RAM pipelined */
433#define L2CR_L2RAM_PIPE_LW 0x01800000 /* L2 RAM pipelined latewr */
434#define L2CR_L2DO 0x00400000 /* L2 data only */
435#define L2CR_L2I 0x00200000 /* L2 global invalidate */
436#define L2CR_L2CTL 0x00100000 /* L2 RAM control */
437#define L2CR_L2WT 0x00080000 /* L2 write-through */
438#define L2CR_L2TS 0x00040000 /* L2 test support */
439#define L2CR_L2OH_MASK 0x00030000 /* L2 output hold mask */
440#define L2CR_L2OH_0_5 0x00000000 /* L2 output hold 0.5 ns */
441#define L2CR_L2OH_1_0 0x00010000 /* L2 output hold 1.0 ns */
442#define L2CR_L2SL 0x00008000 /* L2 DLL slow */
443#define L2CR_L2DF 0x00004000 /* L2 differential clock */
444#define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */
445#define L2CR_L2IP 0x00000001 /* L2 GI in progress */
446#define L2CR_L2IO_745x 0x00100000 /* L2 instr. only (745x) */
447#define L2CR_L2DO_745x 0x00010000 /* L2 data only (745x) */
448#define L2CR_L2REP_745x 0x00001000 /* L2 repl. algorithm (745x) */
449#define L2CR_L2HWF_745x 0x00000800 /* L2 hardware flush (745x) */
450#define SPRN_L3CR 0x3FA /* Level 3 Cache Control Regsiter */
451#define L3CR_L3E 0x80000000 /* L3 enable */
452#define L3CR_L3PE 0x40000000 /* L3 data parity enable */
453#define L3CR_L3APE 0x20000000 /* L3 addr parity enable */
454#define L3CR_L3SIZ 0x10000000 /* L3 size */
455#define L3CR_L3CLKEN 0x08000000 /* L3 clock enable */
456#define L3CR_L3RES 0x04000000 /* L3 special reserved bit */
457#define L3CR_L3CLKDIV 0x03800000 /* L3 clock divisor */
458#define L3CR_L3IO 0x00400000 /* L3 instruction only */
459#define L3CR_L3SPO 0x00040000 /* L3 sample point override */
460#define L3CR_L3CKSP 0x00030000 /* L3 clock sample point */
461#define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */
462#define L3CR_L3REP 0x00001000 /* L3 replacement algorithm */
463#define L3CR_L3HWF 0x00000800 /* L3 hardware flush */
464#define L3CR_L3I 0x00000400 /* L3 global invalidate */
465#define L3CR_L3RT 0x00000300 /* L3 SRAM type */
466#define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */
467#define L3CR_L3DO 0x00000040 /* L3 data only mode */
468#define L3CR_PMEN 0x00000004 /* L3 private memory enable */
469#define L3CR_PMSIZ 0x00000001 /* L3 private memory size */
9f04b9e3 470
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PM		 471#define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */
472#define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */
473#define SPRN_LDSTCR 0x3f8 /* Load/Store control register */
474#define SPRN_LDSTDB 0x3f4 /* */
475#define SPRN_LR 0x008 /* Link Register */
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PM		 476#ifndef SPRN_PIR
477#define SPRN_PIR 0x3FF /* Processor Identification Register */
478#endif
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PM		 479#define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */
480#define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */
d6b89a19 481#define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */
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PM		 482#define SPRN_PVR 0x11F /* Processor Version Register */
483#define SPRN_RPA 0x3D6 /* Required Physical Address Register */
484#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
485#define SPRN_SDR1 0x019 /* MMU Hash Base Register */
799d6046 486#define SPRN_ASR 0x118 /* Address Space Register */
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PM		 487#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
488#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
489#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
490#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
491#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
492#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
493#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
494#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
495#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
496#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
497#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
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PM		 498#define SRR1_ISI_NOPT 0x40000000 /* ISI: Not found in hash */
499#define SRR1_ISI_N_OR_G 0x10000000 /* ISI: Access is no-exec or G */
500#define SRR1_ISI_PROT 0x08000000 /* ISI: Other protection fault */
c902be71 501#define SRR1_WAKEMASK 0x00380000 /* reason for wakeup */
c902be71
AB		 502#define SRR1_WAKESYSERR 0x00300000 /* System error */
503#define SRR1_WAKEEE 0x00200000 /* External interrupt */
504#define SRR1_WAKEMT 0x00280000 /* mtctrl */
50fb8ebe 505#define SRR1_WAKEHMI 0x00280000 /* Hypervisor maintenance */
c902be71
AB		 506#define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */
507#define SRR1_WAKETHERM 0x00100000 /* Thermal management interrupt */
50fb8ebe
BH		 508#define SRR1_WAKERESET 0x00100000 /* System reset */
509#define SRR1_WAKESTATE 0x00030000 /* Powersave exit mask [46:47] */
510#define SRR1_WS_DEEPEST 0x00030000 /* Some resources not maintained,
511 * may not be recoverable */
512#define SRR1_WS_DEEPER 0x00020000 /* Some resources not maintained */
513#define SRR1_WS_DEEP 0x00010000 /* All resources maintained */
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AG		 514#define SRR1_PROGFPE 0x00100000 /* Floating Point Enabled */
515#define SRR1_PROGPRIV 0x00040000 /* Privileged instruction */
516#define SRR1_PROGTRAP 0x00020000 /* Trap */
517#define SRR1_PROGADDR 0x00010000 /* SRR0 contains subsequent addr */
50fb8ebe 518
acf7d768
BH		 519#define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */
520#define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */
c902be71 521
c388cfeb
OJ		 522#define SPRN_TBCTL 0x35f /* PA6T Timebase control register */
523#define TBCTL_FREEZE 0x0000000000000000ull /* Freeze all tbs */
524#define TBCTL_RESTART 0x0000000100000000ull /* Restart all tbs */
525#define TBCTL_UPDATE_UPPER 0x0000000200000000ull /* Set upper 32 bits */
526#define TBCTL_UPDATE_LOWER 0x0000000300000000ull /* Set lower 32 bits */
527
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PM		 528#ifndef SPRN_SVR
529#define SPRN_SVR 0x11E /* System Version Register */
530#endif
531#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
532/* these bits were defined in inverted endian sense originally, ugh, confusing */
533#define THRM1_TIN (1 << 31)
534#define THRM1_TIV (1 << 30)
535#define THRM1_THRES(x) ((x&0x7f)<<23)
536#define THRM3_SITV(x) ((x&0x3fff)<<1)
537#define THRM1_TID (1<<2)
538#define THRM1_TIE (1<<1)
539#define THRM1_V (1<<0)
540#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
541#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
542#define THRM3_E (1<<0)
543#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
544#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
545#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
546#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
547#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
548#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
549#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
550#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
551#define SPRN_VRSAVE 0x100 /* Vector Register Save Register */
552#define SPRN_XER 0x001 /* Fixed Point Exception Register */
553
d6d549b2
AG		 554#define SPRN_MMCR0_GEKKO 0x3B8 /* Gekko Monitor Mode Control Register 0 */
555#define SPRN_MMCR1_GEKKO 0x3BC /* Gekko Monitor Mode Control Register 1 */
556#define SPRN_PMC1_GEKKO 0x3B9 /* Gekko Performance Monitor Control 1 */
557#define SPRN_PMC2_GEKKO 0x3BA /* Gekko Performance Monitor Control 2 */
558#define SPRN_PMC3_GEKKO 0x3BD /* Gekko Performance Monitor Control 3 */
559#define SPRN_PMC4_GEKKO 0x3BE /* Gekko Performance Monitor Control 4 */
560#define SPRN_WPAR_GEKKO 0x399 /* Gekko Write Pipe Address Register */
561
4350147a
BH		 562#define SPRN_SCOMC 0x114 /* SCOM Access Control */
563#define SPRN_SCOMD 0x115 /* SCOM Access DATA */
564
9f04b9e3
PM		 565/* Performance monitor SPRs */
566#ifdef CONFIG_PPC64
567#define SPRN_MMCR0 795
568#define MMCR0_FC 0x80000000UL /* freeze counters */
569#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
570#define MMCR0_KERNEL_DISABLE MMCR0_FCS
571#define MMCR0_FCP 0x20000000UL /* freeze in problem state */
572#define MMCR0_PROBLEM_DISABLE MMCR0_FCP
573#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
574#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
575#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
576#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */
577#define MMCR0_TBEE 0x00400000UL /* time base exception enable */
578#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
579#define MMCR0_PMCjCE 0x00004000UL /* PMCj count enable*/
580#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
581#define MMCR0_PMAO 0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */
582#define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */
583#define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */
584#define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */
585#define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */
586#define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */
587#define SPRN_MMCR1 798
588#define SPRN_MMCRA 0x312
0bbd0d4b 589#define MMCRA_SDSYNC 0x80000000UL /* SDAR synced with SIAR */
81cd5ae3
AB		 590#define MMCRA_SDAR_DCACHE_MISS 0x40000000UL
591#define MMCRA_SDAR_ERAT_MISS 0x20000000UL
9f04b9e3
PM		 592#define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */
593#define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */
078f1940 594#define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */
595#define MMCRA_SLOT_SHIFT 24
9f04b9e3 596#define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
0bbd0d4b 597#define POWER6_MMCRA_SDSYNC 0x0000080000000000ULL /* SDAR/SIAR synced */
e78dbc80
MN		 598#define POWER6_MMCRA_SIHV 0x0000040000000000ULL
599#define POWER6_MMCRA_SIPR 0x0000020000000000ULL
600#define POWER6_MMCRA_THRM 0x00000020UL
601#define POWER6_MMCRA_OTHER 0x0000000EUL
9f04b9e3
PM		 602#define SPRN_PMC1 787
603#define SPRN_PMC2 788
604#define SPRN_PMC3 789
605#define SPRN_PMC4 790
606#define SPRN_PMC5 791
607#define SPRN_PMC6 792
608#define SPRN_PMC7 793
609#define SPRN_PMC8 794
610#define SPRN_SIAR 780
611#define SPRN_SDAR 781
612
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OJ		 613#define SPRN_PA6T_MMCR0 795
614#define PA6T_MMCR0_EN0 0x0000000000000001UL
615#define PA6T_MMCR0_EN1 0x0000000000000002UL
616#define PA6T_MMCR0_EN2 0x0000000000000004UL
617#define PA6T_MMCR0_EN3 0x0000000000000008UL
618#define PA6T_MMCR0_EN4 0x0000000000000010UL
619#define PA6T_MMCR0_EN5 0x0000000000000020UL
620#define PA6T_MMCR0_SUPEN 0x0000000000000040UL
621#define PA6T_MMCR0_PREN 0x0000000000000080UL
622#define PA6T_MMCR0_HYPEN 0x0000000000000100UL
623#define PA6T_MMCR0_FCM0 0x0000000000000200UL
624#define PA6T_MMCR0_FCM1 0x0000000000000400UL
625#define PA6T_MMCR0_INTGEN 0x0000000000000800UL
626#define PA6T_MMCR0_INTEN0 0x0000000000001000UL
627#define PA6T_MMCR0_INTEN1 0x0000000000002000UL
628#define PA6T_MMCR0_INTEN2 0x0000000000004000UL
629#define PA6T_MMCR0_INTEN3 0x0000000000008000UL
630#define PA6T_MMCR0_INTEN4 0x0000000000010000UL
631#define PA6T_MMCR0_INTEN5 0x0000000000020000UL
632#define PA6T_MMCR0_DISCNT 0x0000000000040000UL
633#define PA6T_MMCR0_UOP 0x0000000000080000UL
634#define PA6T_MMCR0_TRG 0x0000000000100000UL
635#define PA6T_MMCR0_TRGEN 0x0000000000200000UL
636#define PA6T_MMCR0_TRGREG 0x0000000001600000UL
637#define PA6T_MMCR0_SIARLOG 0x0000000002000000UL
638#define PA6T_MMCR0_SDARLOG 0x0000000004000000UL
639#define PA6T_MMCR0_PROEN 0x0000000008000000UL
640#define PA6T_MMCR0_PROLOG 0x0000000010000000UL
641#define PA6T_MMCR0_DAMEN2 0x0000000020000000UL
642#define PA6T_MMCR0_DAMEN3 0x0000000040000000UL
643#define PA6T_MMCR0_DAMEN4 0x0000000080000000UL
644#define PA6T_MMCR0_DAMEN5 0x0000000100000000UL
645#define PA6T_MMCR0_DAMSEL2 0x0000000200000000UL
646#define PA6T_MMCR0_DAMSEL3 0x0000000400000000UL
647#define PA6T_MMCR0_DAMSEL4 0x0000000800000000UL
648#define PA6T_MMCR0_DAMSEL5 0x0000001000000000UL
649#define PA6T_MMCR0_HANDDIS 0x0000002000000000UL
650#define PA6T_MMCR0_PCTEN 0x0000004000000000UL
651#define PA6T_MMCR0_SOCEN 0x0000008000000000UL
652#define PA6T_MMCR0_SOCMOD 0x0000010000000000UL
653
654#define SPRN_PA6T_MMCR1 798
655#define PA6T_MMCR1_ES2 0x00000000000000ffUL
656#define PA6T_MMCR1_ES3 0x000000000000ff00UL
657#define PA6T_MMCR1_ES4 0x0000000000ff0000UL
658#define PA6T_MMCR1_ES5 0x00000000ff000000UL
659
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OJ		 660#define SPRN_PA6T_UPMC0 771 /* User PerfMon Counter 0 */
661#define SPRN_PA6T_UPMC1 772 /* ... */
25fc530e
OJ		 662#define SPRN_PA6T_UPMC2 773
663#define SPRN_PA6T_UPMC3 774
664#define SPRN_PA6T_UPMC4 775
665#define SPRN_PA6T_UPMC5 776
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OJ		 666#define SPRN_PA6T_UMMCR0 779 /* User Monitor Mode Control Register 0 */
667#define SPRN_PA6T_SIAR 780 /* Sampled Instruction Address */
668#define SPRN_PA6T_UMMCR1 782 /* User Monitor Mode Control Register 1 */
669#define SPRN_PA6T_SIER 785 /* Sampled Instruction Event Register */
670#define SPRN_PA6T_PMC0 787
671#define SPRN_PA6T_PMC1 788
672#define SPRN_PA6T_PMC2 789
673#define SPRN_PA6T_PMC3 790
674#define SPRN_PA6T_PMC4 791
675#define SPRN_PA6T_PMC5 792
676#define SPRN_PA6T_TSR0 793 /* Timestamp Register 0 */
677#define SPRN_PA6T_TSR1 794 /* Timestamp Register 1 */
678#define SPRN_PA6T_TSR2 799 /* Timestamp Register 2 */
679#define SPRN_PA6T_TSR3 784 /* Timestamp Register 3 */
680
681#define SPRN_PA6T_IER 981 /* Icache Error Register */
682#define SPRN_PA6T_DER 982 /* Dcache Error Register */
683#define SPRN_PA6T_BER 862 /* BIU Error Address Register */
684#define SPRN_PA6T_MER 849 /* MMU Error Register */
685
686#define SPRN_PA6T_IMA0 880 /* Instruction Match Array 0 */
687#define SPRN_PA6T_IMA1 881 /* ... */
688#define SPRN_PA6T_IMA2 882
689#define SPRN_PA6T_IMA3 883
690#define SPRN_PA6T_IMA4 884
691#define SPRN_PA6T_IMA5 885
692#define SPRN_PA6T_IMA6 886
693#define SPRN_PA6T_IMA7 887
694#define SPRN_PA6T_IMA8 888
695#define SPRN_PA6T_IMA9 889
696#define SPRN_PA6T_BTCR 978 /* Breakpoint and Tagging Control Register */
697#define SPRN_PA6T_IMAAT 979 /* Instruction Match Array Action Table */
698#define SPRN_PA6T_PCCR 1019 /* Power Counter Control Register */
cda563fb 699#define SPRN_BKMK 1020 /* Cell Bookmark Register */
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OJ		 700#define SPRN_PA6T_RPCCR 1021 /* Retire PC Trace Control Register */
701
6529c13d 702
9f04b9e3 703#else /* 32-bit */
555d97ac
AF		 704#define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */
705#define MMCR0_FC 0x80000000UL /* freeze counters */
706#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
707#define MMCR0_FCP 0x20000000UL /* freeze in problem state */
708#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
709#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
710#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
711#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */
712#define MMCR0_TBEE 0x00400000UL /* time base exception enable */
713#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
714#define MMCR0_PMCnCE 0x00004000UL /* count enable for all but PMC 1*/
715#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
716#define MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */
717#define MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */
718
719#define SPRN_MMCR1 956
720#define MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */
721#define MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */
722#define MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */
723#define MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */
724#define SPRN_MMCR2 944
725#define SPRN_PMC1 953 /* Performance Counter Register 1 */
726#define SPRN_PMC2 954 /* Performance Counter Register 2 */
727#define SPRN_PMC3 957 /* Performance Counter Register 3 */
728#define SPRN_PMC4 958 /* Performance Counter Register 4 */
729#define SPRN_PMC5 945 /* Performance Counter Register 5 */
730#define SPRN_PMC6 946 /* Performance Counter Register 6 */
731
732#define SPRN_SIAR 955 /* Sampled Instruction Address Register */
9f04b9e3 733
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PM		 734/* Bit definitions for MMCR0 and PMC1 / PMC2. */
735#define MMCR0_PMC1_CYCLES (1 << 7)
736#define MMCR0_PMC1_ICACHEMISS (5 << 7)
737#define MMCR0_PMC1_DTLB (6 << 7)
738#define MMCR0_PMC2_DCACHEMISS 0x6
739#define MMCR0_PMC2_CYCLES 0x1
740#define MMCR0_PMC2_ITLB 0x7
741#define MMCR0_PMC2_LOADMISSTIME 0x5
9f04b9e3 742#endif
14cf11af 743
ee43eb78
BH		 744/*
745 * SPRG usage:
746 *
747 * All 64-bit:
2dd60d79
BH		 748 * - SPRG1 stores PACA pointer except 64-bit server in
749 * HV mode in which case it is HSPRG0
ee43eb78
BH		 750 *
751 * 64-bit server:
752 * - SPRG0 unused (reserved for HV on Power4)
063517be
BH		 753 * - SPRG2 scratch for exception vectors
754 * - SPRG3 unused (user visible)
2dd60d79
BH		 755 * - HSPRG0 stores PACA in HV mode
756 * - HSPRG1 scratch for "HV" exceptions
ee43eb78 757 *
13363ab9
BH		 758 * 64-bit embedded
759 * - SPRG0 generic exception scratch
760 * - SPRG2 TLB exception stack
761 * - SPRG3 unused (user visible)
762 * - SPRG4 unused (user visible)
763 * - SPRG6 TLB miss scratch (user visible, sorry !)
764 * - SPRG7 critical exception scratch
765 * - SPRG8 machine check exception scratch
766 * - SPRG9 debug exception scratch
767 *
ee43eb78
BH		 768 * All 32-bit:
769 * - SPRG3 current thread_info pointer
770 * (virtual on BookE, physical on others)
771 *
772 * 32-bit classic:
773 * - SPRG0 scratch for exception vectors
774 * - SPRG1 scratch for exception vectors
775 * - SPRG2 indicator that we are in RTAS
776 * - SPRG4 (603 only) pseudo TLB LRU data
777 *
778 * 32-bit 40x:
779 * - SPRG0 scratch for exception vectors
780 * - SPRG1 scratch for exception vectors
781 * - SPRG2 scratch for exception vectors
782 * - SPRG4 scratch for exception vectors (not 403)
783 * - SPRG5 scratch for exception vectors (not 403)
784 * - SPRG6 scratch for exception vectors (not 403)
785 * - SPRG7 scratch for exception vectors (not 403)
786 *
787 * 32-bit 440 and FSL BookE:
788 * - SPRG0 scratch for exception vectors
789 * - SPRG1 scratch for exception vectors (*)
790 * - SPRG2 scratch for crit interrupts handler
791 * - SPRG4 scratch for exception vectors
792 * - SPRG5 scratch for exception vectors
793 * - SPRG6 scratch for machine check handler
794 * - SPRG7 scratch for exception vectors
795 * - SPRG9 scratch for debug vectors (e500 only)
796 *
797 * Additionally, BookE separates "read" and "write"
798 * of those registers. That allows to use the userspace
799 * readable variant for reads, which can avoid a fault
800 * with KVM type virtualization.
801 *
802 * (*) Under KVM, the host SPRG1 is used to point to
803 * the current VCPU data structure
804 *
805 * 32-bit 8xx:
806 * - SPRG0 scratch for exception vectors
807 * - SPRG1 scratch for exception vectors
808 * - SPRG2 apparently unused but initialized
809 *
810 */
811#ifdef CONFIG_PPC64
063517be 812#define SPRN_SPRG_PACA SPRN_SPRG1
ee43eb78
BH		 813#else
814#define SPRN_SPRG_THREAD SPRN_SPRG3
815#endif
816
817#ifdef CONFIG_PPC_BOOK3S_64
063517be 818#define SPRN_SPRG_SCRATCH0 SPRN_SPRG2
2dd60d79
BH		 819#define SPRN_SPRG_HPACA SPRN_HSPRG0
820#define SPRN_SPRG_HSCRATCH0 SPRN_HSPRG1
821
822#define GET_PACA(rX) \
823 BEGIN_FTR_SECTION_NESTED(66); \
824 mfspr rX,SPRN_SPRG_PACA; \
825 FTR_SECTION_ELSE_NESTED(66); \
826 mfspr rX,SPRN_SPRG_HPACA; \
969391c5 827 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
2dd60d79
BH		 828
829#define SET_PACA(rX) \
830 BEGIN_FTR_SECTION_NESTED(66); \
831 mtspr SPRN_SPRG_PACA,rX; \
832 FTR_SECTION_ELSE_NESTED(66); \
833 mtspr SPRN_SPRG_HPACA,rX; \
969391c5 834 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
673b189a
PM		 835
836#define GET_SCRATCH0(rX) \
837 BEGIN_FTR_SECTION_NESTED(66); \
838 mfspr rX,SPRN_SPRG_SCRATCH0; \
839 FTR_SECTION_ELSE_NESTED(66); \
840 mfspr rX,SPRN_SPRG_HSCRATCH0; \
969391c5 841 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
673b189a
PM		 842
843#define SET_SCRATCH0(rX) \
844 BEGIN_FTR_SECTION_NESTED(66); \
845 mtspr SPRN_SPRG_SCRATCH0,rX; \
846 FTR_SECTION_ELSE_NESTED(66); \
847 mtspr SPRN_SPRG_HSCRATCH0,rX; \
969391c5 848 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
593adf31
PM		 849
850#else /* CONFIG_PPC_BOOK3S_64 */
851#define GET_SCRATCH0(rX) mfspr rX,SPRN_SPRG_SCRATCH0
852#define SET_SCRATCH0(rX) mtspr SPRN_SPRG_SCRATCH0,rX
853
ee43eb78
BH		 854#endif
855
13363ab9
BH		 856#ifdef CONFIG_PPC_BOOK3E_64
857#define SPRN_SPRG_MC_SCRATCH SPRN_SPRG8
858#define SPRN_SPRG_CRIT_SCRATCH SPRN_SPRG7
859#define SPRN_SPRG_DBG_SCRATCH SPRN_SPRG9
860#define SPRN_SPRG_TLB_EXFRAME SPRN_SPRG2
861#define SPRN_SPRG_TLB_SCRATCH SPRN_SPRG6
862#define SPRN_SPRG_GEN_SCRATCH SPRN_SPRG0
2dd60d79
BH		 863
864#define SET_PACA(rX) mtspr SPRN_SPRG_PACA,rX
865#define GET_PACA(rX) mfspr rX,SPRN_SPRG_PACA
866
13363ab9
BH		 867#endif
868
ee43eb78
BH		 869#ifdef CONFIG_PPC_BOOK3S_32
870#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
871#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
872#define SPRN_SPRG_RTAS SPRN_SPRG2
873#define SPRN_SPRG_603_LRU SPRN_SPRG4
874#endif
875
876#ifdef CONFIG_40x
877#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
878#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
879#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
880#define SPRN_SPRG_SCRATCH3 SPRN_SPRG4
881#define SPRN_SPRG_SCRATCH4 SPRN_SPRG5
882#define SPRN_SPRG_SCRATCH5 SPRN_SPRG6
883#define SPRN_SPRG_SCRATCH6 SPRN_SPRG7
884#endif
885
886#ifdef CONFIG_BOOKE
887#define SPRN_SPRG_RSCRATCH0 SPRN_SPRG0
888#define SPRN_SPRG_WSCRATCH0 SPRN_SPRG0
889#define SPRN_SPRG_RSCRATCH1 SPRN_SPRG1
890#define SPRN_SPRG_WSCRATCH1 SPRN_SPRG1
891#define SPRN_SPRG_RSCRATCH_CRIT SPRN_SPRG2
892#define SPRN_SPRG_WSCRATCH_CRIT SPRN_SPRG2
893#define SPRN_SPRG_RSCRATCH2 SPRN_SPRG4R
894#define SPRN_SPRG_WSCRATCH2 SPRN_SPRG4W
895#define SPRN_SPRG_RSCRATCH3 SPRN_SPRG5R
896#define SPRN_SPRG_WSCRATCH3 SPRN_SPRG5W
1325a684
AK		 897#define SPRN_SPRG_RSCRATCH_MC SPRN_SPRG1
898#define SPRN_SPRG_WSCRATCH_MC SPRN_SPRG1
ee43eb78
BH		 899#define SPRN_SPRG_RSCRATCH4 SPRN_SPRG7R
900#define SPRN_SPRG_WSCRATCH4 SPRN_SPRG7W
901#ifdef CONFIG_E200
902#define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG6R
903#define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG6W
904#else
905#define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG9
906#define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG9
907#endif
908#define SPRN_SPRG_RVCPU SPRN_SPRG1
909#define SPRN_SPRG_WVCPU SPRN_SPRG1
910#endif
911
912#ifdef CONFIG_8xx
913#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
914#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
915#endif
916
2dd60d79
BH		 917
918
3a2c48cf
AB		 919/*
920 * An mtfsf instruction with the L bit set. On CPUs that support this a
52aed7cd 921 * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored.
3a2c48cf
AB		 922 *
923 * Until binutils gets the new form of mtfsf, hardwire the instruction.
924 */
925#ifdef CONFIG_PPC64
926#define MTFSF_L(REG) \
927 .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
928#else
929#define MTFSF_L(REG) mtfsf 0xff, (REG)
930#endif
931
14cf11af
PM		 932/* Processor Version Register (PVR) field extraction */
933
934#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
935#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
936
9f04b9e3
PM		 937#define __is_processor(pv) (PVR_VER(mfspr(SPRN_PVR)) == (pv))
938
14cf11af
PM		 939/*
940 * IBM has further subdivided the standard PowerPC 16-bit version and
941 * revision subfields of the PVR for the PowerPC 403s into the following:
942 */
943
944#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
945#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
946#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
947#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
948#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
949#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
950
951/* Processor Version Numbers */
952
953#define PVR_403GA 0x00200000
954#define PVR_403GB 0x00200100
955#define PVR_403GC 0x00200200
956#define PVR_403GCX 0x00201400
957#define PVR_405GP 0x40110000
e7f75ad0 958#define PVR_476 0x11a52000
df777bd3 959#define PVR_476FPE 0x7ff50000
14cf11af
PM		 960#define PVR_STB03XXX 0x40310000
961#define PVR_NP405H 0x41410000
962#define PVR_NP405L 0x41610000
963#define PVR_601 0x00010000
964#define PVR_602 0x00050000
965#define PVR_603 0x00030000
966#define PVR_603e 0x00060000
967#define PVR_603ev 0x00070000
968#define PVR_603r 0x00071000
969#define PVR_604 0x00040000
970#define PVR_604e 0x00090000
971#define PVR_604r 0x000A0000
972#define PVR_620 0x00140000
973#define PVR_740 0x00080000
974#define PVR_750 PVR_740
975#define PVR_740P 0x10080000
976#define PVR_750P PVR_740P
977#define PVR_7400 0x000C0000
978#define PVR_7410 0x800C0000
979#define PVR_7450 0x80000000
980#define PVR_8540 0x80200000
981#define PVR_8560 0x80200000
ac6f1203
LY		 982#define PVR_VER_E500V1 0x8020
983#define PVR_VER_E500V2 0x8021
14cf11af
PM		 984/*
985 * For the 8xx processors, all of them report the same PVR family for
986 * the PowerPC core. The various versions of these processors must be
987 * differentiated by the version number in the Communication Processor
988 * Module (CPM).
989 */
990#define PVR_821 0x00500000
991#define PVR_823 PVR_821
992#define PVR_850 PVR_821
993#define PVR_860 PVR_821
994#define PVR_8240 0x00810100
995#define PVR_8245 0x80811014
996#define PVR_8260 PVR_8240
997
b4e8c8dd
TS		 998/* 476 Simulator seems to currently have the PVR of the 602... */
999#define PVR_476_ISS 0x00052000
1000
9f04b9e3
PM		 1001/* 64-bit processors */
1002/* XXX the prefix should be PVR_, we'll do a global sweep to fix it one day */
d6b89a19
MN		 1003#define PV_NORTHSTAR 0x0033
1004#define PV_PULSAR 0x0034
1005#define PV_POWER4 0x0035
1006#define PV_ICESTAR 0x0036
1007#define PV_SSTAR 0x0037
1008#define PV_POWER4p 0x0038
9f04b9e3 1009#define PV_970 0x0039
d6b89a19 1010#define PV_POWER5 0x003A
9f04b9e3
PM		 1011#define PV_POWER5p 0x003B
1012#define PV_970FX 0x003C
50fb8ebe
BH		 1013#define PV_POWER6 0x003E
1014#define PV_POWER7 0x003F
d6b89a19
MN		 1015#define PV_630 0x0040
1016#define PV_630p 0x0041
1017#define PV_970MP 0x0044
362ff7b2 1018#define PV_970GX 0x0045
d6b89a19 1019#define PV_BE 0x0070
b3ebd1d8 1020#define PV_PA6T 0x0090
9f04b9e3 1021
14cf11af
PM		 1022/* Macros for setting and retrieving special purpose registers */
1023#ifndef __ASSEMBLY__
9f04b9e3 1024#define mfmsr() ({unsigned long rval; \
14cf11af 1025 asm volatile("mfmsr %0" : "=r" (rval)); rval;})
0866eb99 1026#ifdef CONFIG_PPC_BOOK3S_64
9f04b9e3 1027#define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \
4c75f84f 1028 : : "r" (v) : "memory")
9f04b9e3 1029#define mtmsrd(v) __mtmsrd((v), 0)
f78541dc 1030#define mtmsr(v) mtmsrd(v)
9f04b9e3 1031#else
326ed6a9
SW		 1032#define mtmsr(v) asm volatile("mtmsr %0" : \
1033 : "r" ((unsigned long)(v)) \
1034 : "memory")
9f04b9e3 1035#endif
14cf11af 1036
9f04b9e3 1037#define mfspr(rn) ({unsigned long rval; \
14cf11af
PM		 1038 asm volatile("mfspr %0," __stringify(rn) \
1039 : "=r" (rval)); rval;})
326ed6a9
SW		 1040#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : \
1041 : "r" ((unsigned long)(v)) \
2fae0a52 1042 : "memory")
14cf11af 1043
859deea9
BH		 1044#ifdef __powerpc64__
1045#ifdef CONFIG_PPC_CELL
1046#define mftb() ({unsigned long rval; \
1047 asm volatile( \
1048 "90: mftb %0;\n" \
1049 "97: cmpwi %0,0;\n" \
1050 " beq- 90b;\n" \
1051 "99:\n" \
1052 ".section __ftr_fixup,\"a\"\n" \
1053 ".align 3\n" \
1054 "98:\n" \
1055 " .llong %1\n" \
1056 " .llong %1\n" \
1057 " .llong 97b-98b\n" \
1058 " .llong 99b-98b\n" \
fac23fe4
ME		 1059 " .llong 0\n" \
1060 " .llong 0\n" \
859deea9
BH		 1061 ".previous" \
1062 : "=r" (rval) : "i" (CPU_FTR_CELL_TB_BUG)); rval;})
1063#else
9f04b9e3
PM		 1064#define mftb() ({unsigned long rval; \
1065 asm volatile("mftb %0" : "=r" (rval)); rval;})
859deea9
BH		 1066#endif /* !CONFIG_PPC_CELL */
1067
1068#else /* __powerpc64__ */
1069
9f04b9e3
PM		 1070#define mftbl() ({unsigned long rval; \
1071 asm volatile("mftbl %0" : "=r" (rval)); rval;})
859deea9
BH		 1072#define mftbu() ({unsigned long rval; \
1073 asm volatile("mftbu %0" : "=r" (rval)); rval;})
1074#endif /* !__powerpc64__ */
9f04b9e3
PM		 1075
1076#define mttbl(v) asm volatile("mttbl %0":: "r"(v))
1077#define mttbu(v) asm volatile("mttbu %0":: "r"(v))
1078
1079#ifdef CONFIG_PPC32
14cf11af
PM		 1080#define mfsrin(v) ({unsigned int rval; \
1081 asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
1082 rval;})
9f04b9e3 1083#endif
14cf11af
PM		 1084
1085#define proc_trap() asm volatile("trap")
9f04b9e3 1086
fe1952fc
BH		 1087#define __get_SP() ({unsigned long sp; \
1088 asm volatile("mr %0,1": "=r" (sp)); sp;})
4350147a
BH		 1089
1090extern unsigned long scom970_read(unsigned int address);
1091extern void scom970_write(unsigned int address, unsigned long value);
1092
322b4394
AV		 1093struct pt_regs;
1094
1095extern void ppc_save_regs(struct pt_regs *regs);
1096
14cf11af 1097#endif /* __ASSEMBLY__ */
14cf11af 1098#endif /* __KERNEL__ */
9f04b9e3 1099#endif /* _ASM_POWERPC_REG_H */
Linux 6.x block layer and io_uring tree(s)