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98658538 | 1 | /* |
98658538 LY |
2 | * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved. |
3 | * | |
4 | * Authors: Shlomi Gridish <gridish@freescale.com> | |
5 | * Li Yang <leoli@freescale.com> | |
6 | * | |
7 | * Description: | |
8 | * QE IC external definitions and structure. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the | |
12 | * Free Software Foundation; either version 2 of the License, or (at your | |
13 | * option) any later version. | |
14 | */ | |
15 | #ifndef _ASM_POWERPC_QE_IC_H | |
16 | #define _ASM_POWERPC_QE_IC_H | |
17 | ||
18 | #include <linux/irq.h> | |
19 | ||
be11d3b3 AV |
20 | struct device_node; |
21 | struct qe_ic; | |
22 | ||
98658538 LY |
23 | #define NUM_OF_QE_IC_GROUPS 6 |
24 | ||
25 | /* Flags when we init the QE IC */ | |
26 | #define QE_IC_SPREADMODE_GRP_W 0x00000001 | |
27 | #define QE_IC_SPREADMODE_GRP_X 0x00000002 | |
28 | #define QE_IC_SPREADMODE_GRP_Y 0x00000004 | |
29 | #define QE_IC_SPREADMODE_GRP_Z 0x00000008 | |
30 | #define QE_IC_SPREADMODE_GRP_RISCA 0x00000010 | |
31 | #define QE_IC_SPREADMODE_GRP_RISCB 0x00000020 | |
32 | ||
33 | #define QE_IC_LOW_SIGNAL 0x00000100 | |
34 | #define QE_IC_HIGH_SIGNAL 0x00000200 | |
35 | ||
36 | #define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH 0x00001000 | |
37 | #define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH 0x00002000 | |
38 | #define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH 0x00004000 | |
39 | #define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH 0x00008000 | |
40 | #define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH 0x00010000 | |
41 | #define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH 0x00020000 | |
42 | #define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH 0x00040000 | |
43 | #define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH 0x00080000 | |
44 | #define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH 0x00100000 | |
45 | #define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH 0x00200000 | |
46 | #define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH 0x00400000 | |
47 | #define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH 0x00800000 | |
48 | #define QE_IC_GRP_W_DEST_SIGNAL_SHIFT (12) | |
49 | ||
50 | /* QE interrupt sources groups */ | |
51 | enum qe_ic_grp_id { | |
52 | QE_IC_GRP_W = 0, /* QE interrupt controller group W */ | |
53 | QE_IC_GRP_X, /* QE interrupt controller group X */ | |
54 | QE_IC_GRP_Y, /* QE interrupt controller group Y */ | |
55 | QE_IC_GRP_Z, /* QE interrupt controller group Z */ | |
56 | QE_IC_GRP_RISCA, /* QE interrupt controller RISC group A */ | |
57 | QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */ | |
58 | }; | |
59 | ||
be11d3b3 | 60 | #ifdef CONFIG_QUICC_ENGINE |
cccd2102 AV |
61 | void qe_ic_init(struct device_node *node, unsigned int flags, |
62 | void (*low_handler)(unsigned int irq, struct irq_desc *desc), | |
63 | void (*high_handler)(unsigned int irq, struct irq_desc *desc)); | |
be11d3b3 AV |
64 | unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic); |
65 | unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic); | |
66 | #else | |
67 | static inline void qe_ic_init(struct device_node *node, unsigned int flags, | |
68 | void (*low_handler)(unsigned int irq, struct irq_desc *desc), | |
69 | void (*high_handler)(unsigned int irq, struct irq_desc *desc)) | |
70 | {} | |
71 | static inline unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic) | |
72 | { return 0; } | |
73 | static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic) | |
74 | { return 0; } | |
75 | #endif /* CONFIG_QUICC_ENGINE */ | |
76 | ||
98658538 LY |
77 | void qe_ic_set_highest_priority(unsigned int virq, int high); |
78 | int qe_ic_set_priority(unsigned int virq, unsigned int priority); | |
79 | int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high); | |
80 | ||
cccd2102 AV |
81 | static inline void qe_ic_cascade_low_ipic(unsigned int irq, |
82 | struct irq_desc *desc) | |
83 | { | |
84 | struct qe_ic *qe_ic = desc->handler_data; | |
85 | unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic); | |
86 | ||
87 | if (cascade_irq != NO_IRQ) | |
88 | generic_handle_irq(cascade_irq); | |
89 | } | |
90 | ||
91 | static inline void qe_ic_cascade_high_ipic(unsigned int irq, | |
92 | struct irq_desc *desc) | |
93 | { | |
94 | struct qe_ic *qe_ic = desc->handler_data; | |
95 | unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic); | |
96 | ||
97 | if (cascade_irq != NO_IRQ) | |
98 | generic_handle_irq(cascade_irq); | |
99 | } | |
100 | ||
101 | static inline void qe_ic_cascade_low_mpic(unsigned int irq, | |
102 | struct irq_desc *desc) | |
103 | { | |
104 | struct qe_ic *qe_ic = desc->handler_data; | |
105 | unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic); | |
106 | ||
107 | if (cascade_irq != NO_IRQ) | |
108 | generic_handle_irq(cascade_irq); | |
109 | ||
110 | desc->chip->eoi(irq); | |
111 | } | |
112 | ||
113 | static inline void qe_ic_cascade_high_mpic(unsigned int irq, | |
114 | struct irq_desc *desc) | |
115 | { | |
116 | struct qe_ic *qe_ic = desc->handler_data; | |
117 | unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic); | |
118 | ||
119 | if (cascade_irq != NO_IRQ) | |
120 | generic_handle_irq(cascade_irq); | |
121 | ||
122 | desc->chip->eoi(irq); | |
123 | } | |
124 | ||
125 | static inline void qe_ic_cascade_muxed_mpic(unsigned int irq, | |
126 | struct irq_desc *desc) | |
127 | { | |
128 | struct qe_ic *qe_ic = desc->handler_data; | |
129 | unsigned int cascade_irq; | |
130 | ||
131 | cascade_irq = qe_ic_get_high_irq(qe_ic); | |
132 | if (cascade_irq == NO_IRQ) | |
133 | cascade_irq = qe_ic_get_low_irq(qe_ic); | |
134 | ||
135 | if (cascade_irq != NO_IRQ) | |
136 | generic_handle_irq(cascade_irq); | |
137 | ||
138 | desc->chip->eoi(irq); | |
139 | } | |
140 | ||
98658538 | 141 | #endif /* _ASM_POWERPC_QE_IC_H */ |