Commit | Line | Data |
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f58a9d17 GL |
1 | /* |
2 | * PS3 platform declarations. | |
3 | * | |
4 | * Copyright (C) 2006 Sony Computer Entertainment Inc. | |
5 | * Copyright 2006 Sony Corp. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; version 2 of the License. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | #if !defined(_ASM_POWERPC_PS3_H) | |
22 | #define _ASM_POWERPC_PS3_H | |
23 | ||
f58a9d17 GL |
24 | #include <linux/init.h> |
25 | #include <linux/types.h> | |
26 | #include <linux/device.h> | |
a1ce3928 | 27 | #include <asm/cell-pmu.h> |
f58a9d17 | 28 | |
66b44954 GL |
29 | union ps3_firmware_version { |
30 | u64 raw; | |
31 | struct { | |
32 | u16 pad; | |
33 | u16 major; | |
34 | u16 minor; | |
35 | u16 rev; | |
36 | }; | |
37 | }; | |
38 | ||
1322810c MM |
39 | void ps3_get_firmware_version(union ps3_firmware_version *v); |
40 | int ps3_compare_firmware_version(u16 major, u16 minor, u16 rev); | |
66b44954 | 41 | |
098e2744 GU |
42 | /* 'Other OS' area */ |
43 | ||
44 | enum ps3_param_av_multi_out { | |
45 | PS3_PARAM_AV_MULTI_OUT_NTSC = 0, | |
46 | PS3_PARAM_AV_MULTI_OUT_PAL_RGB = 1, | |
47 | PS3_PARAM_AV_MULTI_OUT_PAL_YCBCR = 2, | |
48 | PS3_PARAM_AV_MULTI_OUT_SECAM = 3, | |
49 | }; | |
50 | ||
51 | enum ps3_param_av_multi_out ps3_os_area_get_av_multi_out(void); | |
52 | ||
0b5f037a GU |
53 | extern u64 ps3_os_area_get_rtc_diff(void); |
54 | extern void ps3_os_area_set_rtc_diff(u64 rtc_diff); | |
55 | ||
a4e623fb GU |
56 | struct ps3_os_area_flash_ops { |
57 | ssize_t (*read)(void *buf, size_t count, loff_t pos); | |
58 | ssize_t (*write)(const void *buf, size_t count, loff_t pos); | |
59 | }; | |
60 | ||
61 | extern void ps3_os_area_flash_register(const struct ps3_os_area_flash_ops *ops); | |
62 | ||
f58a9d17 GL |
63 | /* dma routines */ |
64 | ||
65 | enum ps3_dma_page_size { | |
66 | PS3_DMA_4K = 12U, | |
67 | PS3_DMA_64K = 16U, | |
68 | PS3_DMA_1M = 20U, | |
69 | PS3_DMA_16M = 24U, | |
70 | }; | |
71 | ||
72 | enum ps3_dma_region_type { | |
73 | PS3_DMA_OTHER = 0, | |
74 | PS3_DMA_INTERNAL = 2, | |
75 | }; | |
76 | ||
6bb5cf10 GL |
77 | struct ps3_dma_region_ops; |
78 | ||
f58a9d17 GL |
79 | /** |
80 | * struct ps3_dma_region - A per device dma state variables structure | |
81 | * @did: The HV device id. | |
82 | * @page_size: The ioc pagesize. | |
83 | * @region_type: The HV region type. | |
84 | * @bus_addr: The 'translated' bus address of the region. | |
85 | * @len: The length in bytes of the region. | |
6bb5cf10 GL |
86 | * @offset: The offset from the start of memory of the region. |
87 | * @ioid: The IOID of the device who owns this region | |
f58a9d17 | 88 | * @chunk_list: Opaque variable used by the ioc page manager. |
6bb5cf10 | 89 | * @region_ops: struct ps3_dma_region_ops - dma region operations |
f58a9d17 GL |
90 | */ |
91 | ||
92 | struct ps3_dma_region { | |
6bb5cf10 GL |
93 | struct ps3_system_bus_device *dev; |
94 | /* device variables */ | |
95 | const struct ps3_dma_region_ops *region_ops; | |
96 | unsigned char ioid; | |
f58a9d17 GL |
97 | enum ps3_dma_page_size page_size; |
98 | enum ps3_dma_region_type region_type; | |
f58a9d17 | 99 | unsigned long len; |
6bb5cf10 GL |
100 | unsigned long offset; |
101 | ||
102 | /* driver variables (set by ps3_dma_region_create) */ | |
103 | unsigned long bus_addr; | |
f58a9d17 GL |
104 | struct { |
105 | spinlock_t lock; | |
106 | struct list_head head; | |
107 | } chunk_list; | |
108 | }; | |
109 | ||
6bb5cf10 GL |
110 | struct ps3_dma_region_ops { |
111 | int (*create)(struct ps3_dma_region *); | |
112 | int (*free)(struct ps3_dma_region *); | |
113 | int (*map)(struct ps3_dma_region *, | |
114 | unsigned long virt_addr, | |
115 | unsigned long len, | |
494fd07a | 116 | dma_addr_t *bus_addr, |
6bb5cf10 GL |
117 | u64 iopte_pp); |
118 | int (*unmap)(struct ps3_dma_region *, | |
494fd07a | 119 | dma_addr_t bus_addr, |
6bb5cf10 GL |
120 | unsigned long len); |
121 | }; | |
f58a9d17 GL |
122 | /** |
123 | * struct ps3_dma_region_init - Helper to initialize structure variables | |
124 | * | |
125 | * Helper to properly initialize variables prior to calling | |
126 | * ps3_system_bus_device_register. | |
127 | */ | |
128 | ||
6bb5cf10 GL |
129 | struct ps3_system_bus_device; |
130 | ||
131 | int ps3_dma_region_init(struct ps3_system_bus_device *dev, | |
132 | struct ps3_dma_region *r, enum ps3_dma_page_size page_size, | |
133 | enum ps3_dma_region_type region_type, void *addr, unsigned long len); | |
f58a9d17 GL |
134 | int ps3_dma_region_create(struct ps3_dma_region *r); |
135 | int ps3_dma_region_free(struct ps3_dma_region *r); | |
136 | int ps3_dma_map(struct ps3_dma_region *r, unsigned long virt_addr, | |
494fd07a | 137 | unsigned long len, dma_addr_t *bus_addr, |
6bb5cf10 | 138 | u64 iopte_pp); |
494fd07a | 139 | int ps3_dma_unmap(struct ps3_dma_region *r, dma_addr_t bus_addr, |
f58a9d17 GL |
140 | unsigned long len); |
141 | ||
142 | /* mmio routines */ | |
143 | ||
144 | enum ps3_mmio_page_size { | |
145 | PS3_MMIO_4K = 12U, | |
146 | PS3_MMIO_64K = 16U | |
147 | }; | |
148 | ||
6bb5cf10 | 149 | struct ps3_mmio_region_ops; |
f58a9d17 GL |
150 | /** |
151 | * struct ps3_mmio_region - a per device mmio state variables structure | |
152 | * | |
153 | * Current systems can be supported with a single region per device. | |
154 | */ | |
155 | ||
156 | struct ps3_mmio_region { | |
6bb5cf10 GL |
157 | struct ps3_system_bus_device *dev; |
158 | const struct ps3_mmio_region_ops *mmio_ops; | |
f58a9d17 GL |
159 | unsigned long bus_addr; |
160 | unsigned long len; | |
161 | enum ps3_mmio_page_size page_size; | |
162 | unsigned long lpar_addr; | |
163 | }; | |
164 | ||
6bb5cf10 GL |
165 | struct ps3_mmio_region_ops { |
166 | int (*create)(struct ps3_mmio_region *); | |
167 | int (*free)(struct ps3_mmio_region *); | |
168 | }; | |
f58a9d17 GL |
169 | /** |
170 | * struct ps3_mmio_region_init - Helper to initialize structure variables | |
171 | * | |
172 | * Helper to properly initialize variables prior to calling | |
173 | * ps3_system_bus_device_register. | |
174 | */ | |
175 | ||
6bb5cf10 GL |
176 | int ps3_mmio_region_init(struct ps3_system_bus_device *dev, |
177 | struct ps3_mmio_region *r, unsigned long bus_addr, unsigned long len, | |
178 | enum ps3_mmio_page_size page_size); | |
f58a9d17 GL |
179 | int ps3_mmio_region_create(struct ps3_mmio_region *r); |
180 | int ps3_free_mmio_region(struct ps3_mmio_region *r); | |
181 | unsigned long ps3_mm_phys_to_lpar(unsigned long phys_addr); | |
182 | ||
183 | /* inrerrupt routines */ | |
184 | ||
861be32c GL |
185 | enum ps3_cpu_binding { |
186 | PS3_BINDING_CPU_ANY = -1, | |
187 | PS3_BINDING_CPU_0 = 0, | |
188 | PS3_BINDING_CPU_1 = 1, | |
189 | }; | |
190 | ||
dc4f60c2 GL |
191 | int ps3_irq_plug_setup(enum ps3_cpu_binding cpu, unsigned long outlet, |
192 | unsigned int *virq); | |
193 | int ps3_irq_plug_destroy(unsigned int virq); | |
194 | int ps3_event_receive_port_setup(enum ps3_cpu_binding cpu, unsigned int *virq); | |
195 | int ps3_event_receive_port_destroy(unsigned int virq); | |
f58a9d17 | 196 | int ps3_send_event_locally(unsigned int virq); |
dc4f60c2 GL |
197 | |
198 | int ps3_io_irq_setup(enum ps3_cpu_binding cpu, unsigned int interrupt_id, | |
861be32c | 199 | unsigned int *virq); |
dc4f60c2 GL |
200 | int ps3_io_irq_destroy(unsigned int virq); |
201 | int ps3_vuart_irq_setup(enum ps3_cpu_binding cpu, void* virt_addr_bmp, | |
f58a9d17 | 202 | unsigned int *virq); |
dc4f60c2 GL |
203 | int ps3_vuart_irq_destroy(unsigned int virq); |
204 | int ps3_spe_irq_setup(enum ps3_cpu_binding cpu, unsigned long spe_id, | |
861be32c | 205 | unsigned int class, unsigned int *virq); |
dc4f60c2 GL |
206 | int ps3_spe_irq_destroy(unsigned int virq); |
207 | ||
6bb5cf10 GL |
208 | int ps3_sb_event_receive_port_setup(struct ps3_system_bus_device *dev, |
209 | enum ps3_cpu_binding cpu, unsigned int *virq); | |
210 | int ps3_sb_event_receive_port_destroy(struct ps3_system_bus_device *dev, | |
211 | unsigned int virq); | |
f58a9d17 GL |
212 | |
213 | /* lv1 result codes */ | |
214 | ||
215 | enum lv1_result { | |
216 | LV1_SUCCESS = 0, | |
217 | /* not used -1 */ | |
218 | LV1_RESOURCE_SHORTAGE = -2, | |
219 | LV1_NO_PRIVILEGE = -3, | |
220 | LV1_DENIED_BY_POLICY = -4, | |
221 | LV1_ACCESS_VIOLATION = -5, | |
222 | LV1_NO_ENTRY = -6, | |
223 | LV1_DUPLICATE_ENTRY = -7, | |
224 | LV1_TYPE_MISMATCH = -8, | |
225 | LV1_BUSY = -9, | |
226 | LV1_EMPTY = -10, | |
227 | LV1_WRONG_STATE = -11, | |
228 | /* not used -12 */ | |
229 | LV1_NO_MATCH = -13, | |
230 | LV1_ALREADY_CONNECTED = -14, | |
231 | LV1_UNSUPPORTED_PARAMETER_VALUE = -15, | |
232 | LV1_CONDITION_NOT_SATISFIED = -16, | |
233 | LV1_ILLEGAL_PARAMETER_VALUE = -17, | |
234 | LV1_BAD_OPTION = -18, | |
235 | LV1_IMPLEMENTATION_LIMITATION = -19, | |
236 | LV1_NOT_IMPLEMENTED = -20, | |
237 | LV1_INVALID_CLASS_ID = -21, | |
238 | LV1_CONSTRAINT_NOT_SATISFIED = -22, | |
239 | LV1_ALIGNMENT_ERROR = -23, | |
06462d92 GU |
240 | LV1_HARDWARE_ERROR = -24, |
241 | LV1_INVALID_DATA_FORMAT = -25, | |
242 | LV1_INVALID_OPERATION = -26, | |
f58a9d17 GL |
243 | LV1_INTERNAL_ERROR = -32768, |
244 | }; | |
245 | ||
246 | static inline const char* ps3_result(int result) | |
247 | { | |
248 | #if defined(DEBUG) | |
249 | switch (result) { | |
250 | case LV1_SUCCESS: | |
251 | return "LV1_SUCCESS (0)"; | |
252 | case -1: | |
253 | return "** unknown result ** (-1)"; | |
254 | case LV1_RESOURCE_SHORTAGE: | |
255 | return "LV1_RESOURCE_SHORTAGE (-2)"; | |
256 | case LV1_NO_PRIVILEGE: | |
257 | return "LV1_NO_PRIVILEGE (-3)"; | |
258 | case LV1_DENIED_BY_POLICY: | |
259 | return "LV1_DENIED_BY_POLICY (-4)"; | |
260 | case LV1_ACCESS_VIOLATION: | |
261 | return "LV1_ACCESS_VIOLATION (-5)"; | |
262 | case LV1_NO_ENTRY: | |
263 | return "LV1_NO_ENTRY (-6)"; | |
264 | case LV1_DUPLICATE_ENTRY: | |
265 | return "LV1_DUPLICATE_ENTRY (-7)"; | |
266 | case LV1_TYPE_MISMATCH: | |
267 | return "LV1_TYPE_MISMATCH (-8)"; | |
268 | case LV1_BUSY: | |
269 | return "LV1_BUSY (-9)"; | |
270 | case LV1_EMPTY: | |
271 | return "LV1_EMPTY (-10)"; | |
272 | case LV1_WRONG_STATE: | |
273 | return "LV1_WRONG_STATE (-11)"; | |
274 | case -12: | |
275 | return "** unknown result ** (-12)"; | |
276 | case LV1_NO_MATCH: | |
277 | return "LV1_NO_MATCH (-13)"; | |
278 | case LV1_ALREADY_CONNECTED: | |
279 | return "LV1_ALREADY_CONNECTED (-14)"; | |
280 | case LV1_UNSUPPORTED_PARAMETER_VALUE: | |
281 | return "LV1_UNSUPPORTED_PARAMETER_VALUE (-15)"; | |
282 | case LV1_CONDITION_NOT_SATISFIED: | |
283 | return "LV1_CONDITION_NOT_SATISFIED (-16)"; | |
284 | case LV1_ILLEGAL_PARAMETER_VALUE: | |
285 | return "LV1_ILLEGAL_PARAMETER_VALUE (-17)"; | |
286 | case LV1_BAD_OPTION: | |
287 | return "LV1_BAD_OPTION (-18)"; | |
288 | case LV1_IMPLEMENTATION_LIMITATION: | |
289 | return "LV1_IMPLEMENTATION_LIMITATION (-19)"; | |
290 | case LV1_NOT_IMPLEMENTED: | |
291 | return "LV1_NOT_IMPLEMENTED (-20)"; | |
292 | case LV1_INVALID_CLASS_ID: | |
293 | return "LV1_INVALID_CLASS_ID (-21)"; | |
294 | case LV1_CONSTRAINT_NOT_SATISFIED: | |
295 | return "LV1_CONSTRAINT_NOT_SATISFIED (-22)"; | |
296 | case LV1_ALIGNMENT_ERROR: | |
297 | return "LV1_ALIGNMENT_ERROR (-23)"; | |
06462d92 GU |
298 | case LV1_HARDWARE_ERROR: |
299 | return "LV1_HARDWARE_ERROR (-24)"; | |
300 | case LV1_INVALID_DATA_FORMAT: | |
301 | return "LV1_INVALID_DATA_FORMAT (-25)"; | |
302 | case LV1_INVALID_OPERATION: | |
303 | return "LV1_INVALID_OPERATION (-26)"; | |
f58a9d17 GL |
304 | case LV1_INTERNAL_ERROR: |
305 | return "LV1_INTERNAL_ERROR (-32768)"; | |
306 | default: | |
307 | BUG(); | |
308 | return "** unknown result **"; | |
309 | }; | |
310 | #else | |
311 | return ""; | |
312 | #endif | |
313 | } | |
314 | ||
a3d4d643 GL |
315 | /* system bus routines */ |
316 | ||
317 | enum ps3_match_id { | |
46d01492 GU |
318 | PS3_MATCH_ID_EHCI = 1, |
319 | PS3_MATCH_ID_OHCI = 2, | |
320 | PS3_MATCH_ID_GELIC = 3, | |
321 | PS3_MATCH_ID_AV_SETTINGS = 4, | |
322 | PS3_MATCH_ID_SYSTEM_MANAGER = 5, | |
323 | PS3_MATCH_ID_STOR_DISK = 6, | |
324 | PS3_MATCH_ID_STOR_ROM = 7, | |
325 | PS3_MATCH_ID_STOR_FLASH = 8, | |
326 | PS3_MATCH_ID_SOUND = 9, | |
327 | PS3_MATCH_ID_GPU = 10, | |
328 | PS3_MATCH_ID_LPM = 11, | |
6bb5cf10 GL |
329 | }; |
330 | ||
46d01492 GU |
331 | enum ps3_match_sub_id { |
332 | PS3_MATCH_SUB_ID_GPU_FB = 1, | |
cffb4add | 333 | PS3_MATCH_SUB_ID_GPU_RAMDISK = 2, |
46d01492 GU |
334 | }; |
335 | ||
336 | #define PS3_MODULE_ALIAS_EHCI "ps3:1:0" | |
337 | #define PS3_MODULE_ALIAS_OHCI "ps3:2:0" | |
338 | #define PS3_MODULE_ALIAS_GELIC "ps3:3:0" | |
339 | #define PS3_MODULE_ALIAS_AV_SETTINGS "ps3:4:0" | |
340 | #define PS3_MODULE_ALIAS_SYSTEM_MANAGER "ps3:5:0" | |
341 | #define PS3_MODULE_ALIAS_STOR_DISK "ps3:6:0" | |
342 | #define PS3_MODULE_ALIAS_STOR_ROM "ps3:7:0" | |
343 | #define PS3_MODULE_ALIAS_STOR_FLASH "ps3:8:0" | |
344 | #define PS3_MODULE_ALIAS_SOUND "ps3:9:0" | |
345 | #define PS3_MODULE_ALIAS_GPU_FB "ps3:10:1" | |
0a2d15b9 | 346 | #define PS3_MODULE_ALIAS_GPU_RAMDISK "ps3:10:2" |
46d01492 | 347 | #define PS3_MODULE_ALIAS_LPM "ps3:11:0" |
6bb5cf10 GL |
348 | |
349 | enum ps3_system_bus_device_type { | |
350 | PS3_DEVICE_TYPE_IOC0 = 1, | |
351 | PS3_DEVICE_TYPE_SB, | |
352 | PS3_DEVICE_TYPE_VUART, | |
ed757002 | 353 | PS3_DEVICE_TYPE_LPM, |
a3d4d643 GL |
354 | }; |
355 | ||
356 | /** | |
357 | * struct ps3_system_bus_device - a device on the system bus | |
358 | */ | |
359 | ||
360 | struct ps3_system_bus_device { | |
361 | enum ps3_match_id match_id; | |
059e4938 | 362 | enum ps3_match_sub_id match_sub_id; |
6bb5cf10 GL |
363 | enum ps3_system_bus_device_type dev_type; |
364 | ||
034e0ab5 GU |
365 | u64 bus_id; /* SB */ |
366 | u64 dev_id; /* SB */ | |
6bb5cf10 GL |
367 | unsigned int interrupt_id; /* SB */ |
368 | struct ps3_dma_region *d_region; /* SB, IOC0 */ | |
369 | struct ps3_mmio_region *m_region; /* SB, IOC0*/ | |
370 | unsigned int port_number; /* VUART */ | |
ed757002 GL |
371 | struct { /* LPM */ |
372 | u64 node_id; | |
373 | u64 pu_id; | |
374 | u64 rights; | |
375 | } lpm; | |
6bb5cf10 GL |
376 | |
377 | /* struct iommu_table *iommu_table; -- waiting for BenH's cleanups */ | |
a3d4d643 | 378 | struct device core; |
6bb5cf10 | 379 | void *driver_priv; /* private driver variables */ |
a3d4d643 GL |
380 | }; |
381 | ||
6bb5cf10 GL |
382 | int ps3_open_hv_device(struct ps3_system_bus_device *dev); |
383 | int ps3_close_hv_device(struct ps3_system_bus_device *dev); | |
384 | ||
a3d4d643 GL |
385 | /** |
386 | * struct ps3_system_bus_driver - a driver for a device on the system bus | |
387 | */ | |
388 | ||
389 | struct ps3_system_bus_driver { | |
390 | enum ps3_match_id match_id; | |
059e4938 | 391 | enum ps3_match_sub_id match_sub_id; |
a3d4d643 GL |
392 | struct device_driver core; |
393 | int (*probe)(struct ps3_system_bus_device *); | |
394 | int (*remove)(struct ps3_system_bus_device *); | |
6bb5cf10 | 395 | int (*shutdown)(struct ps3_system_bus_device *); |
a3d4d643 GL |
396 | /* int (*suspend)(struct ps3_system_bus_device *, pm_message_t); */ |
397 | /* int (*resume)(struct ps3_system_bus_device *); */ | |
398 | }; | |
399 | ||
400 | int ps3_system_bus_device_register(struct ps3_system_bus_device *dev); | |
401 | int ps3_system_bus_driver_register(struct ps3_system_bus_driver *drv); | |
402 | void ps3_system_bus_driver_unregister(struct ps3_system_bus_driver *drv); | |
6bb5cf10 GL |
403 | |
404 | static inline struct ps3_system_bus_driver *ps3_drv_to_system_bus_drv( | |
a3d4d643 GL |
405 | struct device_driver *_drv) |
406 | { | |
407 | return container_of(_drv, struct ps3_system_bus_driver, core); | |
408 | } | |
6bb5cf10 | 409 | static inline struct ps3_system_bus_device *ps3_dev_to_system_bus_dev( |
a3d4d643 GL |
410 | struct device *_dev) |
411 | { | |
412 | return container_of(_dev, struct ps3_system_bus_device, core); | |
413 | } | |
6bb5cf10 GL |
414 | static inline struct ps3_system_bus_driver * |
415 | ps3_system_bus_dev_to_system_bus_drv(struct ps3_system_bus_device *_dev) | |
416 | { | |
417 | BUG_ON(!_dev); | |
418 | BUG_ON(!_dev->core.driver); | |
419 | return ps3_drv_to_system_bus_drv(_dev->core.driver); | |
420 | } | |
a3d4d643 GL |
421 | |
422 | /** | |
423 | * ps3_system_bus_set_drvdata - | |
424 | * @dev: device structure | |
425 | * @data: Data to set | |
426 | */ | |
427 | ||
03fa68c2 | 428 | static inline void ps3_system_bus_set_drvdata( |
a3d4d643 GL |
429 | struct ps3_system_bus_device *dev, void *data) |
430 | { | |
9f08e9db | 431 | dev_set_drvdata(&dev->core, data); |
a3d4d643 | 432 | } |
03fa68c2 | 433 | static inline void *ps3_system_bus_get_drvdata( |
a3d4d643 GL |
434 | struct ps3_system_bus_device *dev) |
435 | { | |
9f08e9db | 436 | return dev_get_drvdata(&dev->core); |
a3d4d643 GL |
437 | } |
438 | ||
439 | /* These two need global scope for get_dma_ops(). */ | |
440 | ||
441 | extern struct bus_type ps3_system_bus_type; | |
442 | ||
fde5efd0 GL |
443 | /* system manager */ |
444 | ||
66c63b84 GL |
445 | struct ps3_sys_manager_ops { |
446 | struct ps3_system_bus_device *dev; | |
447 | void (*power_off)(struct ps3_system_bus_device *dev); | |
448 | void (*restart)(struct ps3_system_bus_device *dev); | |
449 | }; | |
450 | ||
451 | void ps3_sys_manager_register_ops(const struct ps3_sys_manager_ops *ops); | |
ca052f79 GU |
452 | void __noreturn ps3_sys_manager_power_off(void); |
453 | void __noreturn ps3_sys_manager_restart(void); | |
454 | void __noreturn ps3_sys_manager_halt(void); | |
1c43d265 GL |
455 | int ps3_sys_manager_get_wol(void); |
456 | void ps3_sys_manager_set_wol(int state); | |
fde5efd0 | 457 | |
fbdb3e5b GU |
458 | struct ps3_prealloc { |
459 | const char *name; | |
460 | void *address; | |
461 | unsigned long size; | |
462 | unsigned long align; | |
463 | }; | |
464 | ||
465 | extern struct ps3_prealloc ps3fb_videomemory; | |
32d73318 | 466 | extern struct ps3_prealloc ps3flash_bounce_buffer; |
fbdb3e5b | 467 | |
781749a4 TY |
468 | /* logical performance monitor */ |
469 | ||
470 | /** | |
471 | * enum ps3_lpm_rights - Rigths granted by the system policy module. | |
472 | * | |
473 | * @PS3_LPM_RIGHTS_USE_LPM: The right to use the lpm. | |
474 | * @PS3_LPM_RIGHTS_USE_TB: The right to use the internal trace buffer. | |
475 | */ | |
476 | ||
477 | enum ps3_lpm_rights { | |
478 | PS3_LPM_RIGHTS_USE_LPM = 0x001, | |
479 | PS3_LPM_RIGHTS_USE_TB = 0x100, | |
480 | }; | |
481 | ||
482 | /** | |
483 | * enum ps3_lpm_tb_type - Type of trace buffer lv1 should use. | |
484 | * | |
485 | * @PS3_LPM_TB_TYPE_NONE: Do not use a trace buffer. | |
486 | * @PS3_LPM_RIGHTS_USE_TB: Use the lv1 internal trace buffer. Must have | |
487 | * rights @PS3_LPM_RIGHTS_USE_TB. | |
488 | */ | |
489 | ||
490 | enum ps3_lpm_tb_type { | |
491 | PS3_LPM_TB_TYPE_NONE = 0, | |
492 | PS3_LPM_TB_TYPE_INTERNAL = 1, | |
493 | }; | |
494 | ||
495 | int ps3_lpm_open(enum ps3_lpm_tb_type tb_type, void *tb_cache, | |
496 | u64 tb_cache_size); | |
497 | int ps3_lpm_close(void); | |
498 | int ps3_lpm_copy_tb(unsigned long offset, void *buf, unsigned long count, | |
499 | unsigned long *bytes_copied); | |
500 | int ps3_lpm_copy_tb_to_user(unsigned long offset, void __user *buf, | |
501 | unsigned long count, unsigned long *bytes_copied); | |
502 | void ps3_set_bookmark(u64 bookmark); | |
503 | void ps3_set_pm_bookmark(u64 tag, u64 incident, u64 th_id); | |
504 | int ps3_set_signal(u64 rtas_signal_group, u8 signal_bit, u16 sub_unit, | |
505 | u8 bus_word); | |
506 | ||
507 | u32 ps3_read_phys_ctr(u32 cpu, u32 phys_ctr); | |
508 | void ps3_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val); | |
509 | u32 ps3_read_ctr(u32 cpu, u32 ctr); | |
510 | void ps3_write_ctr(u32 cpu, u32 ctr, u32 val); | |
511 | ||
512 | u32 ps3_read_pm07_control(u32 cpu, u32 ctr); | |
513 | void ps3_write_pm07_control(u32 cpu, u32 ctr, u32 val); | |
514 | u32 ps3_read_pm(u32 cpu, enum pm_reg_name reg); | |
515 | void ps3_write_pm(u32 cpu, enum pm_reg_name reg, u32 val); | |
516 | ||
517 | u32 ps3_get_ctr_size(u32 cpu, u32 phys_ctr); | |
518 | void ps3_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size); | |
519 | ||
520 | void ps3_enable_pm(u32 cpu); | |
521 | void ps3_disable_pm(u32 cpu); | |
522 | void ps3_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask); | |
523 | void ps3_disable_pm_interrupts(u32 cpu); | |
524 | ||
525 | u32 ps3_get_and_clear_pm_interrupts(u32 cpu); | |
526 | void ps3_sync_irq(int node); | |
527 | u32 ps3_get_hw_thread_id(int cpu); | |
528 | u64 ps3_get_spe_id(void *arg); | |
66c63b84 | 529 | |
f58a9d17 | 530 | #endif |