[linux-2.6-block.git] / arch / powerpc / include / asm / processor.h

#ifndef _ASM_POWERPC_PROCESSOR_H
#define _ASM_POWERPC_PROCESSOR_H

/*
 * Copyright (C) 2001 PPC 64 Team, IBM Corp
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <asm/reg.h>

#ifdef CONFIG_VSX
#define TS_FPRWIDTH 2

#ifdef __BIG_ENDIAN__
#define TS_FPROFFSET 0
#define TS_VSRLOWOFFSET 1
#else
#define TS_FPROFFSET 1
#define TS_VSRLOWOFFSET 0
#endif

#else
#define TS_FPRWIDTH 1
#define TS_FPROFFSET 0
#endif

#ifdef CONFIG_PPC64
/* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
#define PPR_PRIORITY 3
#ifdef __ASSEMBLY__
#define INIT_PPR (PPR_PRIORITY << 50)
#else
#define INIT_PPR ((u64)PPR_PRIORITY << 50)
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_PPC64 */

#ifndef __ASSEMBLY__
#include <linux/compiler.h>
#include <linux/cache.h>
#include <asm/ptrace.h>
#include <asm/types.h>
#include <asm/hw_breakpoint.h>

/* We do _not_ want to define new machine types at all, those must die
 * in favor of using the device-tree
 * -- BenH.
 */

/* PREP sub-platform types. Unused */
#define _PREP_Motorola	0x01	/* motorola prep */
#define _PREP_Firm	0x02	/* firmworks prep */
#define _PREP_IBM	0x00	/* ibm prep */
#define _PREP_Bull	0x03	/* bull prep */

/* CHRP sub-platform types. These are arbitrary */
#define _CHRP_Motorola	0x04	/* motorola chrp, the cobra */
#define _CHRP_IBM	0x05	/* IBM chrp, the longtrail and longtrail 2 */
#define _CHRP_Pegasos	0x06	/* Genesi/bplan's Pegasos and Pegasos2 */
#define _CHRP_briq	0x07	/* TotalImpact's briQ */

#if defined(__KERNEL__) && defined(CONFIG_PPC32)

extern int _chrp_type;

#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */

/*
 * Default implementation of macro that returns current
 * instruction pointer ("program counter").
 */
#define current_text_addr() ({ __label__ _l; _l: &&_l;})

/* Macros for adjusting thread priority (hardware multi-threading) */
#define HMT_very_low()   asm volatile("or 31,31,31   # very low priority")
#define HMT_low()	 asm volatile("or 1,1,1	     # low priority")
#define HMT_medium_low() asm volatile("or 6,6,6      # medium low priority")
#define HMT_medium()	 asm volatile("or 2,2,2	     # medium priority")
#define HMT_medium_high() asm volatile("or 5,5,5      # medium high priority")
#define HMT_high()	 asm volatile("or 3,3,3	     # high priority")

#ifdef __KERNEL__

struct task_struct;
void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
void release_thread(struct task_struct *);

#ifdef CONFIG_PPC32

#if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
#error User TASK_SIZE overlaps with KERNEL_START address
#endif
#define TASK_SIZE	(CONFIG_TASK_SIZE)

/* This decides where the kernel will search for a free chunk of vm
 * space during mmap's.
 */
#define TASK_UNMAPPED_BASE	(TASK_SIZE / 8 * 3)
#endif

#ifdef CONFIG_PPC64
/*
 * 64-bit user address space can have multiple limits
 * For now supported values are:
 */
#define TASK_SIZE_64TB  (0x0000400000000000UL)
#define TASK_SIZE_128TB (0x0000800000000000UL)
#define TASK_SIZE_512TB (0x0002000000000000UL)

#ifdef CONFIG_PPC_BOOK3S_64
/*
 * Max value currently used:
 */
#define TASK_SIZE_USER64	TASK_SIZE_512TB
#else
#define TASK_SIZE_USER64	TASK_SIZE_64TB
#endif

/*
 * 32-bit user address space is 4GB - 1 page
 * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
 */
#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))

#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
		TASK_SIZE_USER32 : TASK_SIZE_USER64)
#define TASK_SIZE	  TASK_SIZE_OF(current)
/* This decides where the kernel will search for a free chunk of vm
 * space during mmap's.
 */
#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_128TB / 4))

#define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \
		TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
#endif

/*
 * Initial task size value for user applications. For book3s 64 we start
 * with 128TB and conditionally enable upto 512TB
 */
#ifdef CONFIG_PPC_BOOK3S_64
#define DEFAULT_MAP_WINDOW	((is_32bit_task()) ? \
				 TASK_SIZE_USER32 : TASK_SIZE_128TB)
#else
#define DEFAULT_MAP_WINDOW	TASK_SIZE
#endif

#ifdef __powerpc64__

#ifdef CONFIG_PPC_BOOK3S_64
/* Limit stack to 128TB */
#define STACK_TOP_USER64 TASK_SIZE_128TB
#else
#define STACK_TOP_USER64 TASK_SIZE_USER64
#endif

#define STACK_TOP_USER32 TASK_SIZE_USER32

#define STACK_TOP (is_32bit_task() ? \
		   STACK_TOP_USER32 : STACK_TOP_USER64)

#define STACK_TOP_MAX TASK_SIZE_USER64

#else /* __powerpc64__ */

#define STACK_TOP TASK_SIZE
#define STACK_TOP_MAX	STACK_TOP

#endif /* __powerpc64__ */

typedef struct {
	unsigned long seg;
} mm_segment_t;

#define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET]
#define TS_CKFPR(i) ckfp_state.fpr[i][TS_FPROFFSET]

/* FP and VSX 0-31 register set */
struct thread_fp_state {
	u64	fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));
	u64	fpscr;		/* Floating point status */
};

/* Complete AltiVec register set including VSCR */
struct thread_vr_state {
	vector128	vr[32] __attribute__((aligned(16)));
	vector128	vscr __attribute__((aligned(16)));
};

struct debug_reg {
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
	/*
	 * The following help to manage the use of Debug Control Registers
	 * om the BookE platforms.
	 */
	uint32_t	dbcr0;
	uint32_t	dbcr1;
#ifdef CONFIG_BOOKE
	uint32_t	dbcr2;
#endif
	/*
	 * The stored value of the DBSR register will be the value at the
	 * last debug interrupt. This register can only be read from the
	 * user (will never be written to) and has value while helping to
	 * describe the reason for the last debug trap.  Torez
	 */
	uint32_t	dbsr;
	/*
	 * The following will contain addresses used by debug applications
	 * to help trace and trap on particular address locations.
	 * The bits in the Debug Control Registers above help define which
	 * of the following registers will contain valid data and/or addresses.
	 */
	unsigned long	iac1;
	unsigned long	iac2;
#if CONFIG_PPC_ADV_DEBUG_IACS > 2
	unsigned long	iac3;
	unsigned long	iac4;
#endif
	unsigned long	dac1;
	unsigned long	dac2;
#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
	unsigned long	dvc1;
	unsigned long	dvc2;
#endif
#endif
};

struct thread_struct {
	unsigned long	ksp;		/* Kernel stack pointer */

#ifdef CONFIG_PPC64
	unsigned long	ksp_vsid;
#endif
	struct pt_regs	*regs;		/* Pointer to saved register state */
	mm_segment_t	fs;		/* for get_fs() validation */
#ifdef CONFIG_BOOKE
	/* BookE base exception scratch space; align on cacheline */
	unsigned long	normsave[8] ____cacheline_aligned;
#endif
#ifdef CONFIG_PPC32
	void		*pgdir;		/* root of page-table tree */
	unsigned long	ksp_limit;	/* if ksp <= ksp_limit stack overflow */
#endif
	/* Debug Registers */
	struct debug_reg debug;
	struct thread_fp_state	fp_state;
	struct thread_fp_state	*fp_save_area;
	int		fpexc_mode;	/* floating-point exception mode */
	unsigned int	align_ctl;	/* alignment handling control */
#ifdef CONFIG_PPC64
	unsigned long	start_tb;	/* Start purr when proc switched in */
	unsigned long	accum_tb;	/* Total accumulated purr for process */
#endif
#ifdef CONFIG_HAVE_HW_BREAKPOINT
	struct perf_event *ptrace_bps[HBP_NUM];
	/*
	 * Helps identify source of single-step exception and subsequent
	 * hw-breakpoint enablement
	 */
	struct perf_event *last_hit_ubp;
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
	struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */
	unsigned long	trap_nr;	/* last trap # on this thread */
	u8 load_fp;
#ifdef CONFIG_ALTIVEC
	u8 load_vec;
	struct thread_vr_state vr_state;
	struct thread_vr_state *vr_save_area;
	unsigned long	vrsave;
	int		used_vr;	/* set if process has used altivec */
#endif /* CONFIG_ALTIVEC */
#ifdef CONFIG_VSX
	/* VSR status */
	int		used_vsr;	/* set if process has used VSX */
#endif /* CONFIG_VSX */
#ifdef CONFIG_SPE
	unsigned long	evr[32];	/* upper 32-bits of SPE regs */
	u64		acc;		/* Accumulator */
	unsigned long	spefscr;	/* SPE & eFP status */
	unsigned long	spefscr_last;	/* SPEFSCR value on last prctl
					   call or trap return */
	int		used_spe;	/* set if process has used spe */
#endif /* CONFIG_SPE */
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
	u8	load_tm;
	u64		tm_tfhar;	/* Transaction fail handler addr */
	u64		tm_texasr;	/* Transaction exception & summary */
	u64		tm_tfiar;	/* Transaction fail instr address reg */
	struct pt_regs	ckpt_regs;	/* Checkpointed registers */

	unsigned long	tm_tar;
	unsigned long	tm_ppr;
	unsigned long	tm_dscr;

	/*
	 * Checkpointed FP and VSX 0-31 register set.
	 *
	 * When a transaction is active/signalled/scheduled etc., *regs is the
	 * most recent set of/speculated GPRs with ckpt_regs being the older
	 * checkpointed regs to which we roll back if transaction aborts.
	 *
	 * These are analogous to how ckpt_regs and pt_regs work
	 */
	struct thread_fp_state ckfp_state; /* Checkpointed FP state */
	struct thread_vr_state ckvr_state; /* Checkpointed VR state */
	unsigned long	ckvrsave; /* Checkpointed VRSAVE */
#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
	void*		kvm_shadow_vcpu; /* KVM internal data */
#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
	struct kvm_vcpu	*kvm_vcpu;
#endif
#ifdef CONFIG_PPC64
	unsigned long	dscr;
	unsigned long	fscr;
	/*
	 * This member element dscr_inherit indicates that the process
	 * has explicitly attempted and changed the DSCR register value
	 * for itself. Hence kernel wont use the default CPU DSCR value
	 * contained in the PACA structure anymore during process context
	 * switch. Once this variable is set, this behaviour will also be
	 * inherited to all the children of this process from that point
	 * onwards.
	 */
	int		dscr_inherit;
	unsigned long	ppr;	/* used to save/restore SMT priority */
#endif
#ifdef CONFIG_PPC_BOOK3S_64
	unsigned long	tar;
	unsigned long	ebbrr;
	unsigned long	ebbhr;
	unsigned long	bescr;
	unsigned long	siar;
	unsigned long	sdar;
	unsigned long	sier;
	unsigned long	mmcr2;
	unsigned 	mmcr0;
	unsigned 	used_ebb;
#endif
};

#define ARCH_MIN_TASKALIGN 16

#define INIT_SP		(sizeof(init_stack) + (unsigned long) &init_stack)
#define INIT_SP_LIMIT \
	(_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)

#ifdef CONFIG_SPE
#define SPEFSCR_INIT \
	.spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \
	.spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
#else
#define SPEFSCR_INIT
#endif

#ifdef CONFIG_PPC32
#define INIT_THREAD { \
	.ksp = INIT_SP, \
	.ksp_limit = INIT_SP_LIMIT, \
	.fs = KERNEL_DS, \
	.pgdir = swapper_pg_dir, \
	.fpexc_mode = MSR_FE0 | MSR_FE1, \
	SPEFSCR_INIT \
}
#else
#define INIT_THREAD  { \
	.ksp = INIT_SP, \
	.regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
	.fs = KERNEL_DS, \
	.fpexc_mode = 0, \
	.ppr = INIT_PPR, \
	.fscr = FSCR_TAR | FSCR_EBB \
}
#endif

/*
 * Return saved PC of a blocked thread. For now, this is the "user" PC
 */
#define thread_saved_pc(tsk)    \
        ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)

#define task_pt_regs(tsk)	((struct pt_regs *)(tsk)->thread.regs)

unsigned long get_wchan(struct task_struct *p);

#define KSTK_EIP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
#define KSTK_ESP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)

/* Get/set floating-point exception mode */
#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))

extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);

#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))

extern int get_endian(struct task_struct *tsk, unsigned long adr);
extern int set_endian(struct task_struct *tsk, unsigned int val);

#define GET_UNALIGN_CTL(tsk, adr)	get_unalign_ctl((tsk), (adr))
#define SET_UNALIGN_CTL(tsk, val)	set_unalign_ctl((tsk), (val))

extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);

extern void load_fp_state(struct thread_fp_state *fp);
extern void store_fp_state(struct thread_fp_state *fp);
extern void load_vr_state(struct thread_vr_state *vr);
extern void store_vr_state(struct thread_vr_state *vr);

static inline unsigned int __unpack_fe01(unsigned long msr_bits)
{
	return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
}

static inline unsigned long __pack_fe01(unsigned int fpmode)
{
	return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
}

#ifdef CONFIG_PPC64
#define cpu_relax()	do { HMT_low(); HMT_medium(); barrier(); } while (0)
#else
#define cpu_relax()	barrier()
#endif

/* Check that a certain kernel stack pointer is valid in task_struct p */
int validate_sp(unsigned long sp, struct task_struct *p,
                       unsigned long nbytes);

/*
 * Prefetch macros.
 */
#define ARCH_HAS_PREFETCH
#define ARCH_HAS_PREFETCHW
#define ARCH_HAS_SPINLOCK_PREFETCH

static inline void prefetch(const void *x)
{
	if (unlikely(!x))
		return;

	__asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
}

static inline void prefetchw(const void *x)
{
	if (unlikely(!x))
		return;

	__asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
}

#define spin_lock_prefetch(x)	prefetchw(x)

#define HAVE_ARCH_PICK_MMAP_LAYOUT

#ifdef CONFIG_PPC64
static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
{
	if (is_32)
		return sp & 0x0ffffffffUL;
	return sp;
}
#else
static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
{
	return sp;
}
#endif

extern unsigned long cpuidle_disable;
enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};

extern int powersave_nap;	/* set if nap mode can be used in idle loop */
extern unsigned long power7_nap(int check_irq);
extern unsigned long power7_sleep(void);
extern unsigned long power7_winkle(void);
extern unsigned long power9_idle_stop(unsigned long stop_psscr_val,
				      unsigned long stop_psscr_mask);

extern void flush_instruction_cache(void);
extern void hard_reset_now(void);
extern void poweroff_now(void);
extern int fix_alignment(struct pt_regs *);
extern void cvt_fd(float *from, double *to);
extern void cvt_df(double *from, float *to);
extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);

#ifdef CONFIG_PPC64
/*
 * We handle most unaligned accesses in hardware. On the other hand 
 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
 * powers of 2 writes until it reaches sufficient alignment).
 *
 * Based on this we disable the IP header alignment in network drivers.
 */
#define NET_IP_ALIGN	0
#endif

#endif /* __KERNEL__ */
#endif /* __ASSEMBLY__ */
#endif /* _ASM_POWERPC_PROCESSOR_H */
Commit	Line	Data
9f04b9e3 PM	1	#ifndef _ASM_POWERPC_PROCESSOR_H
9f04b9e3 PM	2	#define _ASM_POWERPC_PROCESSOR_H
1da177e4 LT	3
1da177e4 LT	4	/*
9f04b9e3 PM	5	* Copyright (C) 2001 PPC 64 Team, IBM Corp
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* as published by the Free Software Foundation; either version
	10	* 2 of the License, or (at your option) any later version.
1da177e4	11	*/
1da177e4	12
9f04b9e3	13	#include <asm/reg.h>
1da177e4	14
c6e6771b MN	15	#ifdef CONFIG_VSX
c6e6771b MN	16	#define TS_FPRWIDTH 2
e156bd8a AB	17
	18	#ifdef __BIG_ENDIAN__
	19	#define TS_FPROFFSET 0
	20	#define TS_VSRLOWOFFSET 1
	21	#else
	22	#define TS_FPROFFSET 1
	23	#define TS_VSRLOWOFFSET 0
	24	#endif
	25
c6e6771b	26	#else
9c75a31c	27	#define TS_FPRWIDTH 1
e156bd8a	28	#define TS_FPROFFSET 0
c6e6771b	29	#endif
9c75a31c	30
92779245 HM	31	#ifdef CONFIG_PPC64
	32	/* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
	33	#define PPR_PRIORITY 3
	34	#ifdef __ASSEMBLY__
	35	#define INIT_PPR (PPR_PRIORITY << 50)
	36	#else
	37	#define INIT_PPR ((u64)PPR_PRIORITY << 50)
	38	#endif /* __ASSEMBLY__ */
	39	#endif /* CONFIG_PPC64 */
	40
9f04b9e3 PM	41	#ifndef __ASSEMBLY__
9f04b9e3 PM	42	#include <linux/compiler.h>
1325a684	43	#include <linux/cache.h>
1da177e4 LT	44	#include <asm/ptrace.h>
1da177e4 LT	45	#include <asm/types.h>
9422de3e	46	#include <asm/hw_breakpoint.h>
1da177e4	47
799d6046 PM	48	/* We do _not_ want to define new machine types at all, those must die
	49	* in favor of using the device-tree
	50	* -- BenH.
1da177e4	51	*/
1da177e4	52
933ee711	53	/* PREP sub-platform types. Unused */
1da177e4 LT	54	#define _PREP_Motorola 0x01 /* motorola prep */
	55	#define _PREP_Firm 0x02 /* firmworks prep */
	56	#define _PREP_IBM 0x00 /* ibm prep */
	57	#define _PREP_Bull 0x03 /* bull prep */
	58
799d6046	59	/* CHRP sub-platform types. These are arbitrary */
1da177e4 LT	60	#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
	61	#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
	62	#define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
26c5032e	63	#define _CHRP_briq 0x07 /* TotalImpact's briQ */
1da177e4	64
e8222502 BH	65	#if defined(__KERNEL__) && defined(CONFIG_PPC32)
	66
	67	extern int _chrp_type;
799d6046	68
e8222502 BH	69	#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
e8222502 BH	70
9f04b9e3 PM	71	/*
	72	* Default implementation of macro that returns current
	73	* instruction pointer ("program counter").
	74	*/
	75	#define current_text_addr() ({ __label__ _l; _l: &&_l;})
	76
	77	/* Macros for adjusting thread priority (hardware multi-threading) */
	78	#define HMT_very_low() asm volatile("or 31,31,31 # very low priority")
	79	#define HMT_low() asm volatile("or 1,1,1 # low priority")
	80	#define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority")
	81	#define HMT_medium() asm volatile("or 2,2,2 # medium priority")
	82	#define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority")
	83	#define HMT_high() asm volatile("or 3,3,3 # high priority")
	84
	85	#ifdef __KERNEL__
	86
1da177e4	87	struct task_struct;
9f04b9e3	88	void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
1da177e4 LT	89	void release_thread(struct task_struct *);
1da177e4 LT	90
9f04b9e3	91	#ifdef CONFIG_PPC32
7c4f10b9 RT	92
	93	#if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
	94	#error User TASK_SIZE overlaps with KERNEL_START address
	95	#endif
9f04b9e3 PM	96	#define TASK_SIZE (CONFIG_TASK_SIZE)
9f04b9e3 PM	97
1da177e4 LT	98	/* This decides where the kernel will search for a free chunk of vm
	99	* space during mmap's.
	100	*/
	101	#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
9f04b9e3 PM	102	#endif
	103
	104	#ifdef CONFIG_PPC64
f6eedbba AK	105	/*
	106	* 64-bit user address space can have multiple limits
	107	* For now supported values are:
	108	*/
	109	#define TASK_SIZE_64TB (0x0000400000000000UL)
	110	#define TASK_SIZE_128TB (0x0000800000000000UL)
	111	#define TASK_SIZE_512TB (0x0002000000000000UL)
	112
	113	#ifdef CONFIG_PPC_BOOK3S_64
	114	/*
	115	* Max value currently used:
	116	*/
f4ea6dcb	117	#define TASK_SIZE_USER64 TASK_SIZE_512TB
f6eedbba	118	#else
f4ea6dcb	119	#define TASK_SIZE_USER64 TASK_SIZE_64TB
f6eedbba	120	#endif
9f04b9e3	121
f6eedbba AK	122	/*
f6eedbba AK	123	* 32-bit user address space is 4GB - 1 page
9f04b9e3 PM	124	* (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
	125	*/
	126	#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
	127
82455257	128	#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
9f04b9e3	129	TASK_SIZE_USER32 : TASK_SIZE_USER64)
82455257	130	#define TASK_SIZE TASK_SIZE_OF(current)
9f04b9e3 PM	131	/* This decides where the kernel will search for a free chunk of vm
	132	* space during mmap's.
	133	*/
	134	#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
f4ea6dcb	135	#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_128TB / 4))
9f04b9e3	136
cab175f9	137	#define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \
9f04b9e3 PM	138	TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
9f04b9e3 PM	139	#endif
1da177e4	140
f4ea6dcb AK	141	/*
	142	* Initial task size value for user applications. For book3s 64 we start
	143	* with 128TB and conditionally enable upto 512TB
	144	*/
	145	#ifdef CONFIG_PPC_BOOK3S_64
	146	#define DEFAULT_MAP_WINDOW ((is_32bit_task()) ? \
	147	TASK_SIZE_USER32 : TASK_SIZE_128TB)
	148	#else
	149	#define DEFAULT_MAP_WINDOW TASK_SIZE
	150	#endif
	151
922a70d3 DH	152	#ifdef __powerpc64__
922a70d3 DH	153
61baf155	154	#ifdef CONFIG_PPC_BOOK3S_64
f4ea6dcb AK	155	/* Limit stack to 128TB */
f4ea6dcb AK	156	#define STACK_TOP_USER64 TASK_SIZE_128TB
61baf155 SW	157	#else
	158	#define STACK_TOP_USER64 TASK_SIZE_USER64
	159	#endif
	160
922a70d3 DH	161	#define STACK_TOP_USER32 TASK_SIZE_USER32
922a70d3 DH	162
cab175f9	163	#define STACK_TOP (is_32bit_task() ? \
922a70d3 DH	164	STACK_TOP_USER32 : STACK_TOP_USER64)
922a70d3 DH	165
f4ea6dcb	166	#define STACK_TOP_MAX TASK_SIZE_USER64
922a70d3 DH	167
	168	#else /* __powerpc64__ */
	169
	170	#define STACK_TOP TASK_SIZE
	171	#define STACK_TOP_MAX STACK_TOP
	172
	173	#endif /* __powerpc64__ */
922a70d3	174
1da177e4 LT	175	typedef struct {
	176	unsigned long seg;
	177	} mm_segment_t;
	178
de79f7b9	179	#define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET]
000ec280	180	#define TS_CKFPR(i) ckfp_state.fpr[i][TS_FPROFFSET]
de79f7b9 PM	181
	182	/* FP and VSX 0-31 register set */
	183	struct thread_fp_state {
	184	u64 fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));
	185	u64 fpscr; /* Floating point status */
	186	};
	187
	188	/* Complete AltiVec register set including VSCR */
	189	struct thread_vr_state {
	190	vector128 vr[32] __attribute__((aligned(16)));
	191	vector128 vscr __attribute__((aligned(16)));
	192	};
9c75a31c	193
51ae8d4a	194	struct debug_reg {
99396ac1 DK	195	#ifdef CONFIG_PPC_ADV_DEBUG_REGS
	196	/*
	197	* The following help to manage the use of Debug Control Registers
	198	* om the BookE platforms.
	199	*/
d8899bb2 BB	200	uint32_t dbcr0;
d8899bb2 BB	201	uint32_t dbcr1;
99396ac1	202	#ifdef CONFIG_BOOKE
d8899bb2	203	uint32_t dbcr2;
99396ac1 DK	204	#endif
	205	/*
	206	* The stored value of the DBSR register will be the value at the
	207	* last debug interrupt. This register can only be read from the
	208	* user (will never be written to) and has value while helping to
	209	* describe the reason for the last debug trap. Torez
	210	*/
d8899bb2	211	uint32_t dbsr;
99396ac1 DK	212	/*
	213	* The following will contain addresses used by debug applications
	214	* to help trace and trap on particular address locations.
	215	* The bits in the Debug Control Registers above help define which
	216	* of the following registers will contain valid data and/or addresses.
	217	*/
	218	unsigned long iac1;
	219	unsigned long iac2;
	220	#if CONFIG_PPC_ADV_DEBUG_IACS > 2
	221	unsigned long iac3;
	222	unsigned long iac4;
	223	#endif
	224	unsigned long dac1;
	225	unsigned long dac2;
	226	#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
	227	unsigned long dvc1;
	228	unsigned long dvc2;
	229	#endif
1da177e4	230	#endif
51ae8d4a BB	231	};
	232
	233	struct thread_struct {
	234	unsigned long ksp; /* Kernel stack pointer */
95791988	235
51ae8d4a BB	236	#ifdef CONFIG_PPC64
	237	unsigned long ksp_vsid;
	238	#endif
	239	struct pt_regs regs; / Pointer to saved register state */
	240	mm_segment_t fs; /* for get_fs() validation */
	241	#ifdef CONFIG_BOOKE
	242	/* BookE base exception scratch space; align on cacheline */
	243	unsigned long normsave[8] ____cacheline_aligned;
	244	#endif
	245	#ifdef CONFIG_PPC32
	246	void pgdir; / root of page-table tree */
	247	unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */
	248	#endif
95791988	249	/* Debug Registers */
51ae8d4a	250	struct debug_reg debug;
de79f7b9	251	struct thread_fp_state fp_state;
18461960	252	struct thread_fp_state *fp_save_area;
9f04b9e3	253	int fpexc_mode; /* floating-point exception mode */
e9370ae1	254	unsigned int align_ctl; /* alignment handling control */
9f04b9e3 PM	255	#ifdef CONFIG_PPC64
9f04b9e3 PM	256	unsigned long start_tb; /* Start purr when proc switched in */
027dfac6	257	unsigned long accum_tb; /* Total accumulated purr for process */
fa769d3f	258	#endif
5aae8a53 P	259	#ifdef CONFIG_HAVE_HW_BREAKPOINT
	260	struct perf_event *ptrace_bps[HBP_NUM];
	261	/*
	262	* Helps identify source of single-step exception and subsequent
	263	* hw-breakpoint enablement
	264	*/
	265	struct perf_event *last_hit_ubp;
	266	#endif /* CONFIG_HAVE_HW_BREAKPOINT */
9422de3e	267	struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */
41ab5266	268	unsigned long trap_nr; /* last trap # on this thread */
70fe3d98	269	u8 load_fp;
1da177e4	270	#ifdef CONFIG_ALTIVEC
70fe3d98	271	u8 load_vec;
de79f7b9	272	struct thread_vr_state vr_state;
18461960	273	struct thread_vr_state *vr_save_area;
1da177e4 LT	274	unsigned long vrsave;
	275	int used_vr; /* set if process has used altivec */
	276	#endif /* CONFIG_ALTIVEC */
c6e6771b MN	277	#ifdef CONFIG_VSX
c6e6771b MN	278	/* VSR status */
71528d8b	279	int used_vsr; /* set if process has used VSX */
c6e6771b	280	#endif /* CONFIG_VSX */
1da177e4 LT	281	#ifdef CONFIG_SPE
	282	unsigned long evr[32]; /* upper 32-bits of SPE regs */
	283	u64 acc; /* Accumulator */
	284	unsigned long spefscr; /* SPE & eFP status */
640e9225 JM	285	unsigned long spefscr_last; /* SPEFSCR value on last prctl
640e9225 JM	286	call or trap return */
1da177e4 LT	287	int used_spe; /* set if process has used spe */
1da177e4 LT	288	#endif /* CONFIG_SPE */
f4c3aff2	289	#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
5d176f75	290	u8 load_tm;
f4c3aff2 MN	291	u64 tm_tfhar; /* Transaction fail handler addr */
	292	u64 tm_texasr; /* Transaction exception & summary */
	293	u64 tm_tfiar; /* Transaction fail instr address reg */
f4c3aff2 MN	294	struct pt_regs ckpt_regs; /* Checkpointed registers */
f4c3aff2 MN	295
28e61cc4 MN	296	unsigned long tm_tar;
	297	unsigned long tm_ppr;
	298	unsigned long tm_dscr;
	299
f4c3aff2	300	/*
dc310669	301	* Checkpointed FP and VSX 0-31 register set.
f4c3aff2 MN	302	*
	303	* When a transaction is active/signalled/scheduled etc., *regs is the
	304	* most recent set of/speculated GPRs with ckpt_regs being the older
	305	* checkpointed regs to which we roll back if transaction aborts.
	306	*
dc310669	307	* These are analogous to how ckpt_regs and pt_regs work
f4c3aff2	308	*/
000ec280 CB	309	struct thread_fp_state ckfp_state; /* Checkpointed FP state */
	310	struct thread_vr_state ckvr_state; /* Checkpointed VR state */
	311	unsigned long ckvrsave; /* Checkpointed VRSAVE */
f4c3aff2	312	#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
97e49255 AG	313	#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
	314	void* kvm_shadow_vcpu; /* KVM internal data */
	315	#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
d30f6e48 SW	316	#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
	317	struct kvm_vcpu *kvm_vcpu;
	318	#endif
efcac658 AK	319	#ifdef CONFIG_PPC64
efcac658 AK	320	unsigned long dscr;
152d523e	321	unsigned long fscr;
d3cb06e0 AK	322	/*
	323	* This member element dscr_inherit indicates that the process
	324	* has explicitly attempted and changed the DSCR register value
	325	* for itself. Hence kernel wont use the default CPU DSCR value
	326	* contained in the PACA structure anymore during process context
	327	* switch. Once this variable is set, this behaviour will also be
	328	* inherited to all the children of this process from that point
	329	* onwards.
	330	*/
efcac658	331	int dscr_inherit;
92779245	332	unsigned long ppr; /* used to save/restore SMT priority */
efcac658	333	#endif
2468dcf6 IM	334	#ifdef CONFIG_PPC_BOOK3S_64
2468dcf6 IM	335	unsigned long tar;
9353374b ME	336	unsigned long ebbrr;
	337	unsigned long ebbhr;
	338	unsigned long bescr;
59affcd3 ME	339	unsigned long siar;
	340	unsigned long sdar;
	341	unsigned long sier;
59affcd3	342	unsigned long mmcr2;
330a1eb7 ME	343	unsigned mmcr0;
330a1eb7 ME	344	unsigned used_ebb;
2468dcf6	345	#endif
1da177e4 LT	346	};
	347
	348	#define ARCH_MIN_TASKALIGN 16
	349
	350	#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
85218827 KG	351	#define INIT_SP_LIMIT \
85218827 KG	352	(_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)
1da177e4	353
6a800f36	354	#ifdef CONFIG_SPE
640e9225 JM	355	#define SPEFSCR_INIT \
	356	.spefscr = SPEFSCR_FINVE \| SPEFSCR_FDBZE \| SPEFSCR_FUNFE \| SPEFSCR_FOVFE, \
	357	.spefscr_last = SPEFSCR_FINVE \| SPEFSCR_FDBZE \| SPEFSCR_FUNFE \| SPEFSCR_FOVFE,
6a800f36 LY	358	#else
	359	#define SPEFSCR_INIT
	360	#endif
9f04b9e3 PM	361
9f04b9e3 PM	362	#ifdef CONFIG_PPC32
1da177e4 LT	363	#define INIT_THREAD { \
1da177e4 LT	364	.ksp = INIT_SP, \
85218827	365	.ksp_limit = INIT_SP_LIMIT, \
1da177e4 LT	366	.fs = KERNEL_DS, \
	367	.pgdir = swapper_pg_dir, \
	368	.fpexc_mode = MSR_FE0 \| MSR_FE1, \
6a800f36	369	SPEFSCR_INIT \
1da177e4	370	}
9f04b9e3 PM	371	#else
	372	#define INIT_THREAD { \
	373	.ksp = INIT_SP, \
	374	.regs = (struct pt_regs )INIT_SP - 1, / XXX bogus, I think */ \
	375	.fs = KERNEL_DS, \
ddf5f75a	376	.fpexc_mode = 0, \
92779245	377	.ppr = INIT_PPR, \
b57bd2de	378	.fscr = FSCR_TAR \| FSCR_EBB \
9f04b9e3 PM	379	}
9f04b9e3 PM	380	#endif
1da177e4 LT	381
	382	/*
	383	* Return saved PC of a blocked thread. For now, this is the "user" PC
	384	*/
9f04b9e3 PM	385	#define thread_saved_pc(tsk) \
9f04b9e3 PM	386	((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
1da177e4	387
e5093ff0 SD	388	#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.regs)
e5093ff0 SD	389
1da177e4 LT	390	unsigned long get_wchan(struct task_struct *p);
1da177e4 LT	391
9f04b9e3 PM	392	#define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
9f04b9e3 PM	393	#define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
1da177e4 LT	394
1da177e4 LT	395	/* Get/set floating-point exception mode */
9f04b9e3 PM	396	#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
9f04b9e3 PM	397	#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
1da177e4 LT	398
	399	extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
	400	extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
	401
fab5db97 PM	402	#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
	403	#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
	404
	405	extern int get_endian(struct task_struct *tsk, unsigned long adr);
	406	extern int set_endian(struct task_struct *tsk, unsigned int val);
	407
e9370ae1 PM	408	#define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
	409	#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
	410
	411	extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
	412	extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
	413
18461960 PM	414	extern void load_fp_state(struct thread_fp_state *fp);
	415	extern void store_fp_state(struct thread_fp_state *fp);
	416	extern void load_vr_state(struct thread_vr_state *vr);
	417	extern void store_vr_state(struct thread_vr_state *vr);
	418
9f04b9e3	419	static inline unsigned int __unpack_fe01(unsigned long msr_bits)
1da177e4 LT	420	{
	421	return ((msr_bits & MSR_FE0) >> 10) \| ((msr_bits & MSR_FE1) >> 8);
	422	}
	423
9f04b9e3	424	static inline unsigned long __pack_fe01(unsigned int fpmode)
1da177e4 LT	425	{
	426	return ((fpmode << 10) & MSR_FE0) \| ((fpmode << 8) & MSR_FE1);
	427	}
	428
9f04b9e3 PM	429	#ifdef CONFIG_PPC64
	430	#define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0)
	431	#else
1da177e4	432	#define cpu_relax() barrier()
9f04b9e3	433	#endif
1da177e4	434
2f25194d AB	435	/* Check that a certain kernel stack pointer is valid in task_struct p */
	436	int validate_sp(unsigned long sp, struct task_struct *p,
	437	unsigned long nbytes);
	438
1da177e4 LT	439	/*
	440	* Prefetch macros.
	441	*/
	442	#define ARCH_HAS_PREFETCH
	443	#define ARCH_HAS_PREFETCHW
	444	#define ARCH_HAS_SPINLOCK_PREFETCH
	445
9f04b9e3	446	static inline void prefetch(const void *x)
1da177e4	447	{
9f04b9e3 PM	448	if (unlikely(!x))
	449	return;
	450
	451	__asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
1da177e4 LT	452	}
1da177e4 LT	453
9f04b9e3	454	static inline void prefetchw(const void *x)
1da177e4	455	{
9f04b9e3 PM	456	if (unlikely(!x))
	457	return;
	458
	459	__asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
1da177e4 LT	460	}
	461
	462	#define spin_lock_prefetch(x) prefetchw(x)
	463
9f04b9e3	464	#define HAVE_ARCH_PICK_MMAP_LAYOUT
1da177e4	465
efbda860	466	#ifdef CONFIG_PPC64
2b3f8e87	467	static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
efbda860	468	{
efbda860	469	if (is_32)
2b3f8e87	470	return sp & 0x0ffffffffUL;
efbda860 JB	471	return sp;
	472	}
	473	#else
2b3f8e87	474	static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
efbda860	475	{
2b3f8e87	476	return sp;
efbda860 JB	477	}
	478	#endif
	479
e8bb3e00	480	extern unsigned long cpuidle_disable;
771dae81 DD	481	enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
771dae81 DD	482
ae3a197e	483	extern int powersave_nap; /* set if nap mode can be used in idle loop */
56548fc0	484	extern unsigned long power7_nap(int check_irq);
7cba160a	485	extern unsigned long power7_sleep(void);
77b54e9f	486	extern unsigned long power7_winkle(void);
09206b60 GS	487	extern unsigned long power9_idle_stop(unsigned long stop_psscr_val,
09206b60 GS	488	unsigned long stop_psscr_mask);
bcef83a0	489
ae3a197e DH	490	extern void flush_instruction_cache(void);
	491	extern void hard_reset_now(void);
	492	extern void poweroff_now(void);
	493	extern int fix_alignment(struct pt_regs *);
	494	extern void cvt_fd(float from, double to);
	495	extern void cvt_df(double from, float to);
	496	extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
	497
	498	#ifdef CONFIG_PPC64
	499	/*
	500	* We handle most unaligned accesses in hardware. On the other hand
	501	* unaligned DMA can be very expensive on some ppc64 IO chips (it does
	502	* powers of 2 writes until it reaches sufficient alignment).
	503	*
	504	* Based on this we disable the IP header alignment in network drivers.
	505	*/
	506	#define NET_IP_ALIGN 0
	507	#endif
	508
1da177e4	509	#endif /* __KERNEL__ */
9f04b9e3 PM	510	#endif /* __ASSEMBLY__ */
9f04b9e3 PM	511	#endif /* _ASM_POWERPC_PROCESSOR_H */