[linux-2.6-block.git] / arch / powerpc / include / asm / processor.h

#ifndef _ASM_POWERPC_PROCESSOR_H
#define _ASM_POWERPC_PROCESSOR_H

/*
 * Copyright (C) 2001 PPC 64 Team, IBM Corp
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <asm/reg.h>

#ifdef CONFIG_VSX
#define TS_FPRWIDTH 2

#ifdef __BIG_ENDIAN__
#define TS_FPROFFSET 0
#define TS_VSRLOWOFFSET 1
#else
#define TS_FPROFFSET 1
#define TS_VSRLOWOFFSET 0
#endif

#else
#define TS_FPRWIDTH 1
#define TS_FPROFFSET 0
#endif

#ifdef CONFIG_PPC64
/* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
#define PPR_PRIORITY 3
#ifdef __ASSEMBLY__
#define DEFAULT_PPR (PPR_PRIORITY << 50)
#else
#define DEFAULT_PPR ((u64)PPR_PRIORITY << 50)
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_PPC64 */

#ifndef __ASSEMBLY__
#include <linux/types.h>
#include <asm/thread_info.h>
#include <asm/ptrace.h>
#include <asm/hw_breakpoint.h>

/* We do _not_ want to define new machine types at all, those must die
 * in favor of using the device-tree
 * -- BenH.
 */

/* PREP sub-platform types. Unused */
#define _PREP_Motorola	0x01	/* motorola prep */
#define _PREP_Firm	0x02	/* firmworks prep */
#define _PREP_IBM	0x00	/* ibm prep */
#define _PREP_Bull	0x03	/* bull prep */

/* CHRP sub-platform types. These are arbitrary */
#define _CHRP_Motorola	0x04	/* motorola chrp, the cobra */
#define _CHRP_IBM	0x05	/* IBM chrp, the longtrail and longtrail 2 */
#define _CHRP_Pegasos	0x06	/* Genesi/bplan's Pegasos and Pegasos2 */
#define _CHRP_briq	0x07	/* TotalImpact's briQ */

#if defined(__KERNEL__) && defined(CONFIG_PPC32)

extern int _chrp_type;

#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */

/* Macros for adjusting thread priority (hardware multi-threading) */
#define HMT_very_low()   asm volatile("or 31,31,31   # very low priority")
#define HMT_low()	 asm volatile("or 1,1,1	     # low priority")
#define HMT_medium_low() asm volatile("or 6,6,6      # medium low priority")
#define HMT_medium()	 asm volatile("or 2,2,2	     # medium priority")
#define HMT_medium_high() asm volatile("or 5,5,5      # medium high priority")
#define HMT_high()	 asm volatile("or 3,3,3	     # high priority")

#ifdef __KERNEL__

struct task_struct;
void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
void release_thread(struct task_struct *);

#ifdef CONFIG_PPC32

#if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
#error User TASK_SIZE overlaps with KERNEL_START address
#endif
#define TASK_SIZE	(CONFIG_TASK_SIZE)

/* This decides where the kernel will search for a free chunk of vm
 * space during mmap's.
 */
#define TASK_UNMAPPED_BASE	(TASK_SIZE / 8 * 3)
#endif

#ifdef CONFIG_PPC64
/*
 * 64-bit user address space can have multiple limits
 * For now supported values are:
 */
#define TASK_SIZE_64TB  (0x0000400000000000UL)
#define TASK_SIZE_128TB (0x0000800000000000UL)
#define TASK_SIZE_512TB (0x0002000000000000UL)
#define TASK_SIZE_1PB   (0x0004000000000000UL)
#define TASK_SIZE_2PB   (0x0008000000000000UL)
/*
 * With 52 bits in the address we can support
 * upto 4PB of range.
 */
#define TASK_SIZE_4PB   (0x0010000000000000UL)

/*
 * For now 512TB is only supported with book3s and 64K linux page size.
 */
#if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_PPC_64K_PAGES)
/*
 * Max value currently used:
 */
#define TASK_SIZE_USER64		TASK_SIZE_4PB
#define DEFAULT_MAP_WINDOW_USER64	TASK_SIZE_128TB
#define TASK_CONTEXT_SIZE		TASK_SIZE_512TB
#else
#define TASK_SIZE_USER64		TASK_SIZE_64TB
#define DEFAULT_MAP_WINDOW_USER64	TASK_SIZE_64TB
/*
 * We don't need to allocate extended context ids for 4K page size, because
 * we limit the max effective address on this config to 64TB.
 */
#define TASK_CONTEXT_SIZE		TASK_SIZE_64TB
#endif

/*
 * 32-bit user address space is 4GB - 1 page
 * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
 */
#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))

#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
		TASK_SIZE_USER32 : TASK_SIZE_USER64)
#define TASK_SIZE	  TASK_SIZE_OF(current)
/* This decides where the kernel will search for a free chunk of vm
 * space during mmap's.
 */
#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(DEFAULT_MAP_WINDOW_USER64 / 4))

#define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \
		TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
#endif

/*
 * Initial task size value for user applications. For book3s 64 we start
 * with 128TB and conditionally enable upto 512TB
 */
#ifdef CONFIG_PPC_BOOK3S_64
#define DEFAULT_MAP_WINDOW	((is_32bit_task()) ?			\
				 TASK_SIZE_USER32 : DEFAULT_MAP_WINDOW_USER64)
#else
#define DEFAULT_MAP_WINDOW	TASK_SIZE
#endif

#ifdef __powerpc64__

#define STACK_TOP_USER64 DEFAULT_MAP_WINDOW_USER64
#define STACK_TOP_USER32 TASK_SIZE_USER32

#define STACK_TOP (is_32bit_task() ? \
		   STACK_TOP_USER32 : STACK_TOP_USER64)

#define STACK_TOP_MAX TASK_SIZE_USER64

#else /* __powerpc64__ */

#define STACK_TOP TASK_SIZE
#define STACK_TOP_MAX	STACK_TOP

#endif /* __powerpc64__ */

typedef struct {
	unsigned long seg;
} mm_segment_t;

#define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET]
#define TS_CKFPR(i) ckfp_state.fpr[i][TS_FPROFFSET]

/* FP and VSX 0-31 register set */
struct thread_fp_state {
	u64	fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));
	u64	fpscr;		/* Floating point status */
};

/* Complete AltiVec register set including VSCR */
struct thread_vr_state {
	vector128	vr[32] __attribute__((aligned(16)));
	vector128	vscr __attribute__((aligned(16)));
};

struct debug_reg {
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
	/*
	 * The following help to manage the use of Debug Control Registers
	 * om the BookE platforms.
	 */
	uint32_t	dbcr0;
	uint32_t	dbcr1;
#ifdef CONFIG_BOOKE
	uint32_t	dbcr2;
#endif
	/*
	 * The stored value of the DBSR register will be the value at the
	 * last debug interrupt. This register can only be read from the
	 * user (will never be written to) and has value while helping to
	 * describe the reason for the last debug trap.  Torez
	 */
	uint32_t	dbsr;
	/*
	 * The following will contain addresses used by debug applications
	 * to help trace and trap on particular address locations.
	 * The bits in the Debug Control Registers above help define which
	 * of the following registers will contain valid data and/or addresses.
	 */
	unsigned long	iac1;
	unsigned long	iac2;
#if CONFIG_PPC_ADV_DEBUG_IACS > 2
	unsigned long	iac3;
	unsigned long	iac4;
#endif
	unsigned long	dac1;
	unsigned long	dac2;
#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
	unsigned long	dvc1;
	unsigned long	dvc2;
#endif
#endif
};

struct thread_struct {
	unsigned long	ksp;		/* Kernel stack pointer */

#ifdef CONFIG_PPC64
	unsigned long	ksp_vsid;
#endif
	struct pt_regs	*regs;		/* Pointer to saved register state */
	mm_segment_t	addr_limit;	/* for get_fs() validation */
#ifdef CONFIG_BOOKE
	/* BookE base exception scratch space; align on cacheline */
	unsigned long	normsave[8] ____cacheline_aligned;
#endif
#ifdef CONFIG_PPC32
	void		*pgdir;		/* root of page-table tree */
	unsigned long	ksp_limit;	/* if ksp <= ksp_limit stack overflow */
#endif
	/* Debug Registers */
	struct debug_reg debug;
	struct thread_fp_state	fp_state;
	struct thread_fp_state	*fp_save_area;
	int		fpexc_mode;	/* floating-point exception mode */
	unsigned int	align_ctl;	/* alignment handling control */
#ifdef CONFIG_HAVE_HW_BREAKPOINT
	struct perf_event *ptrace_bps[HBP_NUM];
	/*
	 * Helps identify source of single-step exception and subsequent
	 * hw-breakpoint enablement
	 */
	struct perf_event *last_hit_ubp;
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
	struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */
	unsigned long	trap_nr;	/* last trap # on this thread */
	u8 load_slb;			/* Ages out SLB preload cache entries */
	u8 load_fp;
#ifdef CONFIG_ALTIVEC
	u8 load_vec;
	struct thread_vr_state vr_state;
	struct thread_vr_state *vr_save_area;
	unsigned long	vrsave;
	int		used_vr;	/* set if process has used altivec */
#endif /* CONFIG_ALTIVEC */
#ifdef CONFIG_VSX
	/* VSR status */
	int		used_vsr;	/* set if process has used VSX */
#endif /* CONFIG_VSX */
#ifdef CONFIG_SPE
	unsigned long	evr[32];	/* upper 32-bits of SPE regs */
	u64		acc;		/* Accumulator */
	unsigned long	spefscr;	/* SPE & eFP status */
	unsigned long	spefscr_last;	/* SPEFSCR value on last prctl
					   call or trap return */
	int		used_spe;	/* set if process has used spe */
#endif /* CONFIG_SPE */
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
	u8	load_tm;
	u64		tm_tfhar;	/* Transaction fail handler addr */
	u64		tm_texasr;	/* Transaction exception & summary */
	u64		tm_tfiar;	/* Transaction fail instr address reg */
	struct pt_regs	ckpt_regs;	/* Checkpointed registers */

	unsigned long	tm_tar;
	unsigned long	tm_ppr;
	unsigned long	tm_dscr;

	/*
	 * Checkpointed FP and VSX 0-31 register set.
	 *
	 * When a transaction is active/signalled/scheduled etc., *regs is the
	 * most recent set of/speculated GPRs with ckpt_regs being the older
	 * checkpointed regs to which we roll back if transaction aborts.
	 *
	 * These are analogous to how ckpt_regs and pt_regs work
	 */
	struct thread_fp_state ckfp_state; /* Checkpointed FP state */
	struct thread_vr_state ckvr_state; /* Checkpointed VR state */
	unsigned long	ckvrsave; /* Checkpointed VRSAVE */
#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
#ifdef CONFIG_PPC_MEM_KEYS
	unsigned long	amr;
	unsigned long	iamr;
	unsigned long	uamor;
#endif
#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
	void*		kvm_shadow_vcpu; /* KVM internal data */
#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
	struct kvm_vcpu	*kvm_vcpu;
#endif
#ifdef CONFIG_PPC64
	unsigned long	dscr;
	unsigned long	fscr;
	/*
	 * This member element dscr_inherit indicates that the process
	 * has explicitly attempted and changed the DSCR register value
	 * for itself. Hence kernel wont use the default CPU DSCR value
	 * contained in the PACA structure anymore during process context
	 * switch. Once this variable is set, this behaviour will also be
	 * inherited to all the children of this process from that point
	 * onwards.
	 */
	int		dscr_inherit;
	unsigned long	tidr;
#endif
#ifdef CONFIG_PPC_BOOK3S_64
	unsigned long	tar;
	unsigned long	ebbrr;
	unsigned long	ebbhr;
	unsigned long	bescr;
	unsigned long	siar;
	unsigned long	sdar;
	unsigned long	sier;
	unsigned long	mmcr2;
	unsigned 	mmcr0;

	unsigned 	used_ebb;
	unsigned int	used_vas;
#endif
};

#define ARCH_MIN_TASKALIGN 16

#define INIT_SP		(sizeof(init_stack) + (unsigned long) &init_stack)
#define INIT_SP_LIMIT \
	(_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)

#ifdef CONFIG_SPE
#define SPEFSCR_INIT \
	.spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \
	.spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
#else
#define SPEFSCR_INIT
#endif

#ifdef CONFIG_PPC32
#define INIT_THREAD { \
	.ksp = INIT_SP, \
	.ksp_limit = INIT_SP_LIMIT, \
	.addr_limit = KERNEL_DS, \
	.pgdir = swapper_pg_dir, \
	.fpexc_mode = MSR_FE0 | MSR_FE1, \
	SPEFSCR_INIT \
}
#else
#define INIT_THREAD  { \
	.ksp = INIT_SP, \
	.regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
	.addr_limit = KERNEL_DS, \
	.fpexc_mode = 0, \
	.fscr = FSCR_TAR | FSCR_EBB \
}
#endif

#define task_pt_regs(tsk)	((struct pt_regs *)(tsk)->thread.regs)

unsigned long get_wchan(struct task_struct *p);

#define KSTK_EIP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
#define KSTK_ESP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)

/* Get/set floating-point exception mode */
#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))

extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);

#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))

extern int get_endian(struct task_struct *tsk, unsigned long adr);
extern int set_endian(struct task_struct *tsk, unsigned int val);

#define GET_UNALIGN_CTL(tsk, adr)	get_unalign_ctl((tsk), (adr))
#define SET_UNALIGN_CTL(tsk, val)	set_unalign_ctl((tsk), (val))

extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);

extern void load_fp_state(struct thread_fp_state *fp);
extern void store_fp_state(struct thread_fp_state *fp);
extern void load_vr_state(struct thread_vr_state *vr);
extern void store_vr_state(struct thread_vr_state *vr);

static inline unsigned int __unpack_fe01(unsigned long msr_bits)
{
	return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
}

static inline unsigned long __pack_fe01(unsigned int fpmode)
{
	return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
}

#ifdef CONFIG_PPC64
#define cpu_relax()	do { HMT_low(); HMT_medium(); barrier(); } while (0)

#define spin_begin()	HMT_low()

#define spin_cpu_relax()	barrier()

#define spin_cpu_yield()	spin_cpu_relax()

#define spin_end()	HMT_medium()

#define spin_until_cond(cond)					\
do {								\
	if (unlikely(!(cond))) {				\
		spin_begin();					\
		do {						\
			spin_cpu_relax();			\
		} while (!(cond));				\
		spin_end();					\
	}							\
} while (0)

#else
#define cpu_relax()	barrier()
#endif

/* Check that a certain kernel stack pointer is valid in task_struct p */
int validate_sp(unsigned long sp, struct task_struct *p,
                       unsigned long nbytes);

/*
 * Prefetch macros.
 */
#define ARCH_HAS_PREFETCH
#define ARCH_HAS_PREFETCHW
#define ARCH_HAS_SPINLOCK_PREFETCH

static inline void prefetch(const void *x)
{
	if (unlikely(!x))
		return;

	__asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
}

static inline void prefetchw(const void *x)
{
	if (unlikely(!x))
		return;

	__asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
}

#define spin_lock_prefetch(x)	prefetchw(x)

#define HAVE_ARCH_PICK_MMAP_LAYOUT

#ifdef CONFIG_PPC64
static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
{
	if (is_32)
		return sp & 0x0ffffffffUL;
	return sp;
}
#else
static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
{
	return sp;
}
#endif

extern unsigned long cpuidle_disable;
enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};

extern int powersave_nap;	/* set if nap mode can be used in idle loop */
extern unsigned long power7_idle_insn(unsigned long type); /* PNV_THREAD_NAP/etc*/
extern void power7_idle_type(unsigned long type);
extern unsigned long power9_idle_stop(unsigned long psscr_val);
extern unsigned long power9_offline_stop(unsigned long psscr_val);
extern void power9_idle_type(unsigned long stop_psscr_val,
			      unsigned long stop_psscr_mask);

extern void flush_instruction_cache(void);
extern void hard_reset_now(void);
extern void poweroff_now(void);
extern int fix_alignment(struct pt_regs *);
extern void cvt_fd(float *from, double *to);
extern void cvt_df(double *from, float *to);
extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);

#ifdef CONFIG_PPC64
/*
 * We handle most unaligned accesses in hardware. On the other hand 
 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
 * powers of 2 writes until it reaches sufficient alignment).
 *
 * Based on this we disable the IP header alignment in network drivers.
 */
#define NET_IP_ALIGN	0
#endif

#endif /* __KERNEL__ */
#endif /* __ASSEMBLY__ */
#endif /* _ASM_POWERPC_PROCESSOR_H */
Commit	Line	Data
9f04b9e3 PM	1	#ifndef _ASM_POWERPC_PROCESSOR_H
9f04b9e3 PM	2	#define _ASM_POWERPC_PROCESSOR_H
1da177e4 LT	3
1da177e4 LT	4	/*
9f04b9e3 PM	5	* Copyright (C) 2001 PPC 64 Team, IBM Corp
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* as published by the Free Software Foundation; either version
	10	* 2 of the License, or (at your option) any later version.
1da177e4	11	*/
1da177e4	12
9f04b9e3	13	#include <asm/reg.h>
1da177e4	14
c6e6771b MN	15	#ifdef CONFIG_VSX
c6e6771b MN	16	#define TS_FPRWIDTH 2
e156bd8a AB	17
	18	#ifdef __BIG_ENDIAN__
	19	#define TS_FPROFFSET 0
	20	#define TS_VSRLOWOFFSET 1
	21	#else
	22	#define TS_FPROFFSET 1
	23	#define TS_VSRLOWOFFSET 0
	24	#endif
	25
c6e6771b	26	#else
9c75a31c	27	#define TS_FPRWIDTH 1
e156bd8a	28	#define TS_FPROFFSET 0
c6e6771b	29	#endif
9c75a31c	30
92779245 HM	31	#ifdef CONFIG_PPC64
	32	/* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
	33	#define PPR_PRIORITY 3
	34	#ifdef __ASSEMBLY__
4c2de74c	35	#define DEFAULT_PPR (PPR_PRIORITY << 50)
92779245	36	#else
4c2de74c	37	#define DEFAULT_PPR ((u64)PPR_PRIORITY << 50)
92779245 HM	38	#endif /* __ASSEMBLY__ */
	39	#endif /* CONFIG_PPC64 */
	40
9f04b9e3	41	#ifndef __ASSEMBLY__
62b84265 CL	42	#include <linux/types.h>
62b84265 CL	43	#include <asm/thread_info.h>
1da177e4	44	#include <asm/ptrace.h>
9422de3e	45	#include <asm/hw_breakpoint.h>
1da177e4	46
799d6046 PM	47	/* We do _not_ want to define new machine types at all, those must die
	48	* in favor of using the device-tree
	49	* -- BenH.
1da177e4	50	*/
1da177e4	51
933ee711	52	/* PREP sub-platform types. Unused */
1da177e4 LT	53	#define _PREP_Motorola 0x01 /* motorola prep */
	54	#define _PREP_Firm 0x02 /* firmworks prep */
	55	#define _PREP_IBM 0x00 /* ibm prep */
	56	#define _PREP_Bull 0x03 /* bull prep */
	57
799d6046	58	/* CHRP sub-platform types. These are arbitrary */
1da177e4 LT	59	#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
	60	#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
	61	#define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
26c5032e	62	#define _CHRP_briq 0x07 /* TotalImpact's briQ */
1da177e4	63
e8222502 BH	64	#if defined(__KERNEL__) && defined(CONFIG_PPC32)
	65
	66	extern int _chrp_type;
799d6046	67
e8222502 BH	68	#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
e8222502 BH	69
9f04b9e3 PM	70	/* Macros for adjusting thread priority (hardware multi-threading) */
	71	#define HMT_very_low() asm volatile("or 31,31,31 # very low priority")
	72	#define HMT_low() asm volatile("or 1,1,1 # low priority")
	73	#define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority")
	74	#define HMT_medium() asm volatile("or 2,2,2 # medium priority")
	75	#define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority")
	76	#define HMT_high() asm volatile("or 3,3,3 # high priority")
	77
	78	#ifdef __KERNEL__
	79
1da177e4	80	struct task_struct;
9f04b9e3	81	void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
1da177e4 LT	82	void release_thread(struct task_struct *);
1da177e4 LT	83
9f04b9e3	84	#ifdef CONFIG_PPC32
7c4f10b9 RT	85
	86	#if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
	87	#error User TASK_SIZE overlaps with KERNEL_START address
	88	#endif
9f04b9e3 PM	89	#define TASK_SIZE (CONFIG_TASK_SIZE)
9f04b9e3 PM	90
1da177e4 LT	91	/* This decides where the kernel will search for a free chunk of vm
	92	* space during mmap's.
	93	*/
	94	#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
9f04b9e3 PM	95	#endif
	96
	97	#ifdef CONFIG_PPC64
f6eedbba AK	98	/*
	99	* 64-bit user address space can have multiple limits
	100	* For now supported values are:
	101	*/
	102	#define TASK_SIZE_64TB (0x0000400000000000UL)
	103	#define TASK_SIZE_128TB (0x0000800000000000UL)
	104	#define TASK_SIZE_512TB (0x0002000000000000UL)
c2b4d8b7 AK	105	#define TASK_SIZE_1PB (0x0004000000000000UL)
	106	#define TASK_SIZE_2PB (0x0008000000000000UL)
	107	/*
	108	* With 52 bits in the address we can support
	109	* upto 4PB of range.
	110	*/
	111	#define TASK_SIZE_4PB (0x0010000000000000UL)
f6eedbba	112
92d9dfda AK	113	/*
	114	* For now 512TB is only supported with book3s and 64K linux page size.
	115	*/
	116	#if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_PPC_64K_PAGES)
f6eedbba AK	117	/*
	118	* Max value currently used:
	119	*/
c2b4d8b7	120	#define TASK_SIZE_USER64 TASK_SIZE_4PB
92d9dfda	121	#define DEFAULT_MAP_WINDOW_USER64 TASK_SIZE_128TB
f384796c	122	#define TASK_CONTEXT_SIZE TASK_SIZE_512TB
f6eedbba	123	#else
92d9dfda AK	124	#define TASK_SIZE_USER64 TASK_SIZE_64TB
92d9dfda AK	125	#define DEFAULT_MAP_WINDOW_USER64 TASK_SIZE_64TB
f384796c AK	126	/*
	127	* We don't need to allocate extended context ids for 4K page size, because
	128	* we limit the max effective address on this config to 64TB.
	129	*/
	130	#define TASK_CONTEXT_SIZE TASK_SIZE_64TB
f6eedbba	131	#endif
9f04b9e3	132
f6eedbba AK	133	/*
f6eedbba AK	134	* 32-bit user address space is 4GB - 1 page
9f04b9e3 PM	135	* (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
	136	*/
	137	#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
	138
82455257	139	#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
9f04b9e3	140	TASK_SIZE_USER32 : TASK_SIZE_USER64)
82455257	141	#define TASK_SIZE TASK_SIZE_OF(current)
9f04b9e3 PM	142	/* This decides where the kernel will search for a free chunk of vm
	143	* space during mmap's.
	144	*/
	145	#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
92d9dfda	146	#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(DEFAULT_MAP_WINDOW_USER64 / 4))
9f04b9e3	147
cab175f9	148	#define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \
9f04b9e3 PM	149	TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
9f04b9e3 PM	150	#endif
1da177e4	151
f4ea6dcb AK	152	/*
	153	* Initial task size value for user applications. For book3s 64 we start
	154	* with 128TB and conditionally enable upto 512TB
	155	*/
	156	#ifdef CONFIG_PPC_BOOK3S_64
92d9dfda AK	157	#define DEFAULT_MAP_WINDOW ((is_32bit_task()) ? \
92d9dfda AK	158	TASK_SIZE_USER32 : DEFAULT_MAP_WINDOW_USER64)
f4ea6dcb AK	159	#else
	160	#define DEFAULT_MAP_WINDOW TASK_SIZE
	161	#endif
	162
922a70d3 DH	163	#ifdef __powerpc64__
922a70d3 DH	164
92d9dfda	165	#define STACK_TOP_USER64 DEFAULT_MAP_WINDOW_USER64
922a70d3 DH	166	#define STACK_TOP_USER32 TASK_SIZE_USER32
922a70d3 DH	167
cab175f9	168	#define STACK_TOP (is_32bit_task() ? \
922a70d3 DH	169	STACK_TOP_USER32 : STACK_TOP_USER64)
922a70d3 DH	170
f4ea6dcb	171	#define STACK_TOP_MAX TASK_SIZE_USER64
922a70d3 DH	172
	173	#else /* __powerpc64__ */
	174
	175	#define STACK_TOP TASK_SIZE
	176	#define STACK_TOP_MAX STACK_TOP
	177
	178	#endif /* __powerpc64__ */
922a70d3	179
1da177e4 LT	180	typedef struct {
	181	unsigned long seg;
	182	} mm_segment_t;
	183
de79f7b9	184	#define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET]
000ec280	185	#define TS_CKFPR(i) ckfp_state.fpr[i][TS_FPROFFSET]
de79f7b9 PM	186
	187	/* FP and VSX 0-31 register set */
	188	struct thread_fp_state {
	189	u64 fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));
	190	u64 fpscr; /* Floating point status */
	191	};
	192
	193	/* Complete AltiVec register set including VSCR */
	194	struct thread_vr_state {
	195	vector128 vr[32] __attribute__((aligned(16)));
	196	vector128 vscr __attribute__((aligned(16)));
	197	};
9c75a31c	198
51ae8d4a	199	struct debug_reg {
99396ac1 DK	200	#ifdef CONFIG_PPC_ADV_DEBUG_REGS
	201	/*
	202	* The following help to manage the use of Debug Control Registers
	203	* om the BookE platforms.
	204	*/
d8899bb2 BB	205	uint32_t dbcr0;
d8899bb2 BB	206	uint32_t dbcr1;
99396ac1	207	#ifdef CONFIG_BOOKE
d8899bb2	208	uint32_t dbcr2;
99396ac1 DK	209	#endif
	210	/*
	211	* The stored value of the DBSR register will be the value at the
	212	* last debug interrupt. This register can only be read from the
	213	* user (will never be written to) and has value while helping to
	214	* describe the reason for the last debug trap. Torez
	215	*/
d8899bb2	216	uint32_t dbsr;
99396ac1 DK	217	/*
	218	* The following will contain addresses used by debug applications
	219	* to help trace and trap on particular address locations.
	220	* The bits in the Debug Control Registers above help define which
	221	* of the following registers will contain valid data and/or addresses.
	222	*/
	223	unsigned long iac1;
	224	unsigned long iac2;
	225	#if CONFIG_PPC_ADV_DEBUG_IACS > 2
	226	unsigned long iac3;
	227	unsigned long iac4;
	228	#endif
	229	unsigned long dac1;
	230	unsigned long dac2;
	231	#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
	232	unsigned long dvc1;
	233	unsigned long dvc2;
	234	#endif
1da177e4	235	#endif
51ae8d4a BB	236	};
	237
	238	struct thread_struct {
	239	unsigned long ksp; /* Kernel stack pointer */
95791988	240
51ae8d4a BB	241	#ifdef CONFIG_PPC64
	242	unsigned long ksp_vsid;
	243	#endif
	244	struct pt_regs regs; / Pointer to saved register state */
ba0635fc	245	mm_segment_t addr_limit; /* for get_fs() validation */
51ae8d4a BB	246	#ifdef CONFIG_BOOKE
	247	/* BookE base exception scratch space; align on cacheline */
	248	unsigned long normsave[8] ____cacheline_aligned;
	249	#endif
	250	#ifdef CONFIG_PPC32
	251	void pgdir; / root of page-table tree */
	252	unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */
	253	#endif
95791988	254	/* Debug Registers */
51ae8d4a	255	struct debug_reg debug;
de79f7b9	256	struct thread_fp_state fp_state;
18461960	257	struct thread_fp_state *fp_save_area;
9f04b9e3	258	int fpexc_mode; /* floating-point exception mode */
e9370ae1	259	unsigned int align_ctl; /* alignment handling control */
5aae8a53 P	260	#ifdef CONFIG_HAVE_HW_BREAKPOINT
	261	struct perf_event *ptrace_bps[HBP_NUM];
	262	/*
	263	* Helps identify source of single-step exception and subsequent
	264	* hw-breakpoint enablement
	265	*/
	266	struct perf_event *last_hit_ubp;
	267	#endif /* CONFIG_HAVE_HW_BREAKPOINT */
9422de3e	268	struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */
41ab5266	269	unsigned long trap_nr; /* last trap # on this thread */
5434ae74	270	u8 load_slb; /* Ages out SLB preload cache entries */
70fe3d98	271	u8 load_fp;
1da177e4	272	#ifdef CONFIG_ALTIVEC
70fe3d98	273	u8 load_vec;
de79f7b9	274	struct thread_vr_state vr_state;
18461960	275	struct thread_vr_state *vr_save_area;
1da177e4 LT	276	unsigned long vrsave;
	277	int used_vr; /* set if process has used altivec */
	278	#endif /* CONFIG_ALTIVEC */
c6e6771b MN	279	#ifdef CONFIG_VSX
c6e6771b MN	280	/* VSR status */
71528d8b	281	int used_vsr; /* set if process has used VSX */
c6e6771b	282	#endif /* CONFIG_VSX */
1da177e4 LT	283	#ifdef CONFIG_SPE
	284	unsigned long evr[32]; /* upper 32-bits of SPE regs */
	285	u64 acc; /* Accumulator */
	286	unsigned long spefscr; /* SPE & eFP status */
640e9225 JM	287	unsigned long spefscr_last; /* SPEFSCR value on last prctl
640e9225 JM	288	call or trap return */
1da177e4 LT	289	int used_spe; /* set if process has used spe */
1da177e4 LT	290	#endif /* CONFIG_SPE */
f4c3aff2	291	#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
5d176f75	292	u8 load_tm;
f4c3aff2 MN	293	u64 tm_tfhar; /* Transaction fail handler addr */
	294	u64 tm_texasr; /* Transaction exception & summary */
	295	u64 tm_tfiar; /* Transaction fail instr address reg */
f4c3aff2 MN	296	struct pt_regs ckpt_regs; /* Checkpointed registers */
f4c3aff2 MN	297
28e61cc4 MN	298	unsigned long tm_tar;
	299	unsigned long tm_ppr;
	300	unsigned long tm_dscr;
	301
f4c3aff2	302	/*
dc310669	303	* Checkpointed FP and VSX 0-31 register set.
f4c3aff2 MN	304	*
	305	* When a transaction is active/signalled/scheduled etc., *regs is the
	306	* most recent set of/speculated GPRs with ckpt_regs being the older
	307	* checkpointed regs to which we roll back if transaction aborts.
	308	*
dc310669	309	* These are analogous to how ckpt_regs and pt_regs work
f4c3aff2	310	*/
000ec280 CB	311	struct thread_fp_state ckfp_state; /* Checkpointed FP state */
	312	struct thread_vr_state ckvr_state; /* Checkpointed VR state */
	313	unsigned long ckvrsave; /* Checkpointed VRSAVE */
f4c3aff2	314	#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
06bb53b3 RP	315	#ifdef CONFIG_PPC_MEM_KEYS
	316	unsigned long amr;
	317	unsigned long iamr;
	318	unsigned long uamor;
	319	#endif
97e49255 AG	320	#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
	321	void* kvm_shadow_vcpu; /* KVM internal data */
	322	#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
d30f6e48 SW	323	#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
	324	struct kvm_vcpu *kvm_vcpu;
	325	#endif
efcac658 AK	326	#ifdef CONFIG_PPC64
efcac658 AK	327	unsigned long dscr;
152d523e	328	unsigned long fscr;
d3cb06e0 AK	329	/*
	330	* This member element dscr_inherit indicates that the process
	331	* has explicitly attempted and changed the DSCR register value
	332	* for itself. Hence kernel wont use the default CPU DSCR value
	333	* contained in the PACA structure anymore during process context
	334	* switch. Once this variable is set, this behaviour will also be
	335	* inherited to all the children of this process from that point
	336	* onwards.
	337	*/
efcac658	338	int dscr_inherit;
ec233ede	339	unsigned long tidr;
efcac658	340	#endif
2468dcf6 IM	341	#ifdef CONFIG_PPC_BOOK3S_64
2468dcf6 IM	342	unsigned long tar;
9353374b ME	343	unsigned long ebbrr;
	344	unsigned long ebbhr;
	345	unsigned long bescr;
59affcd3 ME	346	unsigned long siar;
	347	unsigned long sdar;
	348	unsigned long sier;
59affcd3	349	unsigned long mmcr2;
330a1eb7	350	unsigned mmcr0;
9d2a4d71	351
330a1eb7	352	unsigned used_ebb;
9d2a4d71	353	unsigned int used_vas;
2468dcf6	354	#endif
1da177e4 LT	355	};
	356
	357	#define ARCH_MIN_TASKALIGN 16
	358
	359	#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
85218827 KG	360	#define INIT_SP_LIMIT \
85218827 KG	361	(_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)
1da177e4	362
6a800f36	363	#ifdef CONFIG_SPE
640e9225 JM	364	#define SPEFSCR_INIT \
	365	.spefscr = SPEFSCR_FINVE \| SPEFSCR_FDBZE \| SPEFSCR_FUNFE \| SPEFSCR_FOVFE, \
	366	.spefscr_last = SPEFSCR_FINVE \| SPEFSCR_FDBZE \| SPEFSCR_FUNFE \| SPEFSCR_FOVFE,
6a800f36 LY	367	#else
	368	#define SPEFSCR_INIT
	369	#endif
9f04b9e3 PM	370
9f04b9e3 PM	371	#ifdef CONFIG_PPC32
1da177e4 LT	372	#define INIT_THREAD { \
1da177e4 LT	373	.ksp = INIT_SP, \
85218827	374	.ksp_limit = INIT_SP_LIMIT, \
ba0635fc	375	.addr_limit = KERNEL_DS, \
1da177e4 LT	376	.pgdir = swapper_pg_dir, \
1da177e4 LT	377	.fpexc_mode = MSR_FE0 \| MSR_FE1, \
6a800f36	378	SPEFSCR_INIT \
1da177e4	379	}
9f04b9e3 PM	380	#else
	381	#define INIT_THREAD { \
	382	.ksp = INIT_SP, \
	383	.regs = (struct pt_regs )INIT_SP - 1, / XXX bogus, I think */ \
ba0635fc	384	.addr_limit = KERNEL_DS, \
ddf5f75a	385	.fpexc_mode = 0, \
b57bd2de	386	.fscr = FSCR_TAR \| FSCR_EBB \
9f04b9e3 PM	387	}
9f04b9e3 PM	388	#endif
1da177e4	389
e5093ff0 SD	390	#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.regs)
e5093ff0 SD	391
1da177e4 LT	392	unsigned long get_wchan(struct task_struct *p);
1da177e4 LT	393
9f04b9e3 PM	394	#define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
9f04b9e3 PM	395	#define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
1da177e4 LT	396
1da177e4 LT	397	/* Get/set floating-point exception mode */
9f04b9e3 PM	398	#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
9f04b9e3 PM	399	#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
1da177e4 LT	400
	401	extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
	402	extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
	403
fab5db97 PM	404	#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
	405	#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
	406
	407	extern int get_endian(struct task_struct *tsk, unsigned long adr);
	408	extern int set_endian(struct task_struct *tsk, unsigned int val);
	409
e9370ae1 PM	410	#define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
	411	#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
	412
	413	extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
	414	extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
	415
18461960 PM	416	extern void load_fp_state(struct thread_fp_state *fp);
	417	extern void store_fp_state(struct thread_fp_state *fp);
	418	extern void load_vr_state(struct thread_vr_state *vr);
	419	extern void store_vr_state(struct thread_vr_state *vr);
	420
9f04b9e3	421	static inline unsigned int __unpack_fe01(unsigned long msr_bits)
1da177e4 LT	422	{
	423	return ((msr_bits & MSR_FE0) >> 10) \| ((msr_bits & MSR_FE1) >> 8);
	424	}
	425
9f04b9e3	426	static inline unsigned long __pack_fe01(unsigned int fpmode)
1da177e4 LT	427	{
	428	return ((fpmode << 10) & MSR_FE0) \| ((fpmode << 8) & MSR_FE1);
	429	}
	430
9f04b9e3 PM	431	#ifdef CONFIG_PPC64
9f04b9e3 PM	432	#define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0)
ede8e2bb NP	433
	434	#define spin_begin() HMT_low()
	435
	436	#define spin_cpu_relax() barrier()
	437
	438	#define spin_cpu_yield() spin_cpu_relax()
	439
	440	#define spin_end() HMT_medium()
	441
	442	#define spin_until_cond(cond) \
	443	do { \
	444	if (unlikely(!(cond))) { \
	445	spin_begin(); \
	446	do { \
	447	spin_cpu_relax(); \
	448	} while (!(cond)); \
	449	spin_end(); \
	450	} \
	451	} while (0)
	452
9f04b9e3	453	#else
1da177e4	454	#define cpu_relax() barrier()
9f04b9e3	455	#endif
1da177e4	456
2f25194d AB	457	/* Check that a certain kernel stack pointer is valid in task_struct p */
	458	int validate_sp(unsigned long sp, struct task_struct *p,
	459	unsigned long nbytes);
	460
1da177e4 LT	461	/*
	462	* Prefetch macros.
	463	*/
	464	#define ARCH_HAS_PREFETCH
	465	#define ARCH_HAS_PREFETCHW
	466	#define ARCH_HAS_SPINLOCK_PREFETCH
	467
9f04b9e3	468	static inline void prefetch(const void *x)
1da177e4	469	{
9f04b9e3 PM	470	if (unlikely(!x))
	471	return;
	472
	473	__asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
1da177e4 LT	474	}
1da177e4 LT	475
9f04b9e3	476	static inline void prefetchw(const void *x)
1da177e4	477	{
9f04b9e3 PM	478	if (unlikely(!x))
	479	return;
	480
	481	__asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
1da177e4 LT	482	}
	483
	484	#define spin_lock_prefetch(x) prefetchw(x)
	485
9f04b9e3	486	#define HAVE_ARCH_PICK_MMAP_LAYOUT
1da177e4	487
efbda860	488	#ifdef CONFIG_PPC64
2b3f8e87	489	static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
efbda860	490	{
efbda860	491	if (is_32)
2b3f8e87	492	return sp & 0x0ffffffffUL;
efbda860 JB	493	return sp;
	494	}
	495	#else
2b3f8e87	496	static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
efbda860	497	{
2b3f8e87	498	return sp;
efbda860 JB	499	}
	500	#endif
	501
e8bb3e00	502	extern unsigned long cpuidle_disable;
771dae81 DD	503	enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
771dae81 DD	504
ae3a197e	505	extern int powersave_nap; /* set if nap mode can be used in idle loop */
2201f994 NP	506	extern unsigned long power7_idle_insn(unsigned long type); /* PNV_THREAD_NAP/etc*/
	507	extern void power7_idle_type(unsigned long type);
	508	extern unsigned long power9_idle_stop(unsigned long psscr_val);
3d4fbffd	509	extern unsigned long power9_offline_stop(unsigned long psscr_val);
2201f994 NP	510	extern void power9_idle_type(unsigned long stop_psscr_val,
2201f994 NP	511	unsigned long stop_psscr_mask);
bcef83a0	512
ae3a197e DH	513	extern void flush_instruction_cache(void);
	514	extern void hard_reset_now(void);
	515	extern void poweroff_now(void);
	516	extern int fix_alignment(struct pt_regs *);
	517	extern void cvt_fd(float from, double to);
	518	extern void cvt_df(double from, float to);
	519	extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
	520
	521	#ifdef CONFIG_PPC64
	522	/*
	523	* We handle most unaligned accesses in hardware. On the other hand
	524	* unaligned DMA can be very expensive on some ppc64 IO chips (it does
	525	* powers of 2 writes until it reaches sufficient alignment).
	526	*
	527	* Based on this we disable the IP header alignment in network drivers.
	528	*/
	529	#define NET_IP_ALIGN 0
	530	#endif
	531
1da177e4	532	#endif /* __KERNEL__ */
9f04b9e3 PM	533	#endif /* __ASSEMBLY__ */
9f04b9e3 PM	534	#endif /* _ASM_POWERPC_PROCESSOR_H */