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9f04b9e3 PM |
1 | #ifndef _ASM_POWERPC_PROCESSOR_H |
2 | #define _ASM_POWERPC_PROCESSOR_H | |
1da177e4 LT |
3 | |
4 | /* | |
9f04b9e3 PM |
5 | * Copyright (C) 2001 PPC 64 Team, IBM Corp |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
1da177e4 | 11 | */ |
1da177e4 | 12 | |
9f04b9e3 | 13 | #include <asm/reg.h> |
1da177e4 | 14 | |
c6e6771b MN |
15 | #ifdef CONFIG_VSX |
16 | #define TS_FPRWIDTH 2 | |
e156bd8a AB |
17 | |
18 | #ifdef __BIG_ENDIAN__ | |
19 | #define TS_FPROFFSET 0 | |
20 | #define TS_VSRLOWOFFSET 1 | |
21 | #else | |
22 | #define TS_FPROFFSET 1 | |
23 | #define TS_VSRLOWOFFSET 0 | |
24 | #endif | |
25 | ||
c6e6771b | 26 | #else |
9c75a31c | 27 | #define TS_FPRWIDTH 1 |
e156bd8a | 28 | #define TS_FPROFFSET 0 |
c6e6771b | 29 | #endif |
9c75a31c | 30 | |
92779245 HM |
31 | #ifdef CONFIG_PPC64 |
32 | /* Default SMT priority is set to 3. Use 11- 13bits to save priority. */ | |
33 | #define PPR_PRIORITY 3 | |
34 | #ifdef __ASSEMBLY__ | |
4c2de74c | 35 | #define DEFAULT_PPR (PPR_PRIORITY << 50) |
92779245 | 36 | #else |
4c2de74c | 37 | #define DEFAULT_PPR ((u64)PPR_PRIORITY << 50) |
92779245 HM |
38 | #endif /* __ASSEMBLY__ */ |
39 | #endif /* CONFIG_PPC64 */ | |
40 | ||
9f04b9e3 | 41 | #ifndef __ASSEMBLY__ |
62b84265 | 42 | #include <linux/types.h> |
37333040 | 43 | #include <linux/thread_info.h> |
1da177e4 | 44 | #include <asm/ptrace.h> |
9422de3e | 45 | #include <asm/hw_breakpoint.h> |
1da177e4 | 46 | |
799d6046 PM |
47 | /* We do _not_ want to define new machine types at all, those must die |
48 | * in favor of using the device-tree | |
49 | * -- BenH. | |
1da177e4 | 50 | */ |
1da177e4 | 51 | |
933ee711 | 52 | /* PREP sub-platform types. Unused */ |
1da177e4 LT |
53 | #define _PREP_Motorola 0x01 /* motorola prep */ |
54 | #define _PREP_Firm 0x02 /* firmworks prep */ | |
55 | #define _PREP_IBM 0x00 /* ibm prep */ | |
56 | #define _PREP_Bull 0x03 /* bull prep */ | |
57 | ||
799d6046 | 58 | /* CHRP sub-platform types. These are arbitrary */ |
1da177e4 LT |
59 | #define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */ |
60 | #define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ | |
61 | #define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */ | |
26c5032e | 62 | #define _CHRP_briq 0x07 /* TotalImpact's briQ */ |
1da177e4 | 63 | |
e8222502 BH |
64 | #if defined(__KERNEL__) && defined(CONFIG_PPC32) |
65 | ||
66 | extern int _chrp_type; | |
799d6046 | 67 | |
e8222502 BH |
68 | #endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */ |
69 | ||
9f04b9e3 PM |
70 | /* Macros for adjusting thread priority (hardware multi-threading) */ |
71 | #define HMT_very_low() asm volatile("or 31,31,31 # very low priority") | |
72 | #define HMT_low() asm volatile("or 1,1,1 # low priority") | |
73 | #define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority") | |
74 | #define HMT_medium() asm volatile("or 2,2,2 # medium priority") | |
75 | #define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority") | |
76 | #define HMT_high() asm volatile("or 3,3,3 # high priority") | |
77 | ||
78 | #ifdef __KERNEL__ | |
79 | ||
9f04b9e3 | 80 | #ifdef CONFIG_PPC64 |
92ab45c5 | 81 | #include <asm/task_size_64.h> |
f4ea6dcb | 82 | #else |
92ab45c5 | 83 | #include <asm/task_size_32.h> |
f4ea6dcb AK |
84 | #endif |
85 | ||
92ab45c5 CL |
86 | struct task_struct; |
87 | void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp); | |
88 | void release_thread(struct task_struct *); | |
922a70d3 | 89 | |
1da177e4 LT |
90 | typedef struct { |
91 | unsigned long seg; | |
92 | } mm_segment_t; | |
93 | ||
de79f7b9 | 94 | #define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET] |
000ec280 | 95 | #define TS_CKFPR(i) ckfp_state.fpr[i][TS_FPROFFSET] |
de79f7b9 PM |
96 | |
97 | /* FP and VSX 0-31 register set */ | |
98 | struct thread_fp_state { | |
99 | u64 fpr[32][TS_FPRWIDTH] __attribute__((aligned(16))); | |
100 | u64 fpscr; /* Floating point status */ | |
101 | }; | |
102 | ||
103 | /* Complete AltiVec register set including VSCR */ | |
104 | struct thread_vr_state { | |
105 | vector128 vr[32] __attribute__((aligned(16))); | |
106 | vector128 vscr __attribute__((aligned(16))); | |
107 | }; | |
9c75a31c | 108 | |
51ae8d4a | 109 | struct debug_reg { |
99396ac1 DK |
110 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
111 | /* | |
112 | * The following help to manage the use of Debug Control Registers | |
113 | * om the BookE platforms. | |
114 | */ | |
d8899bb2 BB |
115 | uint32_t dbcr0; |
116 | uint32_t dbcr1; | |
99396ac1 | 117 | #ifdef CONFIG_BOOKE |
d8899bb2 | 118 | uint32_t dbcr2; |
99396ac1 DK |
119 | #endif |
120 | /* | |
121 | * The stored value of the DBSR register will be the value at the | |
122 | * last debug interrupt. This register can only be read from the | |
123 | * user (will never be written to) and has value while helping to | |
124 | * describe the reason for the last debug trap. Torez | |
125 | */ | |
d8899bb2 | 126 | uint32_t dbsr; |
99396ac1 DK |
127 | /* |
128 | * The following will contain addresses used by debug applications | |
129 | * to help trace and trap on particular address locations. | |
130 | * The bits in the Debug Control Registers above help define which | |
131 | * of the following registers will contain valid data and/or addresses. | |
132 | */ | |
133 | unsigned long iac1; | |
134 | unsigned long iac2; | |
135 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | |
136 | unsigned long iac3; | |
137 | unsigned long iac4; | |
138 | #endif | |
139 | unsigned long dac1; | |
140 | unsigned long dac2; | |
141 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 | |
142 | unsigned long dvc1; | |
143 | unsigned long dvc2; | |
144 | #endif | |
1da177e4 | 145 | #endif |
51ae8d4a BB |
146 | }; |
147 | ||
148 | struct thread_struct { | |
149 | unsigned long ksp; /* Kernel stack pointer */ | |
95791988 | 150 | |
51ae8d4a BB |
151 | #ifdef CONFIG_PPC64 |
152 | unsigned long ksp_vsid; | |
153 | #endif | |
154 | struct pt_regs *regs; /* Pointer to saved register state */ | |
ba0635fc | 155 | mm_segment_t addr_limit; /* for get_fs() validation */ |
51ae8d4a BB |
156 | #ifdef CONFIG_BOOKE |
157 | /* BookE base exception scratch space; align on cacheline */ | |
158 | unsigned long normsave[8] ____cacheline_aligned; | |
159 | #endif | |
160 | #ifdef CONFIG_PPC32 | |
161 | void *pgdir; /* root of page-table tree */ | |
162 | unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */ | |
0df977ea CL |
163 | #ifdef CONFIG_PPC_RTAS |
164 | unsigned long rtas_sp; /* stack pointer for when in RTAS */ | |
165 | #endif | |
a68c31fc CL |
166 | #endif |
167 | #if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP) | |
168 | unsigned long kuap; /* opened segments for user access */ | |
51ae8d4a | 169 | #endif |
95791988 | 170 | /* Debug Registers */ |
51ae8d4a | 171 | struct debug_reg debug; |
de79f7b9 | 172 | struct thread_fp_state fp_state; |
18461960 | 173 | struct thread_fp_state *fp_save_area; |
9f04b9e3 | 174 | int fpexc_mode; /* floating-point exception mode */ |
e9370ae1 | 175 | unsigned int align_ctl; /* alignment handling control */ |
5aae8a53 P |
176 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
177 | struct perf_event *ptrace_bps[HBP_NUM]; | |
178 | /* | |
179 | * Helps identify source of single-step exception and subsequent | |
180 | * hw-breakpoint enablement | |
181 | */ | |
182 | struct perf_event *last_hit_ubp; | |
183 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
9422de3e | 184 | struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */ |
41ab5266 | 185 | unsigned long trap_nr; /* last trap # on this thread */ |
5434ae74 | 186 | u8 load_slb; /* Ages out SLB preload cache entries */ |
70fe3d98 | 187 | u8 load_fp; |
1da177e4 | 188 | #ifdef CONFIG_ALTIVEC |
70fe3d98 | 189 | u8 load_vec; |
de79f7b9 | 190 | struct thread_vr_state vr_state; |
18461960 | 191 | struct thread_vr_state *vr_save_area; |
1da177e4 LT |
192 | unsigned long vrsave; |
193 | int used_vr; /* set if process has used altivec */ | |
194 | #endif /* CONFIG_ALTIVEC */ | |
c6e6771b MN |
195 | #ifdef CONFIG_VSX |
196 | /* VSR status */ | |
71528d8b | 197 | int used_vsr; /* set if process has used VSX */ |
c6e6771b | 198 | #endif /* CONFIG_VSX */ |
1da177e4 LT |
199 | #ifdef CONFIG_SPE |
200 | unsigned long evr[32]; /* upper 32-bits of SPE regs */ | |
201 | u64 acc; /* Accumulator */ | |
202 | unsigned long spefscr; /* SPE & eFP status */ | |
640e9225 JM |
203 | unsigned long spefscr_last; /* SPEFSCR value on last prctl |
204 | call or trap return */ | |
1da177e4 LT |
205 | int used_spe; /* set if process has used spe */ |
206 | #endif /* CONFIG_SPE */ | |
f4c3aff2 | 207 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
5d176f75 | 208 | u8 load_tm; |
f4c3aff2 MN |
209 | u64 tm_tfhar; /* Transaction fail handler addr */ |
210 | u64 tm_texasr; /* Transaction exception & summary */ | |
211 | u64 tm_tfiar; /* Transaction fail instr address reg */ | |
f4c3aff2 MN |
212 | struct pt_regs ckpt_regs; /* Checkpointed registers */ |
213 | ||
28e61cc4 MN |
214 | unsigned long tm_tar; |
215 | unsigned long tm_ppr; | |
216 | unsigned long tm_dscr; | |
217 | ||
f4c3aff2 | 218 | /* |
dc310669 | 219 | * Checkpointed FP and VSX 0-31 register set. |
f4c3aff2 MN |
220 | * |
221 | * When a transaction is active/signalled/scheduled etc., *regs is the | |
222 | * most recent set of/speculated GPRs with ckpt_regs being the older | |
223 | * checkpointed regs to which we roll back if transaction aborts. | |
224 | * | |
dc310669 | 225 | * These are analogous to how ckpt_regs and pt_regs work |
f4c3aff2 | 226 | */ |
000ec280 CB |
227 | struct thread_fp_state ckfp_state; /* Checkpointed FP state */ |
228 | struct thread_vr_state ckvr_state; /* Checkpointed VR state */ | |
229 | unsigned long ckvrsave; /* Checkpointed VRSAVE */ | |
f4c3aff2 | 230 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ |
06bb53b3 RP |
231 | #ifdef CONFIG_PPC_MEM_KEYS |
232 | unsigned long amr; | |
233 | unsigned long iamr; | |
234 | unsigned long uamor; | |
235 | #endif | |
97e49255 AG |
236 | #ifdef CONFIG_KVM_BOOK3S_32_HANDLER |
237 | void* kvm_shadow_vcpu; /* KVM internal data */ | |
238 | #endif /* CONFIG_KVM_BOOK3S_32_HANDLER */ | |
d30f6e48 SW |
239 | #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE) |
240 | struct kvm_vcpu *kvm_vcpu; | |
241 | #endif | |
efcac658 AK |
242 | #ifdef CONFIG_PPC64 |
243 | unsigned long dscr; | |
152d523e | 244 | unsigned long fscr; |
d3cb06e0 AK |
245 | /* |
246 | * This member element dscr_inherit indicates that the process | |
247 | * has explicitly attempted and changed the DSCR register value | |
248 | * for itself. Hence kernel wont use the default CPU DSCR value | |
249 | * contained in the PACA structure anymore during process context | |
250 | * switch. Once this variable is set, this behaviour will also be | |
251 | * inherited to all the children of this process from that point | |
252 | * onwards. | |
253 | */ | |
efcac658 | 254 | int dscr_inherit; |
ec233ede | 255 | unsigned long tidr; |
efcac658 | 256 | #endif |
2468dcf6 IM |
257 | #ifdef CONFIG_PPC_BOOK3S_64 |
258 | unsigned long tar; | |
9353374b ME |
259 | unsigned long ebbrr; |
260 | unsigned long ebbhr; | |
261 | unsigned long bescr; | |
59affcd3 ME |
262 | unsigned long siar; |
263 | unsigned long sdar; | |
264 | unsigned long sier; | |
59affcd3 | 265 | unsigned long mmcr2; |
330a1eb7 | 266 | unsigned mmcr0; |
9d2a4d71 | 267 | |
330a1eb7 | 268 | unsigned used_ebb; |
9d2a4d71 | 269 | unsigned int used_vas; |
2468dcf6 | 270 | #endif |
1da177e4 LT |
271 | }; |
272 | ||
273 | #define ARCH_MIN_TASKALIGN 16 | |
274 | ||
275 | #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) | |
a7916a1d | 276 | #define INIT_SP_LIMIT ((unsigned long)&init_stack) |
1da177e4 | 277 | |
6a800f36 | 278 | #ifdef CONFIG_SPE |
640e9225 JM |
279 | #define SPEFSCR_INIT \ |
280 | .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \ | |
281 | .spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, | |
6a800f36 LY |
282 | #else |
283 | #define SPEFSCR_INIT | |
284 | #endif | |
9f04b9e3 PM |
285 | |
286 | #ifdef CONFIG_PPC32 | |
1da177e4 LT |
287 | #define INIT_THREAD { \ |
288 | .ksp = INIT_SP, \ | |
85218827 | 289 | .ksp_limit = INIT_SP_LIMIT, \ |
ba0635fc | 290 | .addr_limit = KERNEL_DS, \ |
1da177e4 LT |
291 | .pgdir = swapper_pg_dir, \ |
292 | .fpexc_mode = MSR_FE0 | MSR_FE1, \ | |
6a800f36 | 293 | SPEFSCR_INIT \ |
1da177e4 | 294 | } |
9f04b9e3 PM |
295 | #else |
296 | #define INIT_THREAD { \ | |
297 | .ksp = INIT_SP, \ | |
298 | .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \ | |
ba0635fc | 299 | .addr_limit = KERNEL_DS, \ |
ddf5f75a | 300 | .fpexc_mode = 0, \ |
b57bd2de | 301 | .fscr = FSCR_TAR | FSCR_EBB \ |
9f04b9e3 PM |
302 | } |
303 | #endif | |
1da177e4 | 304 | |
e5093ff0 SD |
305 | #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.regs) |
306 | ||
1da177e4 LT |
307 | unsigned long get_wchan(struct task_struct *p); |
308 | ||
9f04b9e3 PM |
309 | #define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0) |
310 | #define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0) | |
1da177e4 LT |
311 | |
312 | /* Get/set floating-point exception mode */ | |
9f04b9e3 PM |
313 | #define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr)) |
314 | #define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val)) | |
1da177e4 LT |
315 | |
316 | extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr); | |
317 | extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val); | |
318 | ||
fab5db97 PM |
319 | #define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr)) |
320 | #define SET_ENDIAN(tsk, val) set_endian((tsk), (val)) | |
321 | ||
322 | extern int get_endian(struct task_struct *tsk, unsigned long adr); | |
323 | extern int set_endian(struct task_struct *tsk, unsigned int val); | |
324 | ||
e9370ae1 PM |
325 | #define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr)) |
326 | #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) | |
327 | ||
328 | extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr); | |
329 | extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val); | |
330 | ||
18461960 PM |
331 | extern void load_fp_state(struct thread_fp_state *fp); |
332 | extern void store_fp_state(struct thread_fp_state *fp); | |
333 | extern void load_vr_state(struct thread_vr_state *vr); | |
334 | extern void store_vr_state(struct thread_vr_state *vr); | |
335 | ||
9f04b9e3 | 336 | static inline unsigned int __unpack_fe01(unsigned long msr_bits) |
1da177e4 LT |
337 | { |
338 | return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8); | |
339 | } | |
340 | ||
9f04b9e3 | 341 | static inline unsigned long __pack_fe01(unsigned int fpmode) |
1da177e4 LT |
342 | { |
343 | return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1); | |
344 | } | |
345 | ||
9f04b9e3 PM |
346 | #ifdef CONFIG_PPC64 |
347 | #define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0) | |
ede8e2bb NP |
348 | |
349 | #define spin_begin() HMT_low() | |
350 | ||
351 | #define spin_cpu_relax() barrier() | |
352 | ||
353 | #define spin_cpu_yield() spin_cpu_relax() | |
354 | ||
355 | #define spin_end() HMT_medium() | |
356 | ||
357 | #define spin_until_cond(cond) \ | |
358 | do { \ | |
359 | if (unlikely(!(cond))) { \ | |
360 | spin_begin(); \ | |
361 | do { \ | |
362 | spin_cpu_relax(); \ | |
363 | } while (!(cond)); \ | |
364 | spin_end(); \ | |
365 | } \ | |
366 | } while (0) | |
367 | ||
9f04b9e3 | 368 | #else |
1da177e4 | 369 | #define cpu_relax() barrier() |
9f04b9e3 | 370 | #endif |
1da177e4 | 371 | |
2f25194d AB |
372 | /* Check that a certain kernel stack pointer is valid in task_struct p */ |
373 | int validate_sp(unsigned long sp, struct task_struct *p, | |
374 | unsigned long nbytes); | |
375 | ||
1da177e4 LT |
376 | /* |
377 | * Prefetch macros. | |
378 | */ | |
379 | #define ARCH_HAS_PREFETCH | |
380 | #define ARCH_HAS_PREFETCHW | |
381 | #define ARCH_HAS_SPINLOCK_PREFETCH | |
382 | ||
9f04b9e3 | 383 | static inline void prefetch(const void *x) |
1da177e4 | 384 | { |
9f04b9e3 PM |
385 | if (unlikely(!x)) |
386 | return; | |
387 | ||
388 | __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x)); | |
1da177e4 LT |
389 | } |
390 | ||
9f04b9e3 | 391 | static inline void prefetchw(const void *x) |
1da177e4 | 392 | { |
9f04b9e3 PM |
393 | if (unlikely(!x)) |
394 | return; | |
395 | ||
396 | __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x)); | |
1da177e4 LT |
397 | } |
398 | ||
399 | #define spin_lock_prefetch(x) prefetchw(x) | |
400 | ||
9f04b9e3 | 401 | #define HAVE_ARCH_PICK_MMAP_LAYOUT |
1da177e4 | 402 | |
efbda860 | 403 | #ifdef CONFIG_PPC64 |
2b3f8e87 | 404 | static inline unsigned long get_clean_sp(unsigned long sp, int is_32) |
efbda860 | 405 | { |
efbda860 | 406 | if (is_32) |
2b3f8e87 | 407 | return sp & 0x0ffffffffUL; |
efbda860 JB |
408 | return sp; |
409 | } | |
410 | #else | |
2b3f8e87 | 411 | static inline unsigned long get_clean_sp(unsigned long sp, int is_32) |
efbda860 | 412 | { |
2b3f8e87 | 413 | return sp; |
efbda860 JB |
414 | } |
415 | #endif | |
416 | ||
e8bb3e00 | 417 | extern unsigned long cpuidle_disable; |
771dae81 DD |
418 | enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF}; |
419 | ||
ae3a197e | 420 | extern int powersave_nap; /* set if nap mode can be used in idle loop */ |
2201f994 NP |
421 | extern unsigned long power7_idle_insn(unsigned long type); /* PNV_THREAD_NAP/etc*/ |
422 | extern void power7_idle_type(unsigned long type); | |
423 | extern unsigned long power9_idle_stop(unsigned long psscr_val); | |
3d4fbffd | 424 | extern unsigned long power9_offline_stop(unsigned long psscr_val); |
2201f994 NP |
425 | extern void power9_idle_type(unsigned long stop_psscr_val, |
426 | unsigned long stop_psscr_mask); | |
bcef83a0 | 427 | |
ae3a197e DH |
428 | extern void flush_instruction_cache(void); |
429 | extern void hard_reset_now(void); | |
430 | extern void poweroff_now(void); | |
431 | extern int fix_alignment(struct pt_regs *); | |
432 | extern void cvt_fd(float *from, double *to); | |
433 | extern void cvt_df(double *from, float *to); | |
434 | extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); | |
435 | ||
436 | #ifdef CONFIG_PPC64 | |
437 | /* | |
438 | * We handle most unaligned accesses in hardware. On the other hand | |
439 | * unaligned DMA can be very expensive on some ppc64 IO chips (it does | |
440 | * powers of 2 writes until it reaches sufficient alignment). | |
441 | * | |
442 | * Based on this we disable the IP header alignment in network drivers. | |
443 | */ | |
444 | #define NET_IP_ALIGN 0 | |
445 | #endif | |
446 | ||
1da177e4 | 447 | #endif /* __KERNEL__ */ |
9f04b9e3 PM |
448 | #endif /* __ASSEMBLY__ */ |
449 | #endif /* _ASM_POWERPC_PROCESSOR_H */ |