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powerpc/mm: Fixup tlbie vs mtpidr/mtlpidr ordering issue on POWER9
[linux-2.6-block.git] / arch / powerpc / include / asm / ppc_asm.h
CommitLineData
1da177e4 1/*
1da177e4 2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
1da177e4 3 */
5f7c6907
KG		 4#ifndef _ASM_POWERPC_PPC_ASM_H
5#define _ASM_POWERPC_PPC_ASM_H
6
40ef8cbc 7#include <linux/stringify.h>
3ddfbcf1 8#include <asm/asm-compat.h>
9c75a31c 9#include <asm/processor.h>
16c57b36 10#include <asm/ppc-opcode.h>
cf9efce0 11#include <asm/firmware.h>
2c86cd18 12#include <asm/feature-fixups.h>
40ef8cbc 13
e3f2c6c3 14#ifdef __ASSEMBLY__
3ddfbcf1
DG		 15
16#define SZL (BITS_PER_LONG/8)
1da177e4 17
c6622f63
PM		 18/*
19 * Stuff for accurate CPU time accounting.
20 * These macros handle transitions between user and system state
21 * in exception entry and exit and accumulate time to the
22 * user_time and system_time fields in the paca.
23 */
24
abf917cd 25#ifndef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
c223c903
CL		 26#define ACCOUNT_CPU_USER_ENTRY(ptr, ra, rb)
27#define ACCOUNT_CPU_USER_EXIT(ptr, ra, rb)
cf9efce0 28#define ACCOUNT_STOLEN_TIME
c6622f63 29#else
c223c903 30#define ACCOUNT_CPU_USER_ENTRY(ptr, ra, rb) \
cf9efce0 31 MFTB(ra); /* get timebase */ \
c223c903
CL		 32 PPC_LL rb, ACCOUNT_STARTTIME_USER(ptr); \
33 PPC_STL ra, ACCOUNT_STARTTIME(ptr); \
c6622f63 34 subf rb,rb,ra; /* subtract start value */ \
c223c903 35 PPC_LL ra, ACCOUNT_USER_TIME(ptr); \
c6622f63 36 add ra,ra,rb; /* add on to user time */ \
c223c903 37 PPC_STL ra, ACCOUNT_USER_TIME(ptr); \
c6622f63 38
c223c903 39#define ACCOUNT_CPU_USER_EXIT(ptr, ra, rb) \
cf9efce0 40 MFTB(ra); /* get timebase */ \
c223c903
CL		 41 PPC_LL rb, ACCOUNT_STARTTIME(ptr); \
42 PPC_STL ra, ACCOUNT_STARTTIME_USER(ptr); \
c6622f63 43 subf rb,rb,ra; /* subtract start value */ \
c223c903 44 PPC_LL ra, ACCOUNT_SYSTEM_TIME(ptr); \
cf9efce0 45 add ra,ra,rb; /* add on to system time */ \
c223c903 46 PPC_STL ra, ACCOUNT_SYSTEM_TIME(ptr)
cf9efce0
PM		 47
48#ifdef CONFIG_PPC_SPLPAR
49#define ACCOUNT_STOLEN_TIME \
50BEGIN_FW_FTR_SECTION; \
51 beq 33f; \
52 /* from user - see if there are any DTL entries to process */ \
53 ld r10,PACALPPACAPTR(r13); /* get ptr to VPA */ \
54 ld r11,PACA_DTL_RIDX(r13); /* get log read index */ \
7ffcf8ec
AB		 55 addi r10,r10,LPPACA_DTLIDX; \
56 LDX_BE r10,0,r10; /* get log write index */ \
cf9efce0
PM		 57 cmpd cr1,r11,r10; \
58 beq+ cr1,33f; \
b1576fec 59 bl accumulate_stolen_time; \
990118c8
BH		 60 ld r12,_MSR(r1); \
61 andi. r10,r12,MSR_PR; /* Restore cr0 (coming from user) */ \
cf9efce0
PM		 6233: \
63END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
64
65#else /* CONFIG_PPC_SPLPAR */
66#define ACCOUNT_STOLEN_TIME
67
68#endif /* CONFIG_PPC_SPLPAR */
69
abf917cd 70#endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
c6622f63 71
1da177e4
LT		 72/*
73 * Macros for storing registers into and loading registers from
74 * exception frames.
75 */
5f7c6907
KG		 76#ifdef __powerpc64__
77#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
78#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
79#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
80#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
81#else
1da177e4 82#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
5f7c6907 83#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
a1f3ae3f
CL		 84#define SAVE_NVGPRS(base) stmw 13, GPR0+4*13(base)
85#define REST_NVGPRS(base) lmw 13, GPR0+4*13(base)
5f7c6907
KG		 86#endif
87
1da177e4
LT		 88#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
89#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
90#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
91#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
1da177e4
LT		 92#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
93#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
94#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
95#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
96
de79f7b9 97#define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base)
1da177e4
LT		 98#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
99#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
100#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
101#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
102#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
de79f7b9 103#define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base)
1da177e4
LT		 104#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
105#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
106#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
107#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
108#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
109
de79f7b9 110#define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b
5f7c6907
KG		 111#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
112#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
113#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
114#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
115#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
de79f7b9 116#define REST_VR(n,b,base) li b,16*(n); lvx n,base,b
5f7c6907
KG		 117#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
118#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
119#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
120#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
121#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
1da177e4 122
926f160f
AB		 123#ifdef __BIG_ENDIAN__
124#define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base)
125#define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base)
126#else
127#define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \
128 STXVD2X(n,b,base); \
129 XXSWAPD(n,n)
130
131#define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \
132 XXSWAPD(n,n)
133#endif
72ffff5b 134/* Save the lower 32 VSRs in the thread VSR region */
3ad26e5c 135#define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b)
72ffff5b
MN		 136#define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
137#define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
138#define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
139#define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
140#define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
3ad26e5c 141#define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b)
72ffff5b
MN		 142#define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base)
143#define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
144#define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
145#define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
146#define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
72ffff5b 147
c51584d5
SW		 148/*
149 * b = base register for addressing, o = base offset from register of 1st EVR
150 * n = first EVR, s = scratch
151 */
152#define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b)
153#define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o)
154#define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o)
155#define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o)
156#define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o)
157#define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o)
158#define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n
159#define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o)
160#define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o)
161#define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o)
162#define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o)
163#define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o)
5f7c6907 164
8c71632f
ME		 165/* Macros to adjust thread priority for hardware multithreading */
166#define HMT_VERY_LOW or 31,31,31 # very low priority
167#define HMT_LOW or 1,1,1
168#define HMT_MEDIUM_LOW or 6,6,6 # medium low priority
169#define HMT_MEDIUM or 2,2,2
170#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
171#define HMT_HIGH or 3,3,3
50fb8ebe 172#define HMT_EXTRA_HIGH or 7,7,7 # power7 only
5f7c6907 173
d72be892
MN		 174#ifdef CONFIG_PPC64
175#define ULONG_SIZE 8
176#else
177#define ULONG_SIZE 4
178#endif
0b7673c3
MN		 179#define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE))
180#define VCPU_GPR(n) __VCPU_GPR(__REG_##n)
d72be892 181
88ced031 182#ifdef __KERNEL__
40ef8cbc
PM		 183#ifdef CONFIG_PPC64
184
44ce6a5e 185#define STACKFRAMESIZE 256
0b7673c3
MN		 186#define __STK_REG(i) (112 + ((i)-14)*8)
187#define STK_REG(i) __STK_REG(__REG_##i)
44ce6a5e 188
f55d9665 189#ifdef PPC64_ELF_ABI_v2
6403105b 190#define STK_GOT 24
b37c10d1
AB		 191#define __STK_PARAM(i) (32 + ((i)-3)*8)
192#else
6403105b 193#define STK_GOT 40
0b7673c3 194#define __STK_PARAM(i) (48 + ((i)-3)*8)
b37c10d1 195#endif
0b7673c3 196#define STK_PARAM(i) __STK_PARAM(__REG_##i)
44ce6a5e 197
f55d9665 198#ifdef PPC64_ELF_ABI_v2
7167af7c
AB		 199
200#define _GLOBAL(name) \
7167af7c
AB		 201 .align 2 ; \
202 .type name,@function; \
203 .globl name; \
204name:
205
169c7cee 206#define _GLOBAL_TOC(name) \
169c7cee
AB		 207 .align 2 ; \
208 .type name,@function; \
209 .globl name; \
210name: \
2110: addis r2,r12,(.TOC.-0b)@ha; \
212 addi r2,r2,(.TOC.-0b)@l; \
213 .localentry name,.-name
214
7167af7c
AB		 215#define DOTSYM(a) a
216
217#else
218
40ef8cbc
PM		 219#define XGLUE(a,b) a##b
220#define GLUE(a,b) XGLUE(a,b)
221
222#define _GLOBAL(name) \
40ef8cbc
PM		 223 .align 2 ; \
224 .globl name; \
225 .globl GLUE(.,name); \
bea2dccc 226 .pushsection ".opd","aw"; \
40ef8cbc
PM		 227name: \
228 .quad GLUE(.,name); \
229 .quad .TOC.@tocbase; \
230 .quad 0; \
bea2dccc 231 .popsection; \
40ef8cbc
PM		 232 .type GLUE(.,name),@function; \
233GLUE(.,name):
234
169c7cee
AB		 235#define _GLOBAL_TOC(name) _GLOBAL(name)
236
c1fb0194
AB		 237#define DOTSYM(a) GLUE(.,a)
238
7167af7c
AB		 239#endif
240
40ef8cbc
PM		 241#else /* 32-bit */
242
748a7683
KG		 243#define _ENTRY(n) \
244 .globl n; \
245n:
246
40ef8cbc 247#define _GLOBAL(n) \
40ef8cbc
PM		 248 .stabs __stringify(n:F-1),N_FUN,0,0,n;\
249 .globl n; \
250n:
251
9715a2e8
AG		 252#define _GLOBAL_TOC(name) _GLOBAL(name)
253
40ef8cbc
PM		 254#endif
255
6f698df1
NP		 256/*
257 * __kprobes (the C annotation) puts the symbol into the .kprobes.text
258 * section, which gets emitted at the end of regular text.
259 *
260 * _ASM_NOKPROBE_SYMBOL and NOKPROBE_SYMBOL just adds the symbol to
261 * a blacklist. The former is for core kprobe functions/data, the
262 * latter is for those that incdentially must be excluded from probing
263 * and allows them to be linked at more optimal location within text.
264 */
c0a51491 265#ifdef CONFIG_KPROBES
6f698df1
NP		 266#define _ASM_NOKPROBE_SYMBOL(entry) \
267 .pushsection "_kprobe_blacklist","aw"; \
268 PPC_LONG (entry) ; \
269 .popsection
c0a51491
NP		 270#else
271#define _ASM_NOKPROBE_SYMBOL(entry)
272#endif
6f698df1 273
151f2511
AB		 274#define FUNC_START(name) _GLOBAL(name)
275#define FUNC_END(name)
276
5f7c6907 277/*
e58c3495
DG		 278 * LOAD_REG_IMMEDIATE(rn, expr)
279 * Loads the value of the constant expression 'expr' into register 'rn'
280 * using immediate instructions only. Use this when it's important not
281 * to reference other data (i.e. on ppc64 when the TOC pointer is not
e31aa453 282 * valid) and when 'expr' is a constant or absolute address.
5f7c6907 283 *
e58c3495
DG		 284 * LOAD_REG_ADDR(rn, name)
285 * Loads the address of label 'name' into register 'rn'. Use this when
286 * you don't particularly need immediate instructions only, but you need
287 * the whole address in one register (e.g. it's a structure address and
288 * you want to access various offsets within it). On ppc32 this is
289 * identical to LOAD_REG_IMMEDIATE.
290 *
1c49abec
KH		 291 * LOAD_REG_ADDR_PIC(rn, name)
292 * Loads the address of label 'name' into register 'run'. Use this when
293 * the kernel doesn't run at the linked or relocated address. Please
294 * note that this macro will clobber the lr register.
295 *
e58c3495
DG		 296 * LOAD_REG_ADDRBASE(rn, name)
297 * ADDROFF(name)
298 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into
299 * register 'rn'. ADDROFF(name) returns the remainder of the address as
300 * a constant expression. ADDROFF(name) is a signed expression < 16 bits
301 * in size, so is suitable for use directly as an offset in load and store
302 * instructions. Use this when loading/storing a single word or less as:
303 * LOAD_REG_ADDRBASE(rX, name)
304 * ld rY,ADDROFF(name)(rX)
5f7c6907 305 */
1c49abec
KH		 306
307/* Be careful, this will clobber the lr register. */
308#define LOAD_REG_ADDR_PIC(reg, name) \
309 bl 0f; \
3100: mflr reg; \
311 addis reg,reg,(name - 0b)@ha; \
312 addi reg,reg,(name - 0b)@l;
313
c691b4b8 314#if defined(__powerpc64__) && defined(HAVE_AS_ATHIGH)
7998eb3d
GR		 315#define __AS_ATHIGH high
316#else
317#define __AS_ATHIGH h
318#endif
c691b4b8
CL		 319
320.macro __LOAD_REG_IMMEDIATE_32 r, x
321 .if (\x) >= 0x8000 || (\x) < -0x8000
322 lis \r, (\x)@__AS_ATHIGH
323 .if (\x) & 0xffff != 0
324 ori \r, \r, (\x)@l
325 .endif
326 .else
327 li \r, (\x)@l
328 .endif
329.endm
330
331.macro __LOAD_REG_IMMEDIATE r, x
332 .if (\x) >= 0x80000000 || (\x) < -0x80000000
333 __LOAD_REG_IMMEDIATE_32 \r, (\x) >> 32
334 sldi \r, \r, 32
335 .if (\x) & 0xffff0000 != 0
336 oris \r, \r, (\x)@__AS_ATHIGH
337 .endif
338 .if (\x) & 0xffff != 0
339 ori \r, \r, (\x)@l
340 .endif
341 .else
342 __LOAD_REG_IMMEDIATE_32 \r, \x
343 .endif
344.endm
345
346#ifdef __powerpc64__
347
348#define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE reg, expr
349
d7fb5b18
CL		 350#define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr) \
351 lis tmp, (expr)@highest; \
352 lis reg, (expr)@__AS_ATHIGH; \
353 ori tmp, tmp, (expr)@higher; \
354 ori reg, reg, (expr)@l; \
355 rldimi reg, tmp, 32, 0
e58c3495
DG		 356
357#define LOAD_REG_ADDR(reg,name) \
564aa5cf 358 ld reg,name@got(r2)
e58c3495
DG		 359
360#define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name)
361#define ADDROFF(name) 0
b85a046a 362
f78541dc
PM		 363/* offsets for stack frame layout */
364#define LRSAVE 16
b85a046a
PM		 365
366#else /* 32-bit */
70620186 367
c691b4b8
CL		 368#define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE_32 reg, expr
369
370#define LOAD_REG_IMMEDIATE_SYM(reg,expr) \
564aa5cf
MN		 371 lis reg,(expr)@ha; \
372 addi reg,reg,(expr)@l;
e58c3495 373
c691b4b8 374#define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE_SYM(reg, name)
b85a046a 375
564aa5cf 376#define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha
e58c3495 377#define ADDROFF(name) name@l
b85a046a 378
f78541dc
PM		 379/* offsets for stack frame layout */
380#define LRSAVE 4
b85a046a 381
5f7c6907 382#endif
1da177e4 383
5f7c6907 384/* various errata or part fixups */
1da177e4 385#ifdef CONFIG_PPC601_SYNC_FIX
12c3f1fd
CL		 386#define SYNC sync; isync
387#define SYNC_601 sync
388#define ISYNC_601 isync
1da177e4
LT		 389#else
390#define SYNC
391#define SYNC_601
392#define ISYNC_601
393#endif
394
d52459ca 395#if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
859deea9 396#define MFTB(dest) \
beb2dc0a 39790: mfspr dest, SPRN_TBRL; \
859deea9
BH		 398BEGIN_FTR_SECTION_NESTED(96); \
399 cmpwi dest,0; \
400 beq- 90b; \
401END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
402#else
72e4b2cd
CL		 403#define MFTB(dest) MFTBL(dest)
404#endif
405
406#ifdef CONFIG_PPC_8xx
407#define MFTBL(dest) mftb dest
408#define MFTBU(dest) mftbu dest
409#else
410#define MFTBL(dest) mfspr dest, SPRN_TBRL
411#define MFTBU(dest) mfspr dest, SPRN_TBRU
859deea9 412#endif
5f7c6907 413
1da177e4 414/* tlbsync is not implemented on 601 */
12c3f1fd
CL		 415#if !defined(CONFIG_SMP) || defined(CONFIG_PPC_BOOK3S_601)
416#define TLBSYNC
417#else
418#define TLBSYNC tlbsync; sync
1da177e4
LT		 419#endif
420
694caf02
AB		 421#ifdef CONFIG_PPC64
422#define MTOCRF(FXM, RS) \
423 BEGIN_FTR_SECTION_NESTED(848); \
86e32fdc 424 mtcrf (FXM), RS; \
694caf02 425 FTR_SECTION_ELSE_NESTED(848); \
86e32fdc 426 mtocrf (FXM), RS; \
694caf02
AB		 427 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848)
428#endif
429
1da177e4
LT		 430/*
431 * This instruction is not implemented on the PPC 603 or 601; however, on
432 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
433 * All of these instructions exist in the 8xx, they have magical powers,
434 * and they must be used.
435 */
436
968159c0 437#if !defined(CONFIG_4xx) && !defined(CONFIG_PPC_8xx)
1da177e4
LT		 438#define tlbia \
439 li r4,1024; \
440 mtctr r4; \
441 lis r4,KERNELBASE@h; \
e3824e42
RC		 442 .machine push; \
443 .machine "power4"; \
1da177e4 4440: tlbie r4; \
e3824e42 445 .machine pop; \
1da177e4
LT		 446 addi r4,r4,0x1000; \
447 bdnz 0b
448#endif
449
5f7c6907 450
5f7c6907
KG		 451#ifdef CONFIG_IBM440EP_ERR42
452#define PPC440EP_ERR42 isync
453#else
454#define PPC440EP_ERR42
455#endif
456
a515348f
MN		 457/* The following stops all load and store data streams associated with stream
458 * ID (ie. streams created explicitly). The embedded and server mnemonics for
15a3204d 459 * dcbt are different so this must only be used for server.
a515348f 460 */
15a3204d
NP		 461#define DCBT_BOOK3S_STOP_ALL_STREAM_IDS(scratch) \
462 lis scratch,0x60000000@h; \
463 dcbt 0,scratch,0b01010
a515348f 464
44c58ccc
BH		 465/*
466 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them
467 * keep the address intact to be compatible with code shared with
468 * 32-bit classic.
469 *
470 * On the other hand, I find it useful to have them behave as expected
471 * by their name (ie always do the addition) on 64-bit BookE
472 */
473#if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64)
6316222e
PM		 474#define toreal(rd)
475#define fromreal(rd)
476
2ca7633d
RM		 477/*
478 * We use addis to ensure compatibility with the "classic" ppc versions of
479 * these macros, which use rs = 0 to get the tophys offset in rd, rather than
480 * converting the address in r0, and so this version has to do that too
481 * (i.e. set register rd to 0 when rs == 0).
482 */
1da177e4
LT		 483#define tophys(rd,rs) \
484 addis rd,rs,0
485
486#define tovirt(rd,rs) \
487 addis rd,rs,0
488
5f7c6907 489#elif defined(CONFIG_PPC64)
6316222e
PM		 490#define toreal(rd) /* we can access c000... in real mode */
491#define fromreal(rd)
492
5f7c6907 493#define tophys(rd,rs) \
6316222e 494 clrldi rd,rs,2
5f7c6907
KG		 495
496#define tovirt(rd,rs) \
6316222e
PM		 497 rotldi rd,rs,16; \
498 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\
499 rotldi rd,rd,48
5f7c6907 500#else
6316222e
PM		 501#define toreal(rd) tophys(rd,rd)
502#define fromreal(rd) tovirt(rd,rd)
503
c62ce9ef
CL		 504#define tophys(rd, rs) addis rd, rs, -PAGE_OFFSET@h
505#define tovirt(rd, rs) addis rd, rs, PAGE_OFFSET@h
5f7c6907 506#endif
1da177e4 507
44c58ccc 508#ifdef CONFIG_PPC_BOOK3S_64
40ef8cbc
PM		 509#define RFI rfid
510#define MTMSRD(r) mtmsrd r
b38c77d8 511#define MTMSR_EERI(reg) mtmsrd reg,1
1da177e4 512#else
1da177e4
LT		 513#ifndef CONFIG_40x
514#define RFI rfi
515#else
516#define RFI rfi; b . /* Prevent prefetch past rfi */
517#endif
518#define MTMSRD(r) mtmsr r
b38c77d8 519#define MTMSR_EERI(reg) mtmsr reg
c9cf73ae
MP		 520#endif
521
88ced031
AB		 522#endif /* __KERNEL__ */
523
1da177e4
LT		 524/* The boring bits... */
525
526/* Condition Register Bit Fields */
527
528#define cr0 0
529#define cr1 1
530#define cr2 2
531#define cr3 3
532#define cr4 4
533#define cr5 5
534#define cr6 6
535#define cr7 7
536
537
9a13a524
MN		 538/*
539 * General Purpose Registers (GPRs)
540 *
541 * The lower case r0-r31 should be used in preference to the upper
542 * case R0-R31 as they provide more error checking in the assembler.
543 * Use R0-31 only when really nessesary.
544 */
545
546#define r0 %r0
547#define r1 %r1
548#define r2 %r2
549#define r3 %r3
550#define r4 %r4
551#define r5 %r5
552#define r6 %r6
553#define r7 %r7
554#define r8 %r8
555#define r9 %r9
556#define r10 %r10
557#define r11 %r11
558#define r12 %r12
559#define r13 %r13
560#define r14 %r14
561#define r15 %r15
562#define r16 %r16
563#define r17 %r17
564#define r18 %r18
565#define r19 %r19
566#define r20 %r20
567#define r21 %r21
568#define r22 %r22
569#define r23 %r23
570#define r24 %r24
571#define r25 %r25
572#define r26 %r26
573#define r27 %r27
574#define r28 %r28
575#define r29 %r29
576#define r30 %r30
577#define r31 %r31
1da177e4
LT		 578
579
580/* Floating Point Registers (FPRs) */
581
582#define fr0 0
583#define fr1 1
584#define fr2 2
585#define fr3 3
586#define fr4 4
587#define fr5 5
588#define fr6 6
589#define fr7 7
590#define fr8 8
591#define fr9 9
592#define fr10 10
593#define fr11 11
594#define fr12 12
595#define fr13 13
596#define fr14 14
597#define fr15 15
598#define fr16 16
599#define fr17 17
600#define fr18 18
601#define fr19 19
602#define fr20 20
603#define fr21 21
604#define fr22 22
605#define fr23 23
606#define fr24 24
607#define fr25 25
608#define fr26 26
609#define fr27 27
610#define fr28 28
611#define fr29 29
612#define fr30 30
613#define fr31 31
614
5f7c6907
KG		 615/* AltiVec Registers (VPRs) */
616
c2ce6f9f
AB		 617#define v0 0
618#define v1 1
619#define v2 2
620#define v3 3
621#define v4 4
622#define v5 5
623#define v6 6
624#define v7 7
625#define v8 8
626#define v9 9
627#define v10 10
628#define v11 11
629#define v12 12
630#define v13 13
631#define v14 14
632#define v15 15
633#define v16 16
634#define v17 17
635#define v18 18
636#define v19 19
637#define v20 20
638#define v21 21
639#define v22 22
640#define v23 23
641#define v24 24
642#define v25 25
643#define v26 26
644#define v27 27
645#define v28 28
646#define v29 29
647#define v30 30
648#define v31 31
1da177e4 649
72ffff5b
MN		 650/* VSX Registers (VSRs) */
651
df99e6eb
AB		 652#define vs0 0
653#define vs1 1
654#define vs2 2
655#define vs3 3
656#define vs4 4
657#define vs5 5
658#define vs6 6
659#define vs7 7
660#define vs8 8
661#define vs9 9
662#define vs10 10
663#define vs11 11
664#define vs12 12
665#define vs13 13
666#define vs14 14
667#define vs15 15
668#define vs16 16
669#define vs17 17
670#define vs18 18
671#define vs19 19
672#define vs20 20
673#define vs21 21
674#define vs22 22
675#define vs23 23
676#define vs24 24
677#define vs25 25
678#define vs26 26
679#define vs27 27
680#define vs28 28
681#define vs29 29
682#define vs30 30
683#define vs31 31
684#define vs32 32
685#define vs33 33
686#define vs34 34
687#define vs35 35
688#define vs36 36
689#define vs37 37
690#define vs38 38
691#define vs39 39
692#define vs40 40
693#define vs41 41
694#define vs42 42
695#define vs43 43
696#define vs44 44
697#define vs45 45
698#define vs46 46
699#define vs47 47
700#define vs48 48
701#define vs49 49
702#define vs50 50
703#define vs51 51
704#define vs52 52
705#define vs53 53
706#define vs54 54
707#define vs55 55
708#define vs56 56
709#define vs57 57
710#define vs58 58
711#define vs59 59
712#define vs60 60
713#define vs61 61
714#define vs62 62
715#define vs63 63
72ffff5b 716
5f7c6907
KG		 717/* SPE Registers (EVPRs) */
718
1da177e4
LT		 719#define evr0 0
720#define evr1 1
721#define evr2 2
722#define evr3 3
723#define evr4 4
724#define evr5 5
725#define evr6 6
726#define evr7 7
727#define evr8 8
728#define evr9 9
729#define evr10 10
730#define evr11 11
731#define evr12 12
732#define evr13 13
733#define evr14 14
734#define evr15 15
735#define evr16 16
736#define evr17 17
737#define evr18 18
738#define evr19 19
739#define evr20 20
740#define evr21 21
741#define evr22 22
742#define evr23 23
743#define evr24 24
744#define evr25 25
745#define evr26 26
746#define evr27 27
747#define evr28 28
748#define evr29 29
749#define evr30 30
750#define evr31 31
751
752/* some stab codes */
753#define N_FUN 36
754#define N_RSYM 64
755#define N_SLINE 68
756#define N_SO 100
5f7c6907 757
5c0484e2
BH		 758/*
759 * Create an endian fixup trampoline
760 *
761 * This starts with a "tdi 0,0,0x48" instruction which is
762 * essentially a "trap never", and thus akin to a nop.
763 *
764 * The opcode for this instruction read with the wrong endian
765 * however results in a b . + 8
766 *
767 * So essentially we use that trick to execute the following
768 * trampoline in "reverse endian" if we are running with the
769 * MSR_LE bit set the "wrong" way for whatever endianness the
770 * kernel is built for.
771 */
5f7c6907 772
5c0484e2
BH		 773#ifdef CONFIG_PPC_BOOK3E
774#define FIXUP_ENDIAN
775#else
8ca9c08d
NP		 776/*
777 * This version may be used in in HV or non-HV context.
778 * MSR[EE] must be disabled.
779 */
5c0484e2
BH		 780#define FIXUP_ENDIAN \
781 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
f848ea7f 782 b 191f; /* Skip trampoline if endian is good */ \
5c0484e2
BH		 783 .long 0xa600607d; /* mfmsr r11 */ \
784 .long 0x01006b69; /* xori r11,r11,1 */ \
f1fe5252
NP		 785 .long 0x00004039; /* li r10,0 */ \
786 .long 0x6401417d; /* mtmsrd r10,1 */ \
787 .long 0x05009f42; /* bcl 20,31,$+4 */ \
788 .long 0xa602487d; /* mflr r10 */ \
789 .long 0x14004a39; /* addi r10,r10,20 */ \
5c0484e2
BH		 790 .long 0xa6035a7d; /* mtsrr0 r10 */ \
791 .long 0xa6037b7d; /* mtsrr1 r11 */ \
f848ea7f
NP		 792 .long 0x2400004c; /* rfid */ \
793191:
f1fe5252 794
8ca9c08d
NP		 795/*
796 * This version that may only be used with MSR[HV]=1
797 * - Does not clear MSR[RI], so more robust.
798 * - Slightly smaller and faster.
799 */
800#define FIXUP_ENDIAN_HV \
801 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
802 b 191f; /* Skip trampoline if endian is good */ \
803 .long 0xa600607d; /* mfmsr r11 */ \
804 .long 0x01006b69; /* xori r11,r11,1 */ \
805 .long 0x05009f42; /* bcl 20,31,$+4 */ \
806 .long 0xa602487d; /* mflr r10 */ \
807 .long 0x14004a39; /* addi r10,r10,20 */ \
808 .long 0xa64b5a7d; /* mthsrr0 r10 */ \
809 .long 0xa64b7b7d; /* mthsrr1 r11 */ \
810 .long 0x2402004c; /* hrfid */ \
811191:
812
5c0484e2 813#endif /* !CONFIG_PPC_BOOK3E */
e3f2c6c3 814
5c0484e2 815#endif /* __ASSEMBLY__ */
e3f2c6c3 816
24bfa6a9
NP		 817/*
818 * Helper macro for exception table entries
819 */
820#define EX_TABLE(_fault, _target) \
821 stringify_in_c(.section __ex_table,"a";)\
61a92f70
NP		 822 stringify_in_c(.balign 4;) \
823 stringify_in_c(.long (_fault) - . ;) \
824 stringify_in_c(.long (_target) - . ;) \
24bfa6a9
NP		 825 stringify_in_c(.previous)
826
1cbf8990
DC		 827#ifdef CONFIG_PPC_FSL_BOOK3E
828#define BTB_FLUSH(reg) \
829 lis reg,BUCSR_INIT@h; \
830 ori reg,reg,BUCSR_INIT@l; \
831 mtspr SPRN_BUCSR,reg; \
832 isync;
833#else
834#define BTB_FLUSH(reg)
835#endif /* CONFIG_PPC_FSL_BOOK3E */
836
5f7c6907 837#endif /* _ASM_POWERPC_PPC_ASM_H */
Linux 6.x block layer and io_uring tree(s)