[linux-2.6-block.git] / arch / powerpc / include / asm / pgtable-ppc64.h

#ifndef _ASM_POWERPC_PGTABLE_PPC64_H_
#define _ASM_POWERPC_PGTABLE_PPC64_H_
/*
 * This file contains the functions and defines necessary to modify and use
 * the ppc64 hashed page table.
 */

#ifdef CONFIG_PPC_64K_PAGES
#include <asm/pgtable-ppc64-64k.h>
#else
#include <asm/pgtable-ppc64-4k.h>
#endif

#define FIRST_USER_ADDRESS	0

/*
 * Size of EA range mapped by our pagetables.
 */
#define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
                	    PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
#define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE)


/* Some sanity checking */
#if TASK_SIZE_USER64 > PGTABLE_RANGE
#error TASK_SIZE_USER64 exceeds pagetable range
#endif

#ifdef CONFIG_PPC_STD_MMU_64
#if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT))
#error TASK_SIZE_USER64 exceeds user VSID range
#endif
#endif

/*
 * Define the address range of the kernel non-linear virtual area
 */

#ifdef CONFIG_PPC_BOOK3E
#define KERN_VIRT_START ASM_CONST(0x8000000000000000)
#else
#define KERN_VIRT_START ASM_CONST(0xD000000000000000)
#endif
#define KERN_VIRT_SIZE	PGTABLE_RANGE

/*
 * The vmalloc space starts at the beginning of that region, and
 * occupies half of it on hash CPUs and a quarter of it on Book3E
 */
#define VMALLOC_START	KERN_VIRT_START
#ifdef CONFIG_PPC_BOOK3E
#define VMALLOC_SIZE	(KERN_VIRT_SIZE >> 2)
#else
#define VMALLOC_SIZE	(KERN_VIRT_SIZE >> 1)
#endif
#define VMALLOC_END	(VMALLOC_START + VMALLOC_SIZE)

/*
 * The second half of the kernel virtual space is used for IO mappings,
 * it's itself carved into the PIO region (ISA and PHB IO space) and
 * the ioremap space
 *
 *  ISA_IO_BASE = KERN_IO_START, 64K reserved area
 *  PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
 */
#define KERN_IO_START	(KERN_VIRT_START + (KERN_VIRT_SIZE >> 1))
#define FULL_IO_SIZE	0x80000000ul
#define  ISA_IO_BASE	(KERN_IO_START)
#define  ISA_IO_END	(KERN_IO_START + 0x10000ul)
#define  PHB_IO_BASE	(ISA_IO_END)
#define  PHB_IO_END	(KERN_IO_START + FULL_IO_SIZE)
#define IOREMAP_BASE	(PHB_IO_END)
#define IOREMAP_END	(KERN_VIRT_START + KERN_VIRT_SIZE)


/*
 * Region IDs
 */
#define REGION_SHIFT		60UL
#define REGION_MASK		(0xfUL << REGION_SHIFT)
#define REGION_ID(ea)		(((unsigned long)(ea)) >> REGION_SHIFT)

#define VMALLOC_REGION_ID	(REGION_ID(VMALLOC_START))
#define KERNEL_REGION_ID	(REGION_ID(PAGE_OFFSET))
#define VMEMMAP_REGION_ID	(0xfUL)
#define USER_REGION_ID		(0UL)

/*
 * Defines the address of the vmemap area, in its own region on
 * hash table CPUs and after the vmalloc space on Book3E
 */
#ifdef CONFIG_PPC_BOOK3E
#define VMEMMAP_BASE		VMALLOC_END
#define VMEMMAP_END		KERN_IO_START
#else
#define VMEMMAP_BASE		(VMEMMAP_REGION_ID << REGION_SHIFT)
#endif
#define vmemmap			((struct page *)VMEMMAP_BASE)


/*
 * Include the PTE bits definitions
 */
#ifdef CONFIG_PPC_BOOK3S
#include <asm/pte-hash64.h>
#else
#include <asm/pte-book3e.h>
#endif
#include <asm/pte-common.h>

#ifdef CONFIG_PPC_MM_SLICES
#define HAVE_ARCH_UNMAPPED_AREA
#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
#endif /* CONFIG_PPC_MM_SLICES */

#ifndef __ASSEMBLY__

#include <linux/stddef.h>
#include <asm/tlbflush.h>

/*
 * This is the default implementation of various PTE accessors, it's
 * used in all cases except Book3S with 64K pages where we have a
 * concept of sub-pages
 */
#ifndef __real_pte

#ifdef STRICT_MM_TYPECHECKS
#define __real_pte(e,p)		((real_pte_t){(e)})
#define __rpte_to_pte(r)	((r).pte)
#else
#define __real_pte(e,p)		(e)
#define __rpte_to_pte(r)	(__pte(r))
#endif
#define __rpte_to_hidx(r,index)	(pte_val(__rpte_to_pte(r)) >> 12)

#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift)       \
	do {							         \
		index = 0;					         \
		shift = mmu_psize_defs[psize].shift;		         \

#define pte_iterate_hashed_end() } while(0)

#ifdef CONFIG_PPC_HAS_HASH_64K
#define pte_pagesize_index(mm, addr, pte)	get_slice_psize(mm, addr)
#else
#define pte_pagesize_index(mm, addr, pte)	MMU_PAGE_4K
#endif

#endif /* __real_pte */


/* pte_clear moved to later in this file */

#define PMD_BAD_BITS		(PTE_TABLE_SIZE-1)
#define PUD_BAD_BITS		(PMD_TABLE_SIZE-1)

#define pmd_set(pmdp, pmdval) 	(pmd_val(*(pmdp)) = (pmdval))
#define pmd_none(pmd)		(!pmd_val(pmd))
#define	pmd_bad(pmd)		(!is_kernel_addr(pmd_val(pmd)) \
				 || (pmd_val(pmd) & PMD_BAD_BITS))
#define	pmd_present(pmd)	(pmd_val(pmd) != 0)
#define	pmd_clear(pmdp)		(pmd_val(*(pmdp)) = 0)
#define pmd_page_vaddr(pmd)	(pmd_val(pmd) & ~PMD_MASKED_BITS)
#define pmd_page(pmd)		virt_to_page(pmd_page_vaddr(pmd))

#define pud_set(pudp, pudval)	(pud_val(*(pudp)) = (pudval))
#define pud_none(pud)		(!pud_val(pud))
#define	pud_bad(pud)		(!is_kernel_addr(pud_val(pud)) \
				 || (pud_val(pud) & PUD_BAD_BITS))
#define pud_present(pud)	(pud_val(pud) != 0)
#define pud_clear(pudp)		(pud_val(*(pudp)) = 0)
#define pud_page_vaddr(pud)	(pud_val(pud) & ~PUD_MASKED_BITS)
#define pud_page(pud)		virt_to_page(pud_page_vaddr(pud))

#define pgd_set(pgdp, pudp)	({pgd_val(*(pgdp)) = (unsigned long)(pudp);})

/*
 * Find an entry in a page-table-directory.  We combine the address region
 * (the high order N bits) and the pgd portion of the address.
 */
/* to avoid overflow in free_pgtables we don't use PTRS_PER_PGD here */
#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x1ff)

#define pgd_offset(mm, address)	 ((mm)->pgd + pgd_index(address))

#define pmd_offset(pudp,addr) \
  (((pmd_t *) pud_page_vaddr(*(pudp))) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))

#define pte_offset_kernel(dir,addr) \
  (((pte_t *) pmd_page_vaddr(*(dir))) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))

#define pte_offset_map(dir,addr)	pte_offset_kernel((dir), (addr))
#define pte_offset_map_nested(dir,addr)	pte_offset_kernel((dir), (addr))
#define pte_unmap(pte)			do { } while(0)
#define pte_unmap_nested(pte)		do { } while(0)

/* to find an entry in a kernel page-table-directory */
/* This now only contains the vmalloc pages */
#define pgd_offset_k(address) pgd_offset(&init_mm, address)


/* Atomic PTE updates */
static inline unsigned long pte_update(struct mm_struct *mm,
				       unsigned long addr,
				       pte_t *ptep, unsigned long clr,
				       int huge)
{
#ifdef PTE_ATOMIC_UPDATES
	unsigned long old, tmp;

	__asm__ __volatile__(
	"1:	ldarx	%0,0,%3		# pte_update\n\
	andi.	%1,%0,%6\n\
	bne-	1b \n\
	andc	%1,%0,%4 \n\
	stdcx.	%1,0,%3 \n\
	bne-	1b"
	: "=&r" (old), "=&r" (tmp), "=m" (*ptep)
	: "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY)
	: "cc" );
#else
	unsigned long old = pte_val(*ptep);
	*ptep = __pte(old & ~clr);
#endif
	/* huge pages use the old page table lock */
	if (!huge)
		assert_pte_locked(mm, addr);

#ifdef CONFIG_PPC_STD_MMU_64
	if (old & _PAGE_HASHPTE)
		hpte_need_flush(mm, addr, ptep, old, huge);
#endif

	return old;
}

static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
					      unsigned long addr, pte_t *ptep)
{
	unsigned long old;

       	if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
		return 0;
	old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0);
	return (old & _PAGE_ACCESSED) != 0;
}
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
#define ptep_test_and_clear_young(__vma, __addr, __ptep)		   \
({									   \
	int __r;							   \
	__r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
	__r;								   \
})

#define __HAVE_ARCH_PTEP_SET_WRPROTECT
static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
				      pte_t *ptep)
{
	unsigned long old;

       	if ((pte_val(*ptep) & _PAGE_RW) == 0)
       		return;
	old = pte_update(mm, addr, ptep, _PAGE_RW, 0);
}

static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
					   unsigned long addr, pte_t *ptep)
{
	unsigned long old;

	if ((pte_val(*ptep) & _PAGE_RW) == 0)
		return;
	old = pte_update(mm, addr, ptep, _PAGE_RW, 1);
}

/*
 * We currently remove entries from the hashtable regardless of whether
 * the entry was young or dirty. The generic routines only flush if the
 * entry was young or dirty which is not good enough.
 *
 * We should be more intelligent about this but for the moment we override
 * these functions and force a tlb flush unconditionally
 */
#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
#define ptep_clear_flush_young(__vma, __address, __ptep)		\
({									\
	int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \
						  __ptep);		\
	__young;							\
})

#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
				       unsigned long addr, pte_t *ptep)
{
	unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0);
	return __pte(old);
}

static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
			     pte_t * ptep)
{
	pte_update(mm, addr, ptep, ~0UL, 0);
}


/* Set the dirty and/or accessed bits atomically in a linux PTE, this
 * function doesn't need to flush the hash entry
 */
static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
{
	unsigned long bits = pte_val(entry) &
		(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW |
		 _PAGE_EXEC | _PAGE_HWEXEC);

#ifdef PTE_ATOMIC_UPDATES
	unsigned long old, tmp;

	__asm__ __volatile__(
	"1:	ldarx	%0,0,%4\n\
		andi.	%1,%0,%6\n\
		bne-	1b \n\
		or	%0,%3,%0\n\
		stdcx.	%0,0,%4\n\
		bne-	1b"
	:"=&r" (old), "=&r" (tmp), "=m" (*ptep)
	:"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
	:"cc");
#else
	unsigned long old = pte_val(*ptep);
	*ptep = __pte(old | bits);
#endif
}

#define __HAVE_ARCH_PTE_SAME
#define pte_same(A,B)	(((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)

#define pte_ERROR(e) \
	printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
#define pmd_ERROR(e) \
	printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
#define pgd_ERROR(e) \
	printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))

/* Encode and de-code a swap entry */
#define __swp_type(entry)	(((entry).val >> 1) & 0x3f)
#define __swp_offset(entry)	((entry).val >> 8)
#define __swp_entry(type, offset) ((swp_entry_t){((type)<< 1)|((offset)<<8)})
#define __pte_to_swp_entry(pte)	((swp_entry_t){pte_val(pte) >> PTE_RPN_SHIFT})
#define __swp_entry_to_pte(x)	((pte_t) { (x).val << PTE_RPN_SHIFT })
#define pte_to_pgoff(pte)	(pte_val(pte) >> PTE_RPN_SHIFT)
#define pgoff_to_pte(off)	((pte_t) {((off) << PTE_RPN_SHIFT)|_PAGE_FILE})
#define PTE_FILE_MAX_BITS	(BITS_PER_LONG - PTE_RPN_SHIFT)

void pgtable_cache_init(void);

/*
 * find_linux_pte returns the address of a linux pte for a given
 * effective address and directory.  If not found, it returns zero.
 */static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea)
{
	pgd_t *pg;
	pud_t *pu;
	pmd_t *pm;
	pte_t *pt = NULL;

	pg = pgdir + pgd_index(ea);
	if (!pgd_none(*pg)) {
		pu = pud_offset(pg, ea);
		if (!pud_none(*pu)) {
			pm = pmd_offset(pu, ea);
			if (pmd_present(*pm))
				pt = pte_offset_kernel(pm, ea);
		}
	}
	return pt;
}

pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long address);

#endif /* __ASSEMBLY__ */

#endif /* _ASM_POWERPC_PGTABLE_PPC64_H_ */
Commit	Line	Data
f88df14b DG	1	#ifndef _ASM_POWERPC_PGTABLE_PPC64_H_
	2	#define _ASM_POWERPC_PGTABLE_PPC64_H_
	3	/*
	4	* This file contains the functions and defines necessary to modify and use
	5	* the ppc64 hashed page table.
	6	*/
	7
f88df14b	8	#ifdef CONFIG_PPC_64K_PAGES
c605782b	9	#include <asm/pgtable-ppc64-64k.h>
f88df14b	10	#else
c605782b	11	#include <asm/pgtable-ppc64-4k.h>
f88df14b DG	12	#endif
	13
	14	#define FIRST_USER_ADDRESS 0
	15
	16	/*
	17	* Size of EA range mapped by our pagetables.
	18	*/
	19	#define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
	20	PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
3d5134ee	21	#define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE)
f88df14b	22
c605782b BH	23
c605782b BH	24	/* Some sanity checking */
f88df14b DG	25	#if TASK_SIZE_USER64 > PGTABLE_RANGE
	26	#error TASK_SIZE_USER64 exceeds pagetable range
	27	#endif
	28
94491685	29	#ifdef CONFIG_PPC_STD_MMU_64
f88df14b DG	30	#if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT))
	31	#error TASK_SIZE_USER64 exceeds user VSID range
	32	#endif
94491685	33	#endif
f88df14b DG	34
f88df14b DG	35	/*
57e2a99f	36	* Define the address range of the kernel non-linear virtual area
f88df14b	37	*/
57e2a99f BH	38
	39	#ifdef CONFIG_PPC_BOOK3E
	40	#define KERN_VIRT_START ASM_CONST(0x8000000000000000)
	41	#else
	42	#define KERN_VIRT_START ASM_CONST(0xD000000000000000)
	43	#endif
	44	#define KERN_VIRT_SIZE PGTABLE_RANGE
f88df14b DG	45
f88df14b DG	46	/*
57e2a99f BH	47	* The vmalloc space starts at the beginning of that region, and
	48	* occupies half of it on hash CPUs and a quarter of it on Book3E
	49	*/
	50	#define VMALLOC_START KERN_VIRT_START
	51	#ifdef CONFIG_PPC_BOOK3E
	52	#define VMALLOC_SIZE (KERN_VIRT_SIZE >> 2)
	53	#else
	54	#define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1)
	55	#endif
	56	#define VMALLOC_END (VMALLOC_START + VMALLOC_SIZE)
	57
	58	/*
	59	* The second half of the kernel virtual space is used for IO mappings,
	60	* it's itself carved into the PIO region (ISA and PHB IO space) and
	61	* the ioremap space
3d5134ee	62	*
57e2a99f	63	* ISA_IO_BASE = KERN_IO_START, 64K reserved area
3d5134ee BH	64	* PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
3d5134ee BH	65	* IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
f88df14b	66	*/
57e2a99f	67	#define KERN_IO_START (KERN_VIRT_START + (KERN_VIRT_SIZE >> 1))
3d5134ee	68	#define FULL_IO_SIZE 0x80000000ul
57e2a99f BH	69	#define ISA_IO_BASE (KERN_IO_START)
57e2a99f BH	70	#define ISA_IO_END (KERN_IO_START + 0x10000ul)
3d5134ee	71	#define PHB_IO_BASE (ISA_IO_END)
57e2a99f	72	#define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE)
3d5134ee	73	#define IOREMAP_BASE (PHB_IO_END)
57e2a99f BH	74	#define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE)
57e2a99f BH	75
f88df14b DG	76
	77	/*
	78	* Region IDs
	79	*/
	80	#define REGION_SHIFT 60UL
	81	#define REGION_MASK (0xfUL << REGION_SHIFT)
	82	#define REGION_ID(ea) (((unsigned long)(ea)) >> REGION_SHIFT)
	83
	84	#define VMALLOC_REGION_ID (REGION_ID(VMALLOC_START))
	85	#define KERNEL_REGION_ID (REGION_ID(PAGE_OFFSET))
cec08e7a	86	#define VMEMMAP_REGION_ID (0xfUL)
f88df14b DG	87	#define USER_REGION_ID (0UL)
f88df14b DG	88
d29eff7b	89	/*
57e2a99f BH	90	* Defines the address of the vmemap area, in its own region on
57e2a99f BH	91	* hash table CPUs and after the vmalloc space on Book3E
d29eff7b	92	*/
57e2a99f BH	93	#ifdef CONFIG_PPC_BOOK3E
	94	#define VMEMMAP_BASE VMALLOC_END
	95	#define VMEMMAP_END KERN_IO_START
	96	#else
cec08e7a	97	#define VMEMMAP_BASE (VMEMMAP_REGION_ID << REGION_SHIFT)
57e2a99f	98	#endif
cec08e7a BH	99	#define vmemmap ((struct page *)VMEMMAP_BASE)
cec08e7a BH	100
d29eff7b	101
f88df14b	102	/*
c605782b	103	* Include the PTE bits definitions
f88df14b	104	*/
57e2a99f	105	#ifdef CONFIG_PPC_BOOK3S
c605782b	106	#include <asm/pte-hash64.h>
57e2a99f BH	107	#else
	108	#include <asm/pte-book3e.h>
	109	#endif
71087002	110	#include <asm/pte-common.h>
c605782b	111
94ee815c	112	#ifdef CONFIG_PPC_MM_SLICES
f88df14b DG	113	#define HAVE_ARCH_UNMAPPED_AREA
f88df14b DG	114	#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
94ee815c	115	#endif /* CONFIG_PPC_MM_SLICES */
f88df14b DG	116
	117	#ifndef __ASSEMBLY__
	118
57e2a99f BH	119	#include <linux/stddef.h>
	120	#include <asm/tlbflush.h>
	121
c605782b BH	122	/*
	123	* This is the default implementation of various PTE accessors, it's
	124	* used in all cases except Book3S with 64K pages where we have a
	125	* concept of sub-pages
	126	*/
	127	#ifndef __real_pte
	128
	129	#ifdef STRICT_MM_TYPECHECKS
	130	#define __real_pte(e,p) ((real_pte_t){(e)})
	131	#define __rpte_to_pte(r) ((r).pte)
	132	#else
	133	#define __real_pte(e,p) (e)
	134	#define __rpte_to_pte(r) (__pte(r))
	135	#endif
	136	#define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> 12)
	137
	138	#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
	139	do { \
	140	index = 0; \
	141	shift = mmu_psize_defs[psize].shift; \
	142
	143	#define pte_iterate_hashed_end() } while(0)
	144
	145	#ifdef CONFIG_PPC_HAS_HASH_64K
	146	#define pte_pagesize_index(mm, addr, pte) get_slice_psize(mm, addr)
	147	#else
	148	#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
	149	#endif
	150
	151	#endif /* __real_pte */
	152
	153
f88df14b DG	154	/* pte_clear moved to later in this file */
f88df14b DG	155
f88df14b DG	156	#define PMD_BAD_BITS (PTE_TABLE_SIZE-1)
	157	#define PUD_BAD_BITS (PMD_TABLE_SIZE-1)
	158
	159	#define pmd_set(pmdp, pmdval) (pmd_val(*(pmdp)) = (pmdval))
	160	#define pmd_none(pmd) (!pmd_val(pmd))
	161	#define pmd_bad(pmd) (!is_kernel_addr(pmd_val(pmd)) \
	162	\|\| (pmd_val(pmd) & PMD_BAD_BITS))
	163	#define pmd_present(pmd) (pmd_val(pmd) != 0)
	164	#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0)
	165	#define pmd_page_vaddr(pmd) (pmd_val(pmd) & ~PMD_MASKED_BITS)
	166	#define pmd_page(pmd) virt_to_page(pmd_page_vaddr(pmd))
	167
	168	#define pud_set(pudp, pudval) (pud_val(*(pudp)) = (pudval))
	169	#define pud_none(pud) (!pud_val(pud))
	170	#define pud_bad(pud) (!is_kernel_addr(pud_val(pud)) \
	171	\|\| (pud_val(pud) & PUD_BAD_BITS))
	172	#define pud_present(pud) (pud_val(pud) != 0)
	173	#define pud_clear(pudp) (pud_val(*(pudp)) = 0)
	174	#define pud_page_vaddr(pud) (pud_val(pud) & ~PUD_MASKED_BITS)
	175	#define pud_page(pud) virt_to_page(pud_page_vaddr(pud))
	176
	177	#define pgd_set(pgdp, pudp) ({pgd_val(*(pgdp)) = (unsigned long)(pudp);})
	178
	179	/*
	180	* Find an entry in a page-table-directory. We combine the address region
	181	* (the high order N bits) and the pgd portion of the address.
	182	*/
	183	/* to avoid overflow in free_pgtables we don't use PTRS_PER_PGD here */
	184	#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x1ff)
	185
	186	#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
	187
	188	#define pmd_offset(pudp,addr) \
	189	(((pmd_t ) pud_page_vaddr((pudp))) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
	190
	191	#define pte_offset_kernel(dir,addr) \
	192	(((pte_t ) pmd_page_vaddr((dir))) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
	193
	194	#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
	195	#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
	196	#define pte_unmap(pte) do { } while(0)
	197	#define pte_unmap_nested(pte) do { } while(0)
	198
	199	/* to find an entry in a kernel page-table-directory */
	200	/* This now only contains the vmalloc pages */
	201	#define pgd_offset_k(address) pgd_offset(&init_mm, address)
	202
f88df14b DG	203
	204	/* Atomic PTE updates */
	205	static inline unsigned long pte_update(struct mm_struct *mm,
	206	unsigned long addr,
	207	pte_t *ptep, unsigned long clr,
	208	int huge)
	209	{
a033a487	210	#ifdef PTE_ATOMIC_UPDATES
f88df14b DG	211	unsigned long old, tmp;
	212
	213	__asm__ __volatile__(
	214	"1: ldarx %0,0,%3 # pte_update\n\
	215	andi. %1,%0,%6\n\
	216	bne- 1b \n\
	217	andc %1,%0,%4 \n\
	218	stdcx. %1,0,%3 \n\
	219	bne- 1b"
	220	: "=&r" (old), "=&r" (tmp), "=m" (*ptep)
	221	: "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY)
	222	: "cc" );
a033a487 BH	223	#else
	224	unsigned long old = pte_val(*ptep);
	225	*ptep = __pte(old & ~clr);
	226	#endif
8d30c14c BH	227	/* huge pages use the old page table lock */
	228	if (!huge)
	229	assert_pte_locked(mm, addr);
	230
94491685	231	#ifdef CONFIG_PPC_STD_MMU_64
f88df14b DG	232	if (old & _PAGE_HASHPTE)
f88df14b DG	233	hpte_need_flush(mm, addr, ptep, old, huge);
94491685 BH	234	#endif
94491685 BH	235
f88df14b DG	236	return old;
	237	}
	238
	239	static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
	240	unsigned long addr, pte_t *ptep)
	241	{
	242	unsigned long old;
	243
	244	if ((pte_val(*ptep) & (_PAGE_ACCESSED \| _PAGE_HASHPTE)) == 0)
	245	return 0;
	246	old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0);
	247	return (old & _PAGE_ACCESSED) != 0;
	248	}
	249	#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
	250	#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
	251	({ \
	252	int __r; \
	253	__r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
	254	__r; \
	255	})
	256
f88df14b DG	257	#define __HAVE_ARCH_PTEP_SET_WRPROTECT
	258	static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
	259	pte_t *ptep)
	260	{
	261	unsigned long old;
	262
	263	if ((pte_val(*ptep) & _PAGE_RW) == 0)
	264	return;
	265	old = pte_update(mm, addr, ptep, _PAGE_RW, 0);
	266	}
	267
016b33c4 AW	268	static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
	269	unsigned long addr, pte_t *ptep)
	270	{
	271	unsigned long old;
	272
86df8642 DG	273	if ((pte_val(*ptep) & _PAGE_RW) == 0)
86df8642 DG	274	return;
016b33c4 AW	275	old = pte_update(mm, addr, ptep, _PAGE_RW, 1);
016b33c4 AW	276	}
f88df14b DG	277
	278	/*
	279	* We currently remove entries from the hashtable regardless of whether
	280	* the entry was young or dirty. The generic routines only flush if the
	281	* entry was young or dirty which is not good enough.
	282	*
	283	* We should be more intelligent about this but for the moment we override
	284	* these functions and force a tlb flush unconditionally
	285	*/
	286	#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
	287	#define ptep_clear_flush_young(__vma, __address, __ptep) \
	288	({ \
	289	int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \
	290	__ptep); \
	291	__young; \
	292	})
	293
f88df14b DG	294	#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
	295	static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
	296	unsigned long addr, pte_t *ptep)
	297	{
	298	unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0);
	299	return __pte(old);
	300	}
	301
	302	static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
	303	pte_t * ptep)
	304	{
	305	pte_update(mm, addr, ptep, ~0UL, 0);
	306	}
	307
f88df14b DG	308
	309	/* Set the dirty and/or accessed bits atomically in a linux PTE, this
	310	* function doesn't need to flush the hash entry
	311	*/
8d30c14c	312	static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
f88df14b DG	313	{
f88df14b DG	314	unsigned long bits = pte_val(entry) &
8d1cf34e BH	315	(_PAGE_DIRTY \| _PAGE_ACCESSED \| _PAGE_RW \|
8d1cf34e BH	316	_PAGE_EXEC \| _PAGE_HWEXEC);
a033a487 BH	317
a033a487 BH	318	#ifdef PTE_ATOMIC_UPDATES
f88df14b DG	319	unsigned long old, tmp;
	320
	321	__asm__ __volatile__(
	322	"1: ldarx %0,0,%4\n\
	323	andi. %1,%0,%6\n\
	324	bne- 1b \n\
	325	or %0,%3,%0\n\
	326	stdcx. %0,0,%4\n\
	327	bne- 1b"
	328	:"=&r" (old), "=&r" (tmp), "=m" (*ptep)
	329	:"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
	330	:"cc");
a033a487 BH	331	#else
	332	unsigned long old = pte_val(*ptep);
	333	*ptep = __pte(old \| bits);
	334	#endif
f88df14b	335	}
f88df14b	336
f88df14b DG	337	#define __HAVE_ARCH_PTE_SAME
	338	#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
	339
	340	#define pte_ERROR(e) \
	341	printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
	342	#define pmd_ERROR(e) \
	343	printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
	344	#define pgd_ERROR(e) \
	345	printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
	346
f88df14b DG	347	/* Encode and de-code a swap entry */
	348	#define __swp_type(entry) (((entry).val >> 1) & 0x3f)
	349	#define __swp_offset(entry) ((entry).val >> 8)
	350	#define __swp_entry(type, offset) ((swp_entry_t){((type)<< 1)\|((offset)<<8)})
	351	#define __pte_to_swp_entry(pte) ((swp_entry_t){pte_val(pte) >> PTE_RPN_SHIFT})
	352	#define __swp_entry_to_pte(x) ((pte_t) { (x).val << PTE_RPN_SHIFT })
	353	#define pte_to_pgoff(pte) (pte_val(pte) >> PTE_RPN_SHIFT)
	354	#define pgoff_to_pte(off) ((pte_t) {((off) << PTE_RPN_SHIFT)\|_PAGE_FILE})
	355	#define PTE_FILE_MAX_BITS (BITS_PER_LONG - PTE_RPN_SHIFT)
	356
f88df14b DG	357	void pgtable_cache_init(void);
	358
	359	/*
	360	* find_linux_pte returns the address of a linux pte for a given
	361	* effective address and directory. If not found, it returns zero.
	362	/static inline pte_t find_linux_pte(pgd_t *pgdir, unsigned long ea)
	363	{
	364	pgd_t *pg;
	365	pud_t *pu;
	366	pmd_t *pm;
	367	pte_t *pt = NULL;
	368
	369	pg = pgdir + pgd_index(ea);
	370	if (!pgd_none(*pg)) {
	371	pu = pud_offset(pg, ea);
	372	if (!pud_none(*pu)) {
	373	pm = pmd_offset(pu, ea);
	374	if (pmd_present(*pm))
	375	pt = pte_offset_kernel(pm, ea);
	376	}
	377	}
	378	return pt;
	379	}
	380
ce0ad7f0 NP	381	pte_t huge_pte_offset(struct mm_struct mm, unsigned long address);
ce0ad7f0 NP	382
f88df14b DG	383	#endif /* __ASSEMBLY__ */
	384
	385	#endif /* _ASM_POWERPC_PGTABLE_PPC64_H_ */