Commit | Line | Data |
---|---|---|
2874c5fd | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
d662ed26 | 2 | /* |
a1110654 | 3 | * Performance event support - hardware-specific disambiguation |
d662ed26 | 4 | * |
a1110654 SW |
5 | * For now this is a compile-time decision, but eventually it should be |
6 | * runtime. This would allow multiplatform perf event support for e300 (fsl | |
7 | * embedded perf counters) plus server/classic, and would accommodate | |
8 | * devices other than the core which provide their own performance counters. | |
9 | * | |
10 | * Copyright 2010 Freescale Semiconductor, Inc. | |
d662ed26 | 11 | */ |
079b3c56 | 12 | |
105988c0 | 13 | #ifdef CONFIG_PPC_PERF_CTRS |
a1110654 | 14 | #include <asm/perf_event_server.h> |
3c9450c0 MS |
15 | #else |
16 | static inline bool is_sier_available(void) { return false; } | |
e79b76e0 | 17 | static inline unsigned long get_pmcs_ext_regs(int idx) { return 0; } |
105988c0 PM |
18 | #endif |
19 | ||
a1110654 SW |
20 | #ifdef CONFIG_FSL_EMB_PERF_EVENT |
21 | #include <asm/perf_event_fsl_emb.h> | |
22 | #endif | |
b0f82b81 FW |
23 | |
24 | #ifdef CONFIG_PERF_EVENTS | |
25 | #include <asm/ptrace.h> | |
26 | #include <asm/reg.h> | |
27 | ||
a6460b03 SD |
28 | #define perf_arch_bpf_user_pt_regs(regs) ®s->user_regs |
29 | ||
75382aa7 AB |
30 | /* |
31 | * Overload regs->result to specify whether we should use the MSR (result | |
32 | * is zero) or the SIAR (result is non zero). | |
33 | */ | |
b0f82b81 FW |
34 | #define perf_arch_fetch_caller_regs(regs, __ip) \ |
35 | do { \ | |
75382aa7 | 36 | (regs)->result = 0; \ |
b0f82b81 | 37 | (regs)->nip = __ip; \ |
3d13e839 | 38 | (regs)->gpr[1] = current_stack_frame(); \ |
b0f82b81 FW |
39 | asm volatile("mfmsr %0" : "=r" ((regs)->msr)); \ |
40 | } while (0) | |
333804dc MS |
41 | |
42 | /* To support perf_regs sier update */ | |
43 | extern bool is_sier_available(void); | |
e79b76e0 | 44 | extern unsigned long get_pmcs_ext_regs(int idx); |
781fa481 AS |
45 | /* To define perf extended regs mask value */ |
46 | extern u64 PERF_REG_EXTENDED_MASK; | |
47 | #define PERF_REG_EXTENDED_MASK PERF_REG_EXTENDED_MASK | |
b0f82b81 | 48 | #endif |