Commit | Line | Data |
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2874c5fd | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
f8ef2705 PM |
2 | #ifndef __ASM_POWERPC_PCI_H |
3 | #define __ASM_POWERPC_PCI_H | |
1da177e4 LT |
4 | #ifdef __KERNEL__ |
5 | ||
6 | /* | |
1da177e4 LT |
7 | */ |
8 | ||
9 | #include <linux/types.h> | |
10 | #include <linux/slab.h> | |
11 | #include <linux/string.h> | |
0a0f0d8b | 12 | #include <linux/dma-map-ops.h> |
84be456f | 13 | #include <linux/scatterlist.h> |
1da177e4 LT |
14 | |
15 | #include <asm/machdep.h> | |
1da177e4 LT |
16 | #include <asm/io.h> |
17 | #include <asm/prom.h> | |
f8ef2705 | 18 | #include <asm/pci-bridge.h> |
1da177e4 | 19 | |
467efc2e DA |
20 | /* Return values for pci_controller_ops.probe_mode function */ |
21 | #define PCI_PROBE_NONE -1 /* Don't look at this bus at all */ | |
22 | #define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */ | |
23 | #define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */ | |
24 | ||
1da177e4 LT |
25 | #define PCIBIOS_MIN_IO 0x1000 |
26 | #define PCIBIOS_MIN_MEM 0x10000000 | |
27 | ||
f8ef2705 PM |
28 | /* Values for the `which' argument to sys_pciconfig_iobase syscall. */ |
29 | #define IOBASE_BRIDGE_NUMBER 0 | |
30 | #define IOBASE_MEMORY 1 | |
31 | #define IOBASE_IO 2 | |
32 | #define IOBASE_ISA_IO 3 | |
33 | #define IOBASE_ISA_MEM 4 | |
34 | ||
35 | /* | |
36 | * Set this to 1 if you want the kernel to re-assign all PCI | |
3fd94c6b | 37 | * bus numbers (don't do that on ppc64 yet !) |
f8ef2705 | 38 | */ |
7fe519c2 | 39 | #define pcibios_assign_all_busses() \ |
0e47ff1c | 40 | (pci_has_flag(PCI_REASSIGN_ALL_BUS)) |
1da177e4 | 41 | |
1da177e4 LT |
42 | #define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ |
43 | static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) | |
44 | { | |
45 | if (ppc_md.pci_get_legacy_ide_irq) | |
46 | return ppc_md.pci_get_legacy_ide_irq(dev, channel); | |
47 | return channel ? 15 : 14; | |
48 | } | |
49 | ||
4fc665b8 | 50 | #ifdef CONFIG_PCI |
5299709d | 51 | extern void set_pci_dma_ops(const struct dma_map_ops *dma_ops); |
4fc665b8 BB |
52 | #else /* CONFIG_PCI */ |
53 | #define set_pci_dma_ops(d) | |
4fc665b8 BB |
54 | #endif |
55 | ||
f8ef2705 | 56 | #ifdef CONFIG_PPC64 |
edb2d97e MW |
57 | |
58 | /* | |
59 | * We want to avoid touching the cacheline size or MWI bit. | |
60 | * pSeries firmware sets the cacheline size (which is not the cpu cacheline | |
61 | * size in all cases) and hardware treats MWI the same as memory write. | |
62 | */ | |
63 | #define PCI_DISABLE_MWI | |
1da177e4 | 64 | |
f8ef2705 PM |
65 | #endif /* CONFIG_PPC64 */ |
66 | ||
5516b540 KG |
67 | extern int pci_domain_nr(struct pci_bus *bus); |
68 | ||
fa462f2d BH |
69 | /* Decide whether to display the domain number in /proc */ |
70 | extern int pci_proc_domain(struct pci_bus *bus); | |
71 | ||
1da177e4 | 72 | struct vm_area_struct; |
1da177e4 | 73 | |
28f8f183 DW |
74 | /* Tell PCI code what kind of PCI resource mappings we support */ |
75 | #define HAVE_PCI_MMAP 1 | |
76 | #define ARCH_GENERIC_PCI_MMAP_RESOURCE 1 | |
77 | #define arch_can_pci_mmap_io() 1 | |
78 | #define arch_can_pci_mmap_wc() 1 | |
1da177e4 | 79 | |
e9f82cb7 BH |
80 | extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, |
81 | size_t count); | |
82 | extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, | |
83 | size_t count); | |
84 | extern int pci_mmap_legacy_page_range(struct pci_bus *bus, | |
85 | struct vm_area_struct *vma, | |
86 | enum pci_mmap_state mmap_state); | |
87 | ||
88 | #define HAVE_PCI_LEGACY 1 | |
89 | ||
facf0787 LV |
90 | extern void pcibios_claim_one_bus(struct pci_bus *b); |
91 | ||
fd6852c8 | 92 | extern void pcibios_finish_adding_to_bus(struct pci_bus *bus); |
e90a1318 | 93 | |
3fd94c6b BH |
94 | extern void pcibios_resource_survey(void); |
95 | ||
1da177e4 | 96 | extern struct pci_controller *init_phb_dynamic(struct device_node *dn); |
fd6852c8 | 97 | extern int remove_phb_dynamic(struct pci_controller *phb); |
1da177e4 | 98 | |
ead83717 JR |
99 | extern struct pci_dev *of_create_pci_dev(struct device_node *node, |
100 | struct pci_bus *bus, int devfn); | |
101 | ||
fc5f6221 BL |
102 | extern unsigned int pci_parse_of_flags(u32 addr0, int bridge); |
103 | ||
98d9f30c | 104 | extern void of_scan_pci_bridge(struct pci_dev *dev); |
ead83717 JR |
105 | |
106 | extern void of_scan_bus(struct device_node *node, struct pci_bus *bus); | |
8b8da358 | 107 | extern void of_rescan_bus(struct device_node *node, struct pci_bus *bus); |
ead83717 | 108 | |
1da177e4 LT |
109 | struct file; |
110 | extern pgprot_t pci_phys_mem_access_prot(struct file *file, | |
8b150478 | 111 | unsigned long pfn, |
1da177e4 LT |
112 | unsigned long size, |
113 | pgprot_t prot); | |
114 | ||
38973ba7 | 115 | extern resource_size_t pcibios_io_space_offset(struct pci_controller *hose); |
8b8da358 | 116 | extern void pcibios_setup_bus_self(struct pci_bus *bus); |
0ed2c722 | 117 | extern void pcibios_setup_phb_io_space(struct pci_controller *hose); |
b5d937de | 118 | extern void pcibios_scan_phb(struct pci_controller *hose); |
e9f82cb7 | 119 | |
1da177e4 | 120 | #endif /* __KERNEL__ */ |
5d2aa710 AP |
121 | |
122 | extern struct pci_dev *pnv_pci_get_gpu_dev(struct pci_dev *npdev); | |
123 | extern struct pci_dev *pnv_pci_get_npu_dev(struct pci_dev *gpdev, int index); | |
0e759bd7 AK |
124 | extern int pnv_npu2_init(struct pci_controller *hose); |
125 | extern int pnv_npu2_map_lpar_dev(struct pci_dev *gpdev, unsigned int lparid, | |
126 | unsigned long msr); | |
0bd97167 | 127 | extern int pnv_npu2_unmap_lpar_dev(struct pci_dev *gpdev); |
5d2aa710 | 128 | |
f8ef2705 | 129 | #endif /* __ASM_POWERPC_PCI_H */ |