Commit | Line | Data |
---|---|---|
047ea784 PM |
1 | #ifndef _ASM_POWERPC_PCI_BRIDGE_H |
2 | #define _ASM_POWERPC_PCI_BRIDGE_H | |
88ced031 | 3 | #ifdef __KERNEL__ |
7cd1de6b SR |
4 | /* |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version | |
8 | * 2 of the License, or (at your option) any later version. | |
9 | */ | |
5531e41b | 10 | #include <linux/pci.h> |
a4c9e328 KG |
11 | #include <linux/list.h> |
12 | #include <linux/ioport.h> | |
f4ffd5e5 | 13 | #include <asm-generic/pci-bridge.h> |
a4c9e328 | 14 | |
44ef3390 SR |
15 | struct device_node; |
16 | ||
5531e41b KG |
17 | /* |
18 | * Structure of a PCI controller (host bridge) | |
19 | */ | |
20 | struct pci_controller { | |
21 | struct pci_bus *bus; | |
a4c9e328 | 22 | char is_dynamic; |
7211991f SR |
23 | #ifdef CONFIG_PPC64 |
24 | int node; | |
25 | #endif | |
44ef3390 | 26 | struct device_node *dn; |
a4c9e328 | 27 | struct list_head list_node; |
5531e41b KG |
28 | struct device *parent; |
29 | ||
30 | int first_busno; | |
31 | int last_busno; | |
32 | int self_busno; | |
be8e60d8 | 33 | struct resource busn; |
5531e41b KG |
34 | |
35 | void __iomem *io_base_virt; | |
7211991f SR |
36 | #ifdef CONFIG_PPC64 |
37 | void *io_base_alloc; | |
38 | #endif | |
5531e41b | 39 | resource_size_t io_base_phys; |
13dccb9e | 40 | resource_size_t pci_io_size; |
5531e41b | 41 | |
e9f82cb7 BH |
42 | /* Some machines have a special region to forward the ISA |
43 | * "memory" cycles such as VGA memory regions. Left to 0 | |
44 | * if unsupported | |
45 | */ | |
46 | resource_size_t isa_mem_phys; | |
47 | resource_size_t isa_mem_size; | |
48 | ||
5531e41b | 49 | struct pci_ops *ops; |
70fbb938 SR |
50 | unsigned int __iomem *cfg_addr; |
51 | void __iomem *cfg_data; | |
5531e41b KG |
52 | |
53 | /* | |
54 | * Used for variants of PCI indirect handling and possible quirks: | |
55 | * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1 | |
56 | * EXT_REG - provides access to PCI-e extended registers | |
25985edc | 57 | * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS |
5531e41b KG |
58 | * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS |
59 | * to determine which bus number to match on when generating type0 | |
60 | * config cycles | |
62c66c8e KG |
61 | * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with |
62 | * hanging if we don't have link and try to do config cycles to | |
63 | * anything but the PHB. Only allow talking to the PHB if this is | |
64 | * set. | |
2e56ff20 | 65 | * BIG_ENDIAN - cfg_addr is a big endian register |
5ce4b596 JB |
66 | * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on |
67 | * the PLB4. Effectively disable MRM commands by setting this. | |
34642bbb KG |
68 | * FSL_CFG_REG_LINK - Freescale controller version in which the PCIe |
69 | * link status is in a RC PCIe cfg register (vs being a SoC register) | |
5531e41b | 70 | */ |
7cd1de6b SR |
71 | #define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001 |
72 | #define PPC_INDIRECT_TYPE_EXT_REG 0x00000002 | |
73 | #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004 | |
74 | #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008 | |
75 | #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010 | |
5ce4b596 | 76 | #define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020 |
34642bbb | 77 | #define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040 |
5531e41b | 78 | u32 indirect_type; |
5531e41b KG |
79 | /* Currently, we limit ourselves to 1 IO range and 3 mem |
80 | * ranges since the common pci_bus structure can't handle more | |
81 | */ | |
82 | struct resource io_resource; | |
83 | struct resource mem_resources[3]; | |
3fd47f06 | 84 | resource_size_t mem_offset[3]; |
5516b540 | 85 | int global_number; /* PCI domain number */ |
89d93347 BB |
86 | |
87 | resource_size_t dma_window_base_cur; | |
88 | resource_size_t dma_window_size; | |
89 | ||
7211991f SR |
90 | #ifdef CONFIG_PPC64 |
91 | unsigned long buid; | |
cca87d30 | 92 | struct pci_dn *pci_data; |
34642bbb | 93 | #endif /* CONFIG_PPC64 */ |
7211991f SR |
94 | |
95 | void *private_data; | |
5531e41b KG |
96 | }; |
97 | ||
5531e41b KG |
98 | /* These are used for config access before all the PCI probing |
99 | has been done. */ | |
7cd1de6b SR |
100 | extern int early_read_config_byte(struct pci_controller *hose, int bus, |
101 | int dev_fn, int where, u8 *val); | |
102 | extern int early_read_config_word(struct pci_controller *hose, int bus, | |
103 | int dev_fn, int where, u16 *val); | |
104 | extern int early_read_config_dword(struct pci_controller *hose, int bus, | |
105 | int dev_fn, int where, u32 *val); | |
106 | extern int early_write_config_byte(struct pci_controller *hose, int bus, | |
107 | int dev_fn, int where, u8 val); | |
108 | extern int early_write_config_word(struct pci_controller *hose, int bus, | |
109 | int dev_fn, int where, u16 val); | |
110 | extern int early_write_config_dword(struct pci_controller *hose, int bus, | |
111 | int dev_fn, int where, u32 val); | |
5531e41b | 112 | |
38805e5f KG |
113 | extern int early_find_capability(struct pci_controller *hose, int bus, |
114 | int dev_fn, int cap); | |
115 | ||
5531e41b | 116 | extern void setup_indirect_pci(struct pci_controller* hose, |
d94bad82 VB |
117 | resource_size_t cfg_addr, |
118 | resource_size_t cfg_data, u32 flags); | |
89c2dd62 | 119 | |
50d8f87d RI |
120 | extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn, |
121 | int offset, int len, u32 *val); | |
122 | ||
6d5f6a0e KP |
123 | extern int __indirect_read_config(struct pci_controller *hose, |
124 | unsigned char bus_number, unsigned int devfn, | |
125 | int offset, int len, u32 *val); | |
126 | ||
50d8f87d RI |
127 | extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn, |
128 | int offset, int len, u32 val); | |
129 | ||
89c2dd62 KG |
130 | static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) |
131 | { | |
132 | return bus->sysdata; | |
133 | } | |
134 | ||
98d9f30c BH |
135 | #ifndef CONFIG_PPC64 |
136 | ||
137 | extern int pci_device_from_OF_node(struct device_node *node, | |
138 | u8 *bus, u8 *devfn); | |
139 | extern void pci_create_OF_bus_map(void); | |
140 | ||
89c2dd62 KG |
141 | static inline int isa_vaddr_is_ioport(void __iomem *address) |
142 | { | |
143 | /* No specific ISA handling on ppc32 at this stage, it | |
144 | * all goes through PCI | |
145 | */ | |
146 | return 0; | |
147 | } | |
148 | ||
7cd1de6b | 149 | #else /* CONFIG_PPC64 */ |
1da177e4 | 150 | |
1635317f PM |
151 | /* |
152 | * PCI stuff, for nodes representing PCI devices, pointed to | |
153 | * by device_node->data. | |
154 | */ | |
1635317f PM |
155 | struct iommu_table; |
156 | ||
157 | struct pci_dn { | |
cca87d30 | 158 | int flags; |
a8b2f828 | 159 | #define PCI_DN_FLAG_IOV_VF 0x01 |
cca87d30 | 160 | |
7684b40c | 161 | int busno; /* pci bus number */ |
7684b40c | 162 | int devfn; /* pci device and function number */ |
c035ff1d GS |
163 | int vendor_id; /* Vendor ID */ |
164 | int device_id; /* Device ID */ | |
165 | int class_code; /* Device class code */ | |
b5166cc2 | 166 | |
cca87d30 | 167 | struct pci_dn *parent; |
c2e221e8 LV |
168 | struct pci_controller *phb; /* for pci devices */ |
169 | struct iommu_table *iommu_table; /* for phb's or bridges */ | |
c2e221e8 LV |
170 | struct device_node *node; /* back-pointer to the device_node */ |
171 | ||
172 | int pci_ext_config_space; /* for pci devices */ | |
173 | ||
b6ed42a7 | 174 | struct pci_dev *pcidev; /* back-pointer to the pci device */ |
184cd4a3 | 175 | #ifdef CONFIG_EEH |
2a0352fa | 176 | struct eeh_dev *edev; /* eeh device */ |
c2e221e8 | 177 | #endif |
184cd4a3 BH |
178 | #define IODA_INVALID_PE (-1) |
179 | #ifdef CONFIG_PPC_POWERNV | |
180 | int pe_number; | |
181 | #endif | |
cca87d30 GS |
182 | struct list_head child_list; |
183 | struct list_head list; | |
1635317f PM |
184 | }; |
185 | ||
186 | /* Get the pointer to a device_node's pci_dn */ | |
187 | #define PCI_DN(dn) ((struct pci_dn *) (dn)->data) | |
188 | ||
cca87d30 GS |
189 | extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus, |
190 | int devfn); | |
b72c1f65 | 191 | extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev); |
a8b2f828 GS |
192 | extern struct pci_dn *add_dev_pci_data(struct pci_dev *pdev); |
193 | extern void remove_dev_pci_data(struct pci_dev *pdev); | |
cca87d30 | 194 | extern void *update_dn_pci_info(struct device_node *dn, void *data); |
1da177e4 | 195 | |
40ef8cbc PM |
196 | static inline int pci_device_from_OF_node(struct device_node *np, |
197 | u8 *bus, u8 *devfn) | |
198 | { | |
199 | if (!PCI_DN(np)) | |
200 | return -ENODEV; | |
201 | *bus = PCI_DN(np)->busno; | |
202 | *devfn = PCI_DN(np)->devfn; | |
203 | return 0; | |
204 | } | |
205 | ||
2a0352fa | 206 | #if defined(CONFIG_EEH) |
e8e9b34c GS |
207 | static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn) |
208 | { | |
209 | return pdn ? pdn->edev : NULL; | |
210 | } | |
f8f7d63f | 211 | #else |
e8e9b34c | 212 | #define pdn_to_eeh_dev(x) (NULL) |
2a0352fa GS |
213 | #endif |
214 | ||
2bf6a8fa | 215 | /** Find the bus corresponding to the indicated device node */ |
7cd1de6b | 216 | extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn); |
2bf6a8fa | 217 | |
2bf6a8fa | 218 | /** Remove all of the PCI devices under this bus */ |
7cd1de6b | 219 | extern void pcibios_remove_pci_devices(struct pci_bus *bus); |
2bf6a8fa LV |
220 | |
221 | /** Discover new pci devices under this bus, and add them */ | |
7cd1de6b | 222 | extern void pcibios_add_pci_devices(struct pci_bus *bus); |
1da177e4 | 223 | |
b5166cc2 | 224 | |
3d5134ee BH |
225 | extern void isa_bridge_find_early(struct pci_controller *hose); |
226 | ||
6dfbde20 BH |
227 | static inline int isa_vaddr_is_ioport(void __iomem *address) |
228 | { | |
229 | /* Check if address hits the reserved legacy IO range */ | |
230 | unsigned long ea = (unsigned long)address; | |
231 | return ea >= ISA_IO_BASE && ea < ISA_IO_END; | |
232 | } | |
233 | ||
3d5134ee BH |
234 | extern int pcibios_unmap_io_space(struct pci_bus *bus); |
235 | extern int pcibios_map_io_space(struct pci_bus *bus); | |
236 | ||
357518fa AB |
237 | #ifdef CONFIG_NUMA |
238 | #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE)) | |
239 | #else | |
240 | #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1) | |
241 | #endif | |
242 | ||
7cd1de6b | 243 | #endif /* CONFIG_PPC64 */ |
5531e41b KG |
244 | |
245 | /* Get the PCI host controller for an OF device */ | |
7cd1de6b SR |
246 | extern struct pci_controller *pci_find_hose_for_OF_device( |
247 | struct device_node* node); | |
5531e41b KG |
248 | |
249 | /* Fill up host controller resources from the OF node */ | |
7cd1de6b SR |
250 | extern void pci_process_bridge_OF_ranges(struct pci_controller *hose, |
251 | struct device_node *dev, int primary); | |
5531e41b | 252 | |
5131d4d8 | 253 | /* Allocate & free a PCI host bridge structure */ |
7cd1de6b | 254 | extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev); |
5131d4d8 BH |
255 | extern void pcibios_free_controller(struct pci_controller *phb); |
256 | ||
5531e41b | 257 | #ifdef CONFIG_PCI |
6dfbde20 | 258 | extern int pcibios_vaddr_is_ioport(void __iomem *address); |
5531e41b | 259 | #else |
6dfbde20 BH |
260 | static inline int pcibios_vaddr_is_ioport(void __iomem *address) |
261 | { | |
262 | return 0; | |
263 | } | |
7cd1de6b | 264 | #endif /* CONFIG_PCI */ |
5531e41b | 265 | |
7cd1de6b SR |
266 | #endif /* __KERNEL__ */ |
267 | #endif /* _ASM_POWERPC_PCI_BRIDGE_H */ |