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047ea784 PM |
1 | #ifndef _ASM_POWERPC_PCI_BRIDGE_H |
2 | #define _ASM_POWERPC_PCI_BRIDGE_H | |
88ced031 | 3 | #ifdef __KERNEL__ |
7cd1de6b SR |
4 | /* |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version | |
8 | * 2 of the License, or (at your option) any later version. | |
9 | */ | |
5531e41b | 10 | #include <linux/pci.h> |
a4c9e328 KG |
11 | #include <linux/list.h> |
12 | #include <linux/ioport.h> | |
13 | ||
44ef3390 SR |
14 | struct device_node; |
15 | ||
e02def5b DA |
16 | /* |
17 | * PCI controller operations | |
18 | */ | |
19 | struct pci_controller_ops { | |
062b26ba | 20 | void (*dma_dev_setup)(struct pci_dev *pdev); |
b122c954 | 21 | void (*dma_bus_setup)(struct pci_bus *bus); |
ff9df8c8 | 22 | |
062b26ba | 23 | int (*probe_mode)(struct pci_bus *bus); |
b31e79f8 DA |
24 | |
25 | /* Called when pci_enable_device() is called. Returns true to | |
26 | * allow assignment/enabling of the device. */ | |
062b26ba | 27 | bool (*enable_device_hook)(struct pci_dev *pdev); |
542070ba | 28 | |
062b26ba | 29 | void (*disable_device)(struct pci_dev *pdev); |
abeeed6d | 30 | |
062b26ba | 31 | void (*release_device)(struct pci_dev *pdev); |
10e79630 | 32 | |
542070ba | 33 | /* Called during PCI resource reassignment */ |
062b26ba GS |
34 | resource_size_t (*window_alignment)(struct pci_bus *bus, |
35 | unsigned long type); | |
c5fcb29a GS |
36 | void (*setup_bridge)(struct pci_bus *bus, |
37 | unsigned long type); | |
062b26ba | 38 | void (*reset_secondary_bus)(struct pci_dev *pdev); |
e059b105 DA |
39 | |
40 | #ifdef CONFIG_PCI_MSI | |
062b26ba | 41 | int (*setup_msi_irqs)(struct pci_dev *pdev, |
e059b105 | 42 | int nvec, int type); |
062b26ba | 43 | void (*teardown_msi_irqs)(struct pci_dev *pdev); |
e059b105 | 44 | #endif |
3405c257 | 45 | |
062b26ba GS |
46 | int (*dma_set_mask)(struct pci_dev *pdev, u64 dma_mask); |
47 | u64 (*dma_get_required_mask)(struct pci_dev *pdev); | |
7a8e6bbf | 48 | |
062b26ba | 49 | void (*shutdown)(struct pci_controller *hose); |
e02def5b DA |
50 | }; |
51 | ||
5531e41b KG |
52 | /* |
53 | * Structure of a PCI controller (host bridge) | |
54 | */ | |
55 | struct pci_controller { | |
56 | struct pci_bus *bus; | |
a4c9e328 | 57 | char is_dynamic; |
7211991f SR |
58 | #ifdef CONFIG_PPC64 |
59 | int node; | |
60 | #endif | |
44ef3390 | 61 | struct device_node *dn; |
a4c9e328 | 62 | struct list_head list_node; |
5531e41b KG |
63 | struct device *parent; |
64 | ||
65 | int first_busno; | |
66 | int last_busno; | |
67 | int self_busno; | |
be8e60d8 | 68 | struct resource busn; |
5531e41b KG |
69 | |
70 | void __iomem *io_base_virt; | |
7211991f SR |
71 | #ifdef CONFIG_PPC64 |
72 | void *io_base_alloc; | |
73 | #endif | |
5531e41b | 74 | resource_size_t io_base_phys; |
13dccb9e | 75 | resource_size_t pci_io_size; |
5531e41b | 76 | |
e9f82cb7 BH |
77 | /* Some machines have a special region to forward the ISA |
78 | * "memory" cycles such as VGA memory regions. Left to 0 | |
79 | * if unsupported | |
80 | */ | |
81 | resource_size_t isa_mem_phys; | |
82 | resource_size_t isa_mem_size; | |
83 | ||
e02def5b | 84 | struct pci_controller_ops controller_ops; |
5531e41b | 85 | struct pci_ops *ops; |
70fbb938 SR |
86 | unsigned int __iomem *cfg_addr; |
87 | void __iomem *cfg_data; | |
5531e41b KG |
88 | |
89 | /* | |
90 | * Used for variants of PCI indirect handling and possible quirks: | |
91 | * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1 | |
92 | * EXT_REG - provides access to PCI-e extended registers | |
25985edc | 93 | * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS |
5531e41b KG |
94 | * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS |
95 | * to determine which bus number to match on when generating type0 | |
96 | * config cycles | |
62c66c8e KG |
97 | * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with |
98 | * hanging if we don't have link and try to do config cycles to | |
99 | * anything but the PHB. Only allow talking to the PHB if this is | |
100 | * set. | |
2e56ff20 | 101 | * BIG_ENDIAN - cfg_addr is a big endian register |
5ce4b596 JB |
102 | * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on |
103 | * the PLB4. Effectively disable MRM commands by setting this. | |
34642bbb KG |
104 | * FSL_CFG_REG_LINK - Freescale controller version in which the PCIe |
105 | * link status is in a RC PCIe cfg register (vs being a SoC register) | |
5531e41b | 106 | */ |
7cd1de6b SR |
107 | #define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001 |
108 | #define PPC_INDIRECT_TYPE_EXT_REG 0x00000002 | |
109 | #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004 | |
110 | #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008 | |
111 | #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010 | |
5ce4b596 | 112 | #define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020 |
34642bbb | 113 | #define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040 |
5531e41b | 114 | u32 indirect_type; |
5531e41b KG |
115 | /* Currently, we limit ourselves to 1 IO range and 3 mem |
116 | * ranges since the common pci_bus structure can't handle more | |
117 | */ | |
118 | struct resource io_resource; | |
119 | struct resource mem_resources[3]; | |
3fd47f06 | 120 | resource_size_t mem_offset[3]; |
5516b540 | 121 | int global_number; /* PCI domain number */ |
89d93347 BB |
122 | |
123 | resource_size_t dma_window_base_cur; | |
124 | resource_size_t dma_window_size; | |
125 | ||
7211991f SR |
126 | #ifdef CONFIG_PPC64 |
127 | unsigned long buid; | |
cca87d30 | 128 | struct pci_dn *pci_data; |
34642bbb | 129 | #endif /* CONFIG_PPC64 */ |
7211991f SR |
130 | |
131 | void *private_data; | |
5531e41b KG |
132 | }; |
133 | ||
5531e41b KG |
134 | /* These are used for config access before all the PCI probing |
135 | has been done. */ | |
7cd1de6b SR |
136 | extern int early_read_config_byte(struct pci_controller *hose, int bus, |
137 | int dev_fn, int where, u8 *val); | |
138 | extern int early_read_config_word(struct pci_controller *hose, int bus, | |
139 | int dev_fn, int where, u16 *val); | |
140 | extern int early_read_config_dword(struct pci_controller *hose, int bus, | |
141 | int dev_fn, int where, u32 *val); | |
142 | extern int early_write_config_byte(struct pci_controller *hose, int bus, | |
143 | int dev_fn, int where, u8 val); | |
144 | extern int early_write_config_word(struct pci_controller *hose, int bus, | |
145 | int dev_fn, int where, u16 val); | |
146 | extern int early_write_config_dword(struct pci_controller *hose, int bus, | |
147 | int dev_fn, int where, u32 val); | |
5531e41b | 148 | |
38805e5f KG |
149 | extern int early_find_capability(struct pci_controller *hose, int bus, |
150 | int dev_fn, int cap); | |
151 | ||
5531e41b | 152 | extern void setup_indirect_pci(struct pci_controller* hose, |
d94bad82 VB |
153 | resource_size_t cfg_addr, |
154 | resource_size_t cfg_data, u32 flags); | |
89c2dd62 | 155 | |
50d8f87d RI |
156 | extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn, |
157 | int offset, int len, u32 *val); | |
158 | ||
6d5f6a0e KP |
159 | extern int __indirect_read_config(struct pci_controller *hose, |
160 | unsigned char bus_number, unsigned int devfn, | |
161 | int offset, int len, u32 *val); | |
162 | ||
50d8f87d RI |
163 | extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn, |
164 | int offset, int len, u32 val); | |
165 | ||
89c2dd62 KG |
166 | static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) |
167 | { | |
168 | return bus->sysdata; | |
169 | } | |
170 | ||
98d9f30c BH |
171 | #ifndef CONFIG_PPC64 |
172 | ||
173 | extern int pci_device_from_OF_node(struct device_node *node, | |
174 | u8 *bus, u8 *devfn); | |
175 | extern void pci_create_OF_bus_map(void); | |
176 | ||
7cd1de6b | 177 | #else /* CONFIG_PPC64 */ |
1da177e4 | 178 | |
1635317f PM |
179 | /* |
180 | * PCI stuff, for nodes representing PCI devices, pointed to | |
181 | * by device_node->data. | |
182 | */ | |
1635317f PM |
183 | struct iommu_table; |
184 | ||
185 | struct pci_dn { | |
cca87d30 | 186 | int flags; |
a8b2f828 | 187 | #define PCI_DN_FLAG_IOV_VF 0x01 |
cca87d30 | 188 | |
7684b40c | 189 | int busno; /* pci bus number */ |
7684b40c | 190 | int devfn; /* pci device and function number */ |
c035ff1d GS |
191 | int vendor_id; /* Vendor ID */ |
192 | int device_id; /* Device ID */ | |
193 | int class_code; /* Device class code */ | |
b5166cc2 | 194 | |
cca87d30 | 195 | struct pci_dn *parent; |
c2e221e8 | 196 | struct pci_controller *phb; /* for pci devices */ |
b348aa65 | 197 | struct iommu_table_group *table_group; /* for phb's or bridges */ |
c2e221e8 LV |
198 | |
199 | int pci_ext_config_space; /* for pci devices */ | |
200 | ||
94973b24 | 201 | struct pci_dev *pcidev; /* back-pointer to the pci device */ |
184cd4a3 | 202 | #ifdef CONFIG_EEH |
2a0352fa | 203 | struct eeh_dev *edev; /* eeh device */ |
c2e221e8 | 204 | #endif |
689ee8c9 | 205 | #define IODA_INVALID_PE 0xFFFFFFFF |
689ee8c9 | 206 | unsigned int pe_number; |
6e628c7d | 207 | #ifdef CONFIG_PCI_IOV |
988fc3ba | 208 | int vf_index; /* VF index in the PF */ |
6e628c7d | 209 | u16 vfs_expanded; /* number of VFs IOV BAR expanded */ |
781a868f | 210 | u16 num_vfs; /* number of VFs enabled*/ |
689ee8c9 | 211 | unsigned int *pe_num_map; /* PE# for the first VF PE or array */ |
ee8222fe | 212 | bool m64_single_mode; /* Use M64 BAR in Single Mode */ |
781a868f | 213 | #define IODA_INVALID_M64 (-1) |
ee8222fe | 214 | int (*m64_map)[PCI_SRIOV_NUM_BARS]; |
6e628c7d | 215 | #endif /* CONFIG_PCI_IOV */ |
0dc2830e | 216 | int mps; /* Maximum Payload Size */ |
cca87d30 GS |
217 | struct list_head child_list; |
218 | struct list_head list; | |
d6f934fd | 219 | struct resource holes[PCI_SRIOV_NUM_BARS]; |
1635317f PM |
220 | }; |
221 | ||
222 | /* Get the pointer to a device_node's pci_dn */ | |
223 | #define PCI_DN(dn) ((struct pci_dn *) (dn)->data) | |
224 | ||
cca87d30 GS |
225 | extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus, |
226 | int devfn); | |
b72c1f65 | 227 | extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev); |
a8b2f828 GS |
228 | extern struct pci_dn *add_dev_pci_data(struct pci_dev *pdev); |
229 | extern void remove_dev_pci_data(struct pci_dev *pdev); | |
d8f66f41 GS |
230 | extern struct pci_dn *pci_add_device_node_info(struct pci_controller *hose, |
231 | struct device_node *dn); | |
de5a28ac | 232 | extern void pci_remove_device_node_info(struct device_node *dn); |
1da177e4 | 233 | |
40ef8cbc PM |
234 | static inline int pci_device_from_OF_node(struct device_node *np, |
235 | u8 *bus, u8 *devfn) | |
236 | { | |
237 | if (!PCI_DN(np)) | |
238 | return -ENODEV; | |
239 | *bus = PCI_DN(np)->busno; | |
240 | *devfn = PCI_DN(np)->devfn; | |
241 | return 0; | |
242 | } | |
243 | ||
2a0352fa | 244 | #if defined(CONFIG_EEH) |
e8e9b34c GS |
245 | static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn) |
246 | { | |
247 | return pdn ? pdn->edev : NULL; | |
248 | } | |
f8f7d63f | 249 | #else |
e8e9b34c | 250 | #define pdn_to_eeh_dev(x) (NULL) |
2a0352fa GS |
251 | #endif |
252 | ||
2bf6a8fa | 253 | /** Find the bus corresponding to the indicated device node */ |
3773dd25 | 254 | extern struct pci_bus *pci_find_bus_by_node(struct device_node *dn); |
2bf6a8fa | 255 | |
2bf6a8fa | 256 | /** Remove all of the PCI devices under this bus */ |
bd251b89 | 257 | extern void pci_hp_remove_devices(struct pci_bus *bus); |
2bf6a8fa LV |
258 | |
259 | /** Discover new pci devices under this bus, and add them */ | |
bd251b89 | 260 | extern void pci_hp_add_devices(struct pci_bus *bus); |
1da177e4 | 261 | |
3d5134ee BH |
262 | extern int pcibios_unmap_io_space(struct pci_bus *bus); |
263 | extern int pcibios_map_io_space(struct pci_bus *bus); | |
264 | ||
357518fa AB |
265 | #ifdef CONFIG_NUMA |
266 | #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE)) | |
267 | #else | |
268 | #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1) | |
269 | #endif | |
270 | ||
7cd1de6b | 271 | #endif /* CONFIG_PPC64 */ |
5531e41b KG |
272 | |
273 | /* Get the PCI host controller for an OF device */ | |
7cd1de6b SR |
274 | extern struct pci_controller *pci_find_hose_for_OF_device( |
275 | struct device_node* node); | |
5531e41b KG |
276 | |
277 | /* Fill up host controller resources from the OF node */ | |
7cd1de6b SR |
278 | extern void pci_process_bridge_OF_ranges(struct pci_controller *hose, |
279 | struct device_node *dev, int primary); | |
5531e41b | 280 | |
5131d4d8 | 281 | /* Allocate & free a PCI host bridge structure */ |
7cd1de6b | 282 | extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev); |
5131d4d8 | 283 | extern void pcibios_free_controller(struct pci_controller *phb); |
2dd9c11b | 284 | extern void pcibios_free_controller_deferred(struct pci_host_bridge *bridge); |
5131d4d8 | 285 | |
5531e41b | 286 | #ifdef CONFIG_PCI |
6dfbde20 | 287 | extern int pcibios_vaddr_is_ioport(void __iomem *address); |
5531e41b | 288 | #else |
6dfbde20 BH |
289 | static inline int pcibios_vaddr_is_ioport(void __iomem *address) |
290 | { | |
291 | return 0; | |
292 | } | |
7cd1de6b | 293 | #endif /* CONFIG_PCI */ |
5531e41b | 294 | |
7cd1de6b SR |
295 | #endif /* __KERNEL__ */ |
296 | #endif /* _ASM_POWERPC_PCI_BRIDGE_H */ |