[linux-2.6-block.git] / arch / powerpc / include / asm / pci-bridge.h

#ifndef _ASM_POWERPC_PCI_BRIDGE_H
#define _ASM_POWERPC_PCI_BRIDGE_H
#ifdef __KERNEL__
/*
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
#include <linux/pci.h>
#include <linux/list.h>
#include <linux/ioport.h>

struct device_node;

enum {
	/* Force re-assigning all resources (ignore firmware
	 * setup completely)
	 */
	PCI_REASSIGN_ALL_RSRC	= 0x00000001,

	/* Re-assign all bus numbers */
	PCI_REASSIGN_ALL_BUS	= 0x00000002,

	/* Do not try to assign, just use existing setup */
	PCI_PROBE_ONLY		= 0x00000004,

	/* Don't bother with ISA alignment unless the bridge has
	 * ISA forwarding enabled
	 */
	PCI_CAN_SKIP_ISA_ALIGN	= 0x00000008,

	/* Enable domain numbers in /proc */
	PCI_ENABLE_PROC_DOMAINS	= 0x00000010,
	/* ... except for domain 0 */
	PCI_COMPAT_DOMAIN_0		= 0x00000020,
};
#ifdef CONFIG_PCI
extern unsigned int pci_flags;

static inline void pci_set_flags(int flags)
{
	pci_flags = flags;
}

static inline void pci_add_flags(int flags)
{
	pci_flags |= flags;
}

static inline int pci_has_flag(int flag)
{
	return (pci_flags & flag);
}
#else
static inline void pci_set_flags(int flags) { }
static inline void pci_add_flags(int flags) { }
static inline int pci_has_flag(int flag)
{
	return 0;
}
#endif


/*
 * Structure of a PCI controller (host bridge)
 */
struct pci_controller {
	struct pci_bus *bus;
	char is_dynamic;
#ifdef CONFIG_PPC64
	int node;
#endif
	struct device_node *dn;
	struct list_head list_node;
	struct device *parent;

	int first_busno;
	int last_busno;
	int self_busno;

	void __iomem *io_base_virt;
#ifdef CONFIG_PPC64
	void *io_base_alloc;
#endif
	resource_size_t io_base_phys;
	resource_size_t pci_io_size;

	/* Some machines (PReP) have a non 1:1 mapping of
	 * the PCI memory space in the CPU bus space
	 */
	resource_size_t pci_mem_offset;

	/* Some machines have a special region to forward the ISA
	 * "memory" cycles such as VGA memory regions. Left to 0
	 * if unsupported
	 */
	resource_size_t	isa_mem_phys;
	resource_size_t	isa_mem_size;

	struct pci_ops *ops;
	unsigned int __iomem *cfg_addr;
	void __iomem *cfg_data;

	/*
	 * Used for variants of PCI indirect handling and possible quirks:
	 *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
	 *  EXT_REG - provides access to PCI-e extended registers
	 *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
	 *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
	 *   to determine which bus number to match on when generating type0
	 *   config cycles
	 *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
	 *   hanging if we don't have link and try to do config cycles to
	 *   anything but the PHB.  Only allow talking to the PHB if this is
	 *   set.
	 *  BIG_ENDIAN - cfg_addr is a big endian register
	 *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
	 *   the PLB4.  Effectively disable MRM commands by setting this.
	 */
#define PPC_INDIRECT_TYPE_SET_CFG_TYPE		0x00000001
#define PPC_INDIRECT_TYPE_EXT_REG		0x00000002
#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS	0x00000004
#define PPC_INDIRECT_TYPE_NO_PCIE_LINK		0x00000008
#define PPC_INDIRECT_TYPE_BIG_ENDIAN		0x00000010
#define PPC_INDIRECT_TYPE_BROKEN_MRM		0x00000020
	u32 indirect_type;
	/* Currently, we limit ourselves to 1 IO range and 3 mem
	 * ranges since the common pci_bus structure can't handle more
	 */
	struct resource	io_resource;
	struct resource mem_resources[3];
	int global_number;		/* PCI domain number */

	resource_size_t dma_window_base_cur;
	resource_size_t dma_window_size;

#ifdef CONFIG_PPC64
	unsigned long buid;

	void *private_data;
#endif	/* CONFIG_PPC64 */
};

/* These are used for config access before all the PCI probing
   has been done. */
extern int early_read_config_byte(struct pci_controller *hose, int bus,
			int dev_fn, int where, u8 *val);
extern int early_read_config_word(struct pci_controller *hose, int bus,
			int dev_fn, int where, u16 *val);
extern int early_read_config_dword(struct pci_controller *hose, int bus,
			int dev_fn, int where, u32 *val);
extern int early_write_config_byte(struct pci_controller *hose, int bus,
			int dev_fn, int where, u8 val);
extern int early_write_config_word(struct pci_controller *hose, int bus,
			int dev_fn, int where, u16 val);
extern int early_write_config_dword(struct pci_controller *hose, int bus,
			int dev_fn, int where, u32 val);

extern int early_find_capability(struct pci_controller *hose, int bus,
				 int dev_fn, int cap);

extern void setup_indirect_pci(struct pci_controller* hose,
			       resource_size_t cfg_addr,
			       resource_size_t cfg_data, u32 flags);

static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
{
	return bus->sysdata;
}

#ifndef CONFIG_PPC64

static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
{
	struct pci_controller *host;

	if (bus->self)
		return pci_device_to_OF_node(bus->self);
	host = pci_bus_to_host(bus);
	return host ? host->dn : NULL;
}

static inline int isa_vaddr_is_ioport(void __iomem *address)
{
	/* No specific ISA handling on ppc32 at this stage, it
	 * all goes through PCI
	 */
	return 0;
}

#else	/* CONFIG_PPC64 */

/*
 * PCI stuff, for nodes representing PCI devices, pointed to
 * by device_node->data.
 */
struct iommu_table;

struct pci_dn {
	int	busno;			/* pci bus number */
	int	devfn;			/* pci device and function number */

	struct  pci_controller *phb;	/* for pci devices */
	struct	iommu_table *iommu_table;	/* for phb's or bridges */
	struct	device_node *node;	/* back-pointer to the device_node */

	int	pci_ext_config_space;	/* for pci devices */

#ifdef CONFIG_EEH
	struct	pci_dev *pcidev;	/* back-pointer to the pci device */
	int	class_code;		/* pci device class */
	int	eeh_mode;		/* See eeh.h for possible EEH_MODEs */
	int	eeh_config_addr;
	int	eeh_pe_config_addr; /* new-style partition endpoint address */
	int	eeh_check_count;	/* # times driver ignored error */
	int	eeh_freeze_count;	/* # times this device froze up. */
	int	eeh_false_positives;	/* # times this device reported #ff's */
	u32	config_space[16];	/* saved PCI config space */
#endif
};

/* Get the pointer to a device_node's pci_dn */
#define PCI_DN(dn)	((struct pci_dn *) (dn)->data)

extern struct device_node *fetch_dev_dn(struct pci_dev *dev);
extern void * update_dn_pci_info(struct device_node *dn, void *data);

/* Get a device_node from a pci_dev.  This code must be fast except
 * in the case where the sysdata is incorrect and needs to be fixed
 * up (this will only happen once). */
static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
{
	return dev->dev.of_node ? dev->dev.of_node : fetch_dev_dn(dev);
}

static inline int pci_device_from_OF_node(struct device_node *np,
					  u8 *bus, u8 *devfn)
{
	if (!PCI_DN(np))
		return -ENODEV;
	*bus = PCI_DN(np)->busno;
	*devfn = PCI_DN(np)->devfn;
	return 0;
}

static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
{
	if (bus->self)
		return pci_device_to_OF_node(bus->self);
	else
		return bus->dev.of_node; /* Must be root bus (PHB) */
}

/** Find the bus corresponding to the indicated device node */
extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);

/** Remove all of the PCI devices under this bus */
extern void pcibios_remove_pci_devices(struct pci_bus *bus);

/** Discover new pci devices under this bus, and add them */
extern void pcibios_add_pci_devices(struct pci_bus *bus);


extern void isa_bridge_find_early(struct pci_controller *hose);

static inline int isa_vaddr_is_ioport(void __iomem *address)
{
	/* Check if address hits the reserved legacy IO range */
	unsigned long ea = (unsigned long)address;
	return ea >= ISA_IO_BASE && ea < ISA_IO_END;
}

extern int pcibios_unmap_io_space(struct pci_bus *bus);
extern int pcibios_map_io_space(struct pci_bus *bus);

#ifdef CONFIG_NUMA
#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = (NODE))
#else
#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = -1)
#endif

#endif	/* CONFIG_PPC64 */

/* Get the PCI host controller for an OF device */
extern struct pci_controller *pci_find_hose_for_OF_device(
			struct device_node* node);

/* Fill up host controller resources from the OF node */
extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
			struct device_node *dev, int primary);

/* Allocate & free a PCI host bridge structure */
extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
extern void pcibios_free_controller(struct pci_controller *phb);
extern void pcibios_setup_phb_resources(struct pci_controller *hose);

#ifdef CONFIG_PCI
extern int pcibios_vaddr_is_ioport(void __iomem *address);
#else
static inline int pcibios_vaddr_is_ioport(void __iomem *address)
{
	return 0;
}
#endif	/* CONFIG_PCI */

#endif	/* __KERNEL__ */
#endif	/* _ASM_POWERPC_PCI_BRIDGE_H */
Commit	Line	Data
047ea784 PM	1	#ifndef _ASM_POWERPC_PCI_BRIDGE_H
047ea784 PM	2	#define _ASM_POWERPC_PCI_BRIDGE_H
88ced031	3	#ifdef __KERNEL__
7cd1de6b SR	4	/*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version
	8	* 2 of the License, or (at your option) any later version.
	9	*/
5531e41b	10	#include <linux/pci.h>
a4c9e328 KG	11	#include <linux/list.h>
	12	#include <linux/ioport.h>
	13
44ef3390 SR	14	struct device_node;
44ef3390 SR	15
fc3fb71c BH	16	enum {
	17	/* Force re-assigning all resources (ignore firmware
	18	* setup completely)
	19	*/
0e47ff1c	20	PCI_REASSIGN_ALL_RSRC = 0x00000001,
fc3fb71c BH	21
fc3fb71c BH	22	/* Re-assign all bus numbers */
0e47ff1c	23	PCI_REASSIGN_ALL_BUS = 0x00000002,
fc3fb71c BH	24
fc3fb71c BH	25	/* Do not try to assign, just use existing setup */
0e47ff1c	26	PCI_PROBE_ONLY = 0x00000004,
fc3fb71c BH	27
	28	/* Don't bother with ISA alignment unless the bridge has
	29	* ISA forwarding enabled
	30	*/
0e47ff1c	31	PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
fa462f2d BH	32
fa462f2d BH	33	/* Enable domain numbers in /proc */
0e47ff1c	34	PCI_ENABLE_PROC_DOMAINS = 0x00000010,
fa462f2d	35	/* ... except for domain 0 */
0e47ff1c	36	PCI_COMPAT_DOMAIN_0 = 0x00000020,
fc3fb71c	37	};
7fe519c2	38	#ifdef CONFIG_PCI
0e47ff1c	39	extern unsigned int pci_flags;
7fe519c2	40
0e47ff1c	41	static inline void pci_set_flags(int flags)
7fe519c2	42	{
0e47ff1c	43	pci_flags = flags;
7fe519c2 JB	44	}
7fe519c2 JB	45
0e47ff1c	46	static inline void pci_add_flags(int flags)
7fe519c2	47	{
0e47ff1c	48	pci_flags \|= flags;
7fe519c2 JB	49	}
7fe519c2 JB	50
0e47ff1c	51	static inline int pci_has_flag(int flag)
7fe519c2	52	{
0e47ff1c	53	return (pci_flags & flag);
7fe519c2 JB	54	}
7fe519c2 JB	55	#else
0e47ff1c RH	56	static inline void pci_set_flags(int flags) { }
	57	static inline void pci_add_flags(int flags) { }
	58	static inline int pci_has_flag(int flag)
7fe519c2 JB	59	{
	60	return 0;
	61	}
	62	#endif
fc3fb71c BH	63
fc3fb71c BH	64
5531e41b KG	65	/*
	66	* Structure of a PCI controller (host bridge)
	67	*/
	68	struct pci_controller {
	69	struct pci_bus *bus;
a4c9e328	70	char is_dynamic;
7211991f SR	71	#ifdef CONFIG_PPC64
	72	int node;
	73	#endif
44ef3390	74	struct device_node *dn;
a4c9e328	75	struct list_head list_node;
5531e41b KG	76	struct device *parent;
	77
	78	int first_busno;
	79	int last_busno;
	80	int self_busno;
	81
	82	void __iomem *io_base_virt;
7211991f SR	83	#ifdef CONFIG_PPC64
	84	void *io_base_alloc;
	85	#endif
5531e41b	86	resource_size_t io_base_phys;
13dccb9e	87	resource_size_t pci_io_size;
5531e41b KG	88
	89	/* Some machines (PReP) have a non 1:1 mapping of
	90	* the PCI memory space in the CPU bus space
	91	*/
	92	resource_size_t pci_mem_offset;
	93
e9f82cb7 BH	94	/* Some machines have a special region to forward the ISA
	95	* "memory" cycles such as VGA memory regions. Left to 0
	96	* if unsupported
	97	*/
	98	resource_size_t isa_mem_phys;
	99	resource_size_t isa_mem_size;
	100
5531e41b	101	struct pci_ops *ops;
70fbb938 SR	102	unsigned int __iomem *cfg_addr;
70fbb938 SR	103	void __iomem *cfg_data;
5531e41b KG	104
	105	/*
	106	* Used for variants of PCI indirect handling and possible quirks:
	107	* SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
	108	* EXT_REG - provides access to PCI-e extended registers
25985edc	109	* SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
5531e41b KG	110	* on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
	111	* to determine which bus number to match on when generating type0
	112	* config cycles
62c66c8e KG	113	* NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
	114	* hanging if we don't have link and try to do config cycles to
	115	* anything but the PHB. Only allow talking to the PHB if this is
	116	* set.
2e56ff20	117	* BIG_ENDIAN - cfg_addr is a big endian register
5ce4b596 JB	118	* BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
5ce4b596 JB	119	* the PLB4. Effectively disable MRM commands by setting this.
5531e41b	120	*/
7cd1de6b SR	121	#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
	122	#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
	123	#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
	124	#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
	125	#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
5ce4b596	126	#define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
5531e41b	127	u32 indirect_type;
5531e41b KG	128	/* Currently, we limit ourselves to 1 IO range and 3 mem
	129	* ranges since the common pci_bus structure can't handle more
	130	*/
	131	struct resource io_resource;
	132	struct resource mem_resources[3];
5516b540	133	int global_number; /* PCI domain number */
89d93347 BB	134
	135	resource_size_t dma_window_base_cur;
	136	resource_size_t dma_window_size;
	137
7211991f SR	138	#ifdef CONFIG_PPC64
7211991f SR	139	unsigned long buid;
7211991f SR	140
	141	void *private_data;
	142	#endif /* CONFIG_PPC64 */
5531e41b KG	143	};
5531e41b KG	144
5531e41b KG	145	/* These are used for config access before all the PCI probing
5531e41b KG	146	has been done. */
7cd1de6b SR	147	extern int early_read_config_byte(struct pci_controller *hose, int bus,
	148	int dev_fn, int where, u8 *val);
	149	extern int early_read_config_word(struct pci_controller *hose, int bus,
	150	int dev_fn, int where, u16 *val);
	151	extern int early_read_config_dword(struct pci_controller *hose, int bus,
	152	int dev_fn, int where, u32 *val);
	153	extern int early_write_config_byte(struct pci_controller *hose, int bus,
	154	int dev_fn, int where, u8 val);
	155	extern int early_write_config_word(struct pci_controller *hose, int bus,
	156	int dev_fn, int where, u16 val);
	157	extern int early_write_config_dword(struct pci_controller *hose, int bus,
	158	int dev_fn, int where, u32 val);
5531e41b	159
38805e5f KG	160	extern int early_find_capability(struct pci_controller *hose, int bus,
	161	int dev_fn, int cap);
	162
5531e41b	163	extern void setup_indirect_pci(struct pci_controller* hose,
d94bad82 VB	164	resource_size_t cfg_addr,
d94bad82 VB	165	resource_size_t cfg_data, u32 flags);
89c2dd62	166
89c2dd62 KG	167	static inline struct pci_controller pci_bus_to_host(const struct pci_bus bus)
	168	{
	169	return bus->sysdata;
	170	}
	171
b5d937de GL	172	#ifndef CONFIG_PPC64
b5d937de GL	173
04bea68b SAS	174	static inline struct device_node pci_bus_to_OF_node(struct pci_bus bus)
	175	{
	176	struct pci_controller *host;
	177
	178	if (bus->self)
	179	return pci_device_to_OF_node(bus->self);
	180	host = pci_bus_to_host(bus);
	181	return host ? host->dn : NULL;
	182	}
	183
89c2dd62 KG	184	static inline int isa_vaddr_is_ioport(void __iomem *address)
	185	{
	186	/* No specific ISA handling on ppc32 at this stage, it
	187	* all goes through PCI
	188	*/
	189	return 0;
	190	}
	191
7cd1de6b	192	#else /* CONFIG_PPC64 */
1da177e4	193
1635317f PM	194	/*
	195	* PCI stuff, for nodes representing PCI devices, pointed to
	196	* by device_node->data.
	197	*/
1635317f PM	198	struct iommu_table;
	199
	200	struct pci_dn {
7684b40c	201	int busno; /* pci bus number */
7684b40c	202	int devfn; /* pci device and function number */
b5166cc2	203
c2e221e8 LV	204	struct pci_controller phb; / for pci devices */
c2e221e8 LV	205	struct iommu_table iommu_table; / for phb's or bridges */
c2e221e8 LV	206	struct device_node node; / back-pointer to the device_node */
	207
	208	int pci_ext_config_space; /* for pci devices */
	209
	210	#ifdef CONFIG_EEH
b6ed42a7	211	struct pci_dev pcidev; / back-pointer to the pci device */
86bcab49	212	int class_code; /* pci device class */
1635317f PM	213	int eeh_mode; /* See eeh.h for possible EEH_MODEs */
1635317f PM	214	int eeh_config_addr;
25e591f6	215	int eeh_pe_config_addr; /* new-style partition endpoint address */
7cd1de6b SR	216	int eeh_check_count; /* # times driver ignored error */
	217	int eeh_freeze_count; /* # times this device froze up. */
	218	int eeh_false_positives; /* # times this device reported #ff's */
1635317f	219	u32 config_space[16]; /* saved PCI config space */
c2e221e8	220	#endif
1635317f PM	221	};
	222
	223	/* Get the pointer to a device_node's pci_dn */
	224	#define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
	225
7cd1de6b	226	extern struct device_node fetch_dev_dn(struct pci_dev dev);
2eb4afb6	227	extern void * update_dn_pci_info(struct device_node dn, void data);
1da177e4	228
1635317f PM	229	/* Get a device_node from a pci_dev. This code must be fast except
1635317f PM	230	* in the case where the sysdata is incorrect and needs to be fixed
b5d937de	231	* up (this will only happen once). */
1da177e4 LT	232	static inline struct device_node pci_device_to_OF_node(struct pci_dev dev)
1da177e4 LT	233	{
b5d937de	234	return dev->dev.of_node ? dev->dev.of_node : fetch_dev_dn(dev);
1da177e4 LT	235	}
1da177e4 LT	236
40ef8cbc PM	237	static inline int pci_device_from_OF_node(struct device_node *np,
	238	u8 bus, u8 devfn)
	239	{
	240	if (!PCI_DN(np))
	241	return -ENODEV;
	242	*bus = PCI_DN(np)->busno;
	243	*devfn = PCI_DN(np)->devfn;
	244	return 0;
	245	}
	246
1da177e4 LT	247	static inline struct device_node pci_bus_to_OF_node(struct pci_bus bus)
	248	{
	249	if (bus->self)
	250	return pci_device_to_OF_node(bus->self);
	251	else
b5d937de	252	return bus->dev.of_node; /* Must be root bus (PHB) */
1da177e4 LT	253	}
1da177e4 LT	254
2bf6a8fa	255	/** Find the bus corresponding to the indicated device node */
7cd1de6b	256	extern struct pci_bus pcibios_find_pci_bus(struct device_node dn);
2bf6a8fa	257
2bf6a8fa	258	/** Remove all of the PCI devices under this bus */
7cd1de6b	259	extern void pcibios_remove_pci_devices(struct pci_bus *bus);
2bf6a8fa LV	260
2bf6a8fa LV	261	/** Discover new pci devices under this bus, and add them */
7cd1de6b	262	extern void pcibios_add_pci_devices(struct pci_bus *bus);
1da177e4	263
b5166cc2	264
3d5134ee BH	265	extern void isa_bridge_find_early(struct pci_controller *hose);
3d5134ee BH	266
6dfbde20 BH	267	static inline int isa_vaddr_is_ioport(void __iomem *address)
	268	{
	269	/* Check if address hits the reserved legacy IO range */
	270	unsigned long ea = (unsigned long)address;
	271	return ea >= ISA_IO_BASE && ea < ISA_IO_END;
	272	}
	273
3d5134ee BH	274	extern int pcibios_unmap_io_space(struct pci_bus *bus);
	275	extern int pcibios_map_io_space(struct pci_bus *bus);
	276
357518fa AB	277	#ifdef CONFIG_NUMA
	278	#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
	279	#else
	280	#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
	281	#endif
	282
7cd1de6b	283	#endif /* CONFIG_PPC64 */
5531e41b KG	284
5531e41b KG	285	/* Get the PCI host controller for an OF device */
7cd1de6b SR	286	extern struct pci_controller *pci_find_hose_for_OF_device(
7cd1de6b SR	287	struct device_node* node);
5531e41b KG	288
5531e41b KG	289	/* Fill up host controller resources from the OF node */
7cd1de6b SR	290	extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
7cd1de6b SR	291	struct device_node *dev, int primary);
5531e41b	292
5131d4d8	293	/* Allocate & free a PCI host bridge structure */
7cd1de6b	294	extern struct pci_controller pcibios_alloc_controller(struct device_node dev);
5131d4d8	295	extern void pcibios_free_controller(struct pci_controller *phb);
53280323	296	extern void pcibios_setup_phb_resources(struct pci_controller *hose);
5131d4d8	297
5531e41b	298	#ifdef CONFIG_PCI
6dfbde20	299	extern int pcibios_vaddr_is_ioport(void __iomem *address);
5531e41b	300	#else
6dfbde20 BH	301	static inline int pcibios_vaddr_is_ioport(void __iomem *address)
	302	{
	303	return 0;
	304	}
7cd1de6b	305	#endif /* CONFIG_PCI */
5531e41b	306
7cd1de6b SR	307	#endif /* __KERNEL__ */
7cd1de6b SR	308	#endif /* _ASM_POWERPC_PCI_BRIDGE_H */