[linux-2.6-block.git] / arch / powerpc / include / asm / pci-bridge.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef _ASM_POWERPC_PCI_BRIDGE_H
#define _ASM_POWERPC_PCI_BRIDGE_H
#ifdef __KERNEL__
/*
 */
#include <linux/pci.h>
#include <linux/list.h>
#include <linux/ioport.h>
#include <linux/numa.h>

struct device_node;

/*
 * PCI controller operations
 */
struct pci_controller_ops {
	void		(*dma_dev_setup)(struct pci_dev *pdev);
	void		(*dma_bus_setup)(struct pci_bus *bus);
	bool		(*iommu_bypass_supported)(struct pci_dev *pdev,
				u64 mask);

	int		(*probe_mode)(struct pci_bus *bus);

	/* Called when pci_enable_device() is called. Returns true to
	 * allow assignment/enabling of the device. */
	bool		(*enable_device_hook)(struct pci_dev *pdev);

	void		(*disable_device)(struct pci_dev *pdev);

	void		(*release_device)(struct pci_dev *pdev);

	/* Called during PCI resource reassignment */
	resource_size_t (*window_alignment)(struct pci_bus *bus,
					    unsigned long type);
	void		(*setup_bridge)(struct pci_bus *bus,
					unsigned long type);
	void		(*reset_secondary_bus)(struct pci_dev *pdev);

#ifdef CONFIG_PCI_MSI
	int		(*setup_msi_irqs)(struct pci_dev *pdev,
					  int nvec, int type);
	void		(*teardown_msi_irqs)(struct pci_dev *pdev);
#endif

	void		(*shutdown)(struct pci_controller *hose);
};

/*
 * Structure of a PCI controller (host bridge)
 */
struct pci_controller {
	struct pci_bus *bus;
	char is_dynamic;
#ifdef CONFIG_PPC64
	int node;
#endif
	struct device_node *dn;
	struct list_head list_node;
	struct device *parent;

	int first_busno;
	int last_busno;
	int self_busno;
	struct resource busn;

	void __iomem *io_base_virt;
#ifdef CONFIG_PPC64
	void __iomem *io_base_alloc;
#endif
	resource_size_t io_base_phys;
	resource_size_t pci_io_size;

	/* Some machines have a special region to forward the ISA
	 * "memory" cycles such as VGA memory regions. Left to 0
	 * if unsupported
	 */
	resource_size_t	isa_mem_phys;
	resource_size_t	isa_mem_size;

	struct pci_controller_ops controller_ops;
	struct pci_ops *ops;
	unsigned int __iomem *cfg_addr;
	void __iomem *cfg_data;

	/*
	 * Used for variants of PCI indirect handling and possible quirks:
	 *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
	 *  EXT_REG - provides access to PCI-e extended registers
	 *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
	 *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
	 *   to determine which bus number to match on when generating type0
	 *   config cycles
	 *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
	 *   hanging if we don't have link and try to do config cycles to
	 *   anything but the PHB.  Only allow talking to the PHB if this is
	 *   set.
	 *  BIG_ENDIAN - cfg_addr is a big endian register
	 *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
	 *   the PLB4.  Effectively disable MRM commands by setting this.
	 *  FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
	 *   link status is in a RC PCIe cfg register (vs being a SoC register)
	 */
#define PPC_INDIRECT_TYPE_SET_CFG_TYPE		0x00000001
#define PPC_INDIRECT_TYPE_EXT_REG		0x00000002
#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS	0x00000004
#define PPC_INDIRECT_TYPE_NO_PCIE_LINK		0x00000008
#define PPC_INDIRECT_TYPE_BIG_ENDIAN		0x00000010
#define PPC_INDIRECT_TYPE_BROKEN_MRM		0x00000020
#define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK	0x00000040
	u32 indirect_type;
	/* Currently, we limit ourselves to 1 IO range and 3 mem
	 * ranges since the common pci_bus structure can't handle more
	 */
	struct resource	io_resource;
	struct resource mem_resources[3];
	resource_size_t mem_offset[3];
	int global_number;		/* PCI domain number */

	resource_size_t dma_window_base_cur;
	resource_size_t dma_window_size;

#ifdef CONFIG_PPC64
	unsigned long buid;
	struct pci_dn *pci_data;
#endif	/* CONFIG_PPC64 */

	void *private_data;

	/* IRQ domain hierarchy */
	struct irq_domain	*dev_domain;
	struct irq_domain	*msi_domain;
	struct fwnode_handle	*fwnode;
};

/* These are used for config access before all the PCI probing
   has been done. */
extern int early_read_config_byte(struct pci_controller *hose, int bus,
			int dev_fn, int where, u8 *val);
extern int early_read_config_word(struct pci_controller *hose, int bus,
			int dev_fn, int where, u16 *val);
extern int early_read_config_dword(struct pci_controller *hose, int bus,
			int dev_fn, int where, u32 *val);
extern int early_write_config_byte(struct pci_controller *hose, int bus,
			int dev_fn, int where, u8 val);
extern int early_write_config_word(struct pci_controller *hose, int bus,
			int dev_fn, int where, u16 val);
extern int early_write_config_dword(struct pci_controller *hose, int bus,
			int dev_fn, int where, u32 val);

extern int early_find_capability(struct pci_controller *hose, int bus,
				 int dev_fn, int cap);

extern void setup_indirect_pci(struct pci_controller* hose,
			       resource_size_t cfg_addr,
			       resource_size_t cfg_data, u32 flags);

extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
				int offset, int len, u32 *val);

extern int __indirect_read_config(struct pci_controller *hose,
				  unsigned char bus_number, unsigned int devfn,
				  int offset, int len, u32 *val);

extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
				 int offset, int len, u32 val);

static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
{
	return bus->sysdata;
}

extern int pci_device_from_OF_node(struct device_node *node,
				   u8 *bus, u8 *devfn);
#ifndef CONFIG_PPC64

extern void pci_create_OF_bus_map(void);

#else	/* CONFIG_PPC64 */

/*
 * PCI stuff, for nodes representing PCI devices, pointed to
 * by device_node->data.
 */
struct iommu_table;

struct pci_dn {
	int     flags;
#define PCI_DN_FLAG_IOV_VF	0x01
#define PCI_DN_FLAG_DEAD	0x02    /* Device has been hot-removed */

	int	busno;			/* pci bus number */
	int	devfn;			/* pci device and function number */
	int	vendor_id;		/* Vendor ID */
	int	device_id;		/* Device ID */
	int	class_code;		/* Device class code */

	struct  pci_dn *parent;
	struct  pci_controller *phb;	/* for pci devices */
	struct	iommu_table_group *table_group;	/* for phb's or bridges */

	int	pci_ext_config_space;	/* for pci devices */
#ifdef CONFIG_EEH
	struct eeh_dev *edev;		/* eeh device */
#endif
#define IODA_INVALID_PE		0xFFFFFFFF
	unsigned int pe_number;
#ifdef CONFIG_PCI_IOV
	u16     vfs_expanded;		/* number of VFs IOV BAR expanded */
	u16     num_vfs;		/* number of VFs enabled*/
	unsigned int *pe_num_map;	/* PE# for the first VF PE or array */
	bool    m64_single_mode;	/* Use M64 BAR in Single Mode */
#define IODA_INVALID_M64        (-1)
	int     (*m64_map)[PCI_SRIOV_NUM_BARS];	/* Only used on powernv */
	int     last_allow_rc;			/* Only used on pseries */
#endif /* CONFIG_PCI_IOV */
	int	mps;			/* Maximum Payload Size */
	struct list_head child_list;
	struct list_head list;
	struct resource holes[PCI_SRIOV_NUM_BARS];
};

/* Get the pointer to a device_node's pci_dn */
#define PCI_DN(dn)	((struct pci_dn *) (dn)->data)

extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
					   int devfn);
extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
extern struct pci_dn *pci_add_device_node_info(struct pci_controller *hose,
					       struct device_node *dn);
extern void pci_remove_device_node_info(struct device_node *dn);

#ifdef CONFIG_PCI_IOV
struct pci_dn *add_sriov_vf_pdns(struct pci_dev *pdev);
void remove_sriov_vf_pdns(struct pci_dev *pdev);
#endif

#if defined(CONFIG_EEH)
static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn)
{
	return pdn ? pdn->edev : NULL;
}
#else
#define pdn_to_eeh_dev(x)	(NULL)
#endif

/** Find the bus corresponding to the indicated device node */
extern struct pci_bus *pci_find_bus_by_node(struct device_node *dn);

/** Remove all of the PCI devices under this bus */
extern void pci_hp_remove_devices(struct pci_bus *bus);

/** Discover new pci devices under this bus, and add them */
extern void pci_hp_add_devices(struct pci_bus *bus);

extern int pcibios_unmap_io_space(struct pci_bus *bus);
extern int pcibios_map_io_space(struct pci_bus *bus);

#ifdef CONFIG_NUMA
#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = (NODE))
#else
#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = NUMA_NO_NODE)
#endif

#endif	/* CONFIG_PPC64 */

/* Get the PCI host controller for an OF device */
extern struct pci_controller *pci_find_hose_for_OF_device(
			struct device_node* node);

extern struct pci_controller *pci_find_controller_for_domain(int domain_nr);

/* Fill up host controller resources from the OF node */
extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
			struct device_node *dev, int primary);

/* Allocate & free a PCI host bridge structure */
extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
extern void pcibios_free_controller(struct pci_controller *phb);
extern void pcibios_free_controller_deferred(struct pci_host_bridge *bridge);

#ifdef CONFIG_PCI
extern int pcibios_vaddr_is_ioport(void __iomem *address);
#else
static inline int pcibios_vaddr_is_ioport(void __iomem *address)
{
	return 0;
}
#endif	/* CONFIG_PCI */

#endif	/* __KERNEL__ */
#endif	/* _ASM_POWERPC_PCI_BRIDGE_H */
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
047ea784 PM	2	#ifndef _ASM_POWERPC_PCI_BRIDGE_H
047ea784 PM	3	#define _ASM_POWERPC_PCI_BRIDGE_H
88ced031	4	#ifdef __KERNEL__
7cd1de6b	5	/*
7cd1de6b	6	*/
5531e41b	7	#include <linux/pci.h>
a4c9e328 KG	8	#include <linux/list.h>
a4c9e328 KG	9	#include <linux/ioport.h>
98fa15f3	10	#include <linux/numa.h>
a4c9e328	11
44ef3390 SR	12	struct device_node;
44ef3390 SR	13
e02def5b DA	14	/*
	15	* PCI controller operations
	16	*/
	17	struct pci_controller_ops {
062b26ba	18	void (dma_dev_setup)(struct pci_dev pdev);
b122c954	19	void (dma_bus_setup)(struct pci_bus bus);
8617a5c5 CH	20	bool (iommu_bypass_supported)(struct pci_dev pdev,
8617a5c5 CH	21	u64 mask);
ff9df8c8	22
062b26ba	23	int (probe_mode)(struct pci_bus bus);
b31e79f8 DA	24
	25	/* Called when pci_enable_device() is called. Returns true to
	26	* allow assignment/enabling of the device. */
062b26ba	27	bool (enable_device_hook)(struct pci_dev pdev);
542070ba	28
062b26ba	29	void (disable_device)(struct pci_dev pdev);
abeeed6d	30
062b26ba	31	void (release_device)(struct pci_dev pdev);
10e79630	32
542070ba	33	/* Called during PCI resource reassignment */
062b26ba GS	34	resource_size_t (window_alignment)(struct pci_bus bus,
062b26ba GS	35	unsigned long type);
c5fcb29a GS	36	void (setup_bridge)(struct pci_bus bus,
c5fcb29a GS	37	unsigned long type);
062b26ba	38	void (reset_secondary_bus)(struct pci_dev pdev);
e059b105 DA	39
e059b105 DA	40	#ifdef CONFIG_PCI_MSI
062b26ba	41	int (setup_msi_irqs)(struct pci_dev pdev,
e059b105	42	int nvec, int type);
062b26ba	43	void (teardown_msi_irqs)(struct pci_dev pdev);
e059b105	44	#endif
3405c257	45
062b26ba	46	void (shutdown)(struct pci_controller hose);
e02def5b DA	47	};
e02def5b DA	48
5531e41b KG	49	/*
	50	* Structure of a PCI controller (host bridge)
	51	*/
	52	struct pci_controller {
	53	struct pci_bus *bus;
a4c9e328	54	char is_dynamic;
7211991f SR	55	#ifdef CONFIG_PPC64
	56	int node;
	57	#endif
44ef3390	58	struct device_node *dn;
a4c9e328	59	struct list_head list_node;
5531e41b KG	60	struct device *parent;
	61
	62	int first_busno;
	63	int last_busno;
	64	int self_busno;
be8e60d8	65	struct resource busn;
5531e41b KG	66
5531e41b KG	67	void __iomem *io_base_virt;
7211991f	68	#ifdef CONFIG_PPC64
b274014c	69	void __iomem *io_base_alloc;
7211991f	70	#endif
5531e41b	71	resource_size_t io_base_phys;
13dccb9e	72	resource_size_t pci_io_size;
5531e41b	73
e9f82cb7 BH	74	/* Some machines have a special region to forward the ISA
	75	* "memory" cycles such as VGA memory regions. Left to 0
	76	* if unsupported
	77	*/
	78	resource_size_t isa_mem_phys;
	79	resource_size_t isa_mem_size;
	80
e02def5b	81	struct pci_controller_ops controller_ops;
5531e41b	82	struct pci_ops *ops;
70fbb938 SR	83	unsigned int __iomem *cfg_addr;
70fbb938 SR	84	void __iomem *cfg_data;
5531e41b KG	85
	86	/*
	87	* Used for variants of PCI indirect handling and possible quirks:
	88	* SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
	89	* EXT_REG - provides access to PCI-e extended registers
25985edc	90	* SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
5531e41b KG	91	* on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
	92	* to determine which bus number to match on when generating type0
	93	* config cycles
62c66c8e KG	94	* NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
	95	* hanging if we don't have link and try to do config cycles to
	96	* anything but the PHB. Only allow talking to the PHB if this is
	97	* set.
2e56ff20	98	* BIG_ENDIAN - cfg_addr is a big endian register
5ce4b596 JB	99	* BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
5ce4b596 JB	100	* the PLB4. Effectively disable MRM commands by setting this.
34642bbb KG	101	* FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
34642bbb KG	102	* link status is in a RC PCIe cfg register (vs being a SoC register)
5531e41b	103	*/
7cd1de6b SR	104	#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
	105	#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
	106	#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
	107	#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
	108	#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
5ce4b596	109	#define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
34642bbb	110	#define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040
5531e41b	111	u32 indirect_type;
5531e41b KG	112	/* Currently, we limit ourselves to 1 IO range and 3 mem
	113	* ranges since the common pci_bus structure can't handle more
	114	*/
	115	struct resource io_resource;
	116	struct resource mem_resources[3];
3fd47f06	117	resource_size_t mem_offset[3];
5516b540	118	int global_number; /* PCI domain number */
89d93347 BB	119
	120	resource_size_t dma_window_base_cur;
	121	resource_size_t dma_window_size;
	122
7211991f SR	123	#ifdef CONFIG_PPC64
7211991f SR	124	unsigned long buid;
cca87d30	125	struct pci_dn *pci_data;
34642bbb	126	#endif /* CONFIG_PPC64 */
7211991f SR	127
7211991f SR	128	void *private_data;
a5f3d2c1 CLG	129
	130	/* IRQ domain hierarchy */
	131	struct irq_domain *dev_domain;
	132	struct irq_domain *msi_domain;
	133	struct fwnode_handle *fwnode;
5531e41b KG	134	};
5531e41b KG	135
5531e41b KG	136	/* These are used for config access before all the PCI probing
5531e41b KG	137	has been done. */
7cd1de6b SR	138	extern int early_read_config_byte(struct pci_controller *hose, int bus,
	139	int dev_fn, int where, u8 *val);
	140	extern int early_read_config_word(struct pci_controller *hose, int bus,
	141	int dev_fn, int where, u16 *val);
	142	extern int early_read_config_dword(struct pci_controller *hose, int bus,
	143	int dev_fn, int where, u32 *val);
	144	extern int early_write_config_byte(struct pci_controller *hose, int bus,
	145	int dev_fn, int where, u8 val);
	146	extern int early_write_config_word(struct pci_controller *hose, int bus,
	147	int dev_fn, int where, u16 val);
	148	extern int early_write_config_dword(struct pci_controller *hose, int bus,
	149	int dev_fn, int where, u32 val);
5531e41b	150
38805e5f KG	151	extern int early_find_capability(struct pci_controller *hose, int bus,
	152	int dev_fn, int cap);
	153
5531e41b	154	extern void setup_indirect_pci(struct pci_controller* hose,
d94bad82 VB	155	resource_size_t cfg_addr,
d94bad82 VB	156	resource_size_t cfg_data, u32 flags);
89c2dd62	157
50d8f87d RI	158	extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
	159	int offset, int len, u32 *val);
	160
6d5f6a0e KP	161	extern int __indirect_read_config(struct pci_controller *hose,
	162	unsigned char bus_number, unsigned int devfn,
	163	int offset, int len, u32 *val);
	164
50d8f87d RI	165	extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
	166	int offset, int len, u32 val);
	167
89c2dd62 KG	168	static inline struct pci_controller pci_bus_to_host(const struct pci_bus bus)
	169	{
	170	return bus->sysdata;
	171	}
	172
98d9f30c BH	173	extern int pci_device_from_OF_node(struct device_node *node,
98d9f30c BH	174	u8 bus, u8 devfn);
0aa297e7 CL	175	#ifndef CONFIG_PPC64
0aa297e7 CL	176
98d9f30c BH	177	extern void pci_create_OF_bus_map(void);
98d9f30c BH	178
7cd1de6b	179	#else /* CONFIG_PPC64 */
1da177e4	180
1635317f PM	181	/*
	182	* PCI stuff, for nodes representing PCI devices, pointed to
	183	* by device_node->data.
	184	*/
1635317f PM	185	struct iommu_table;
	186
	187	struct pci_dn {
cca87d30	188	int flags;
a8b2f828	189	#define PCI_DN_FLAG_IOV_VF 0x01
5ef753ae	190	#define PCI_DN_FLAG_DEAD 0x02 /* Device has been hot-removed */
cca87d30	191
7684b40c	192	int busno; /* pci bus number */
7684b40c	193	int devfn; /* pci device and function number */
c035ff1d GS	194	int vendor_id; /* Vendor ID */
	195	int device_id; /* Device ID */
	196	int class_code; /* Device class code */
b5166cc2	197
cca87d30	198	struct pci_dn *parent;
c2e221e8	199	struct pci_controller phb; / for pci devices */
b348aa65	200	struct iommu_table_group table_group; / for phb's or bridges */
c2e221e8 LV	201
c2e221e8 LV	202	int pci_ext_config_space; /* for pci devices */
184cd4a3	203	#ifdef CONFIG_EEH
2a0352fa	204	struct eeh_dev edev; / eeh device */
c2e221e8	205	#endif
689ee8c9	206	#define IODA_INVALID_PE 0xFFFFFFFF
689ee8c9	207	unsigned int pe_number;
6e628c7d WY	208	#ifdef CONFIG_PCI_IOV
6e628c7d WY	209	u16 vfs_expanded; /* number of VFs IOV BAR expanded */
781a868f	210	u16 num_vfs; /* number of VFs enabled*/
689ee8c9	211	unsigned int pe_num_map; / PE# for the first VF PE or array */
ee8222fe	212	bool m64_single_mode; /* Use M64 BAR in Single Mode */
781a868f	213	#define IODA_INVALID_M64 (-1)
565a744d BL	214	int (m64_map)[PCI_SRIOV_NUM_BARS]; / Only used on powernv */
565a744d BL	215	int last_allow_rc; /* Only used on pseries */
6e628c7d	216	#endif /* CONFIG_PCI_IOV */
0dc2830e	217	int mps; /* Maximum Payload Size */
cca87d30 GS	218	struct list_head child_list;
cca87d30 GS	219	struct list_head list;
d6f934fd	220	struct resource holes[PCI_SRIOV_NUM_BARS];
1635317f PM	221	};
	222
	223	/* Get the pointer to a device_node's pci_dn */
	224	#define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
	225
cca87d30 GS	226	extern struct pci_dn pci_get_pdn_by_devfn(struct pci_bus bus,
cca87d30 GS	227	int devfn);
b72c1f65	228	extern struct pci_dn pci_get_pdn(struct pci_dev pdev);
d8f66f41 GS	229	extern struct pci_dn pci_add_device_node_info(struct pci_controller hose,
d8f66f41 GS	230	struct device_node *dn);
de5a28ac	231	extern void pci_remove_device_node_info(struct device_node *dn);
1da177e4	232
8cd6aacc OH	233	#ifdef CONFIG_PCI_IOV
	234	struct pci_dn add_sriov_vf_pdns(struct pci_dev pdev);
	235	void remove_sriov_vf_pdns(struct pci_dev *pdev);
	236	#endif
	237
2a0352fa	238	#if defined(CONFIG_EEH)
e8e9b34c GS	239	static inline struct eeh_dev pdn_to_eeh_dev(struct pci_dn pdn)
	240	{
	241	return pdn ? pdn->edev : NULL;
	242	}
f8f7d63f	243	#else
e8e9b34c	244	#define pdn_to_eeh_dev(x) (NULL)
2a0352fa GS	245	#endif
2a0352fa GS	246
2bf6a8fa	247	/** Find the bus corresponding to the indicated device node */
3773dd25	248	extern struct pci_bus pci_find_bus_by_node(struct device_node dn);
2bf6a8fa	249
2bf6a8fa	250	/** Remove all of the PCI devices under this bus */
bd251b89	251	extern void pci_hp_remove_devices(struct pci_bus *bus);
2bf6a8fa LV	252
2bf6a8fa LV	253	/** Discover new pci devices under this bus, and add them */
bd251b89	254	extern void pci_hp_add_devices(struct pci_bus *bus);
1da177e4	255
3d5134ee BH	256	extern int pcibios_unmap_io_space(struct pci_bus *bus);
	257	extern int pcibios_map_io_space(struct pci_bus *bus);
	258
357518fa AB	259	#ifdef CONFIG_NUMA
	260	#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
	261	#else
98fa15f3	262	#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = NUMA_NO_NODE)
357518fa AB	263	#endif
357518fa AB	264
7cd1de6b	265	#endif /* CONFIG_PPC64 */
5531e41b KG	266
5531e41b KG	267	/* Get the PCI host controller for an OF device */
7cd1de6b SR	268	extern struct pci_controller *pci_find_hose_for_OF_device(
7cd1de6b SR	269	struct device_node* node);
5531e41b	270
67060cb1 OH	271	extern struct pci_controller *pci_find_controller_for_domain(int domain_nr);
67060cb1 OH	272
5531e41b	273	/* Fill up host controller resources from the OF node */
7cd1de6b SR	274	extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
7cd1de6b SR	275	struct device_node *dev, int primary);
5531e41b	276
5131d4d8	277	/* Allocate & free a PCI host bridge structure */
7cd1de6b	278	extern struct pci_controller pcibios_alloc_controller(struct device_node dev);
5131d4d8	279	extern void pcibios_free_controller(struct pci_controller *phb);
2dd9c11b	280	extern void pcibios_free_controller_deferred(struct pci_host_bridge *bridge);
5131d4d8	281
5531e41b	282	#ifdef CONFIG_PCI
6dfbde20	283	extern int pcibios_vaddr_is_ioport(void __iomem *address);
5531e41b	284	#else
6dfbde20 BH	285	static inline int pcibios_vaddr_is_ioport(void __iomem *address)
	286	{
	287	return 0;
	288	}
7cd1de6b	289	#endif /* CONFIG_PCI */
5531e41b	290
7cd1de6b SR	291	#endif /* __KERNEL__ */
7cd1de6b SR	292	#endif /* _ASM_POWERPC_PCI_BRIDGE_H */