[linux-2.6-block.git] / arch / powerpc / include / asm / pci-bridge.h

#ifndef _ASM_POWERPC_PCI_BRIDGE_H
#define _ASM_POWERPC_PCI_BRIDGE_H
#ifdef __KERNEL__
/*
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
#include <linux/pci.h>
#include <linux/list.h>
#include <linux/ioport.h>
#include <linux/numa.h>

struct device_node;

/*
 * PCI controller operations
 */
struct pci_controller_ops {
	void		(*dma_dev_setup)(struct pci_dev *pdev);
	void		(*dma_bus_setup)(struct pci_bus *bus);
	bool		(*iommu_bypass_supported)(struct pci_dev *pdev,
				u64 mask);

	int		(*probe_mode)(struct pci_bus *bus);

	/* Called when pci_enable_device() is called. Returns true to
	 * allow assignment/enabling of the device. */
	bool		(*enable_device_hook)(struct pci_dev *pdev);

	void		(*disable_device)(struct pci_dev *pdev);

	void		(*release_device)(struct pci_dev *pdev);

	/* Called during PCI resource reassignment */
	resource_size_t (*window_alignment)(struct pci_bus *bus,
					    unsigned long type);
	void		(*setup_bridge)(struct pci_bus *bus,
					unsigned long type);
	void		(*reset_secondary_bus)(struct pci_dev *pdev);

#ifdef CONFIG_PCI_MSI
	int		(*setup_msi_irqs)(struct pci_dev *pdev,
					  int nvec, int type);
	void		(*teardown_msi_irqs)(struct pci_dev *pdev);
#endif

	void		(*shutdown)(struct pci_controller *hose);
};

/*
 * Structure of a PCI controller (host bridge)
 */
struct pci_controller {
	struct pci_bus *bus;
	char is_dynamic;
#ifdef CONFIG_PPC64
	int node;
#endif
	struct device_node *dn;
	struct list_head list_node;
	struct device *parent;

	int first_busno;
	int last_busno;
	int self_busno;
	struct resource busn;

	void __iomem *io_base_virt;
#ifdef CONFIG_PPC64
	void *io_base_alloc;
#endif
	resource_size_t io_base_phys;
	resource_size_t pci_io_size;

	/* Some machines have a special region to forward the ISA
	 * "memory" cycles such as VGA memory regions. Left to 0
	 * if unsupported
	 */
	resource_size_t	isa_mem_phys;
	resource_size_t	isa_mem_size;

	struct pci_controller_ops controller_ops;
	struct pci_ops *ops;
	unsigned int __iomem *cfg_addr;
	void __iomem *cfg_data;

	/*
	 * Used for variants of PCI indirect handling and possible quirks:
	 *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
	 *  EXT_REG - provides access to PCI-e extended registers
	 *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
	 *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
	 *   to determine which bus number to match on when generating type0
	 *   config cycles
	 *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
	 *   hanging if we don't have link and try to do config cycles to
	 *   anything but the PHB.  Only allow talking to the PHB if this is
	 *   set.
	 *  BIG_ENDIAN - cfg_addr is a big endian register
	 *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
	 *   the PLB4.  Effectively disable MRM commands by setting this.
	 *  FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
	 *   link status is in a RC PCIe cfg register (vs being a SoC register)
	 */
#define PPC_INDIRECT_TYPE_SET_CFG_TYPE		0x00000001
#define PPC_INDIRECT_TYPE_EXT_REG		0x00000002
#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS	0x00000004
#define PPC_INDIRECT_TYPE_NO_PCIE_LINK		0x00000008
#define PPC_INDIRECT_TYPE_BIG_ENDIAN		0x00000010
#define PPC_INDIRECT_TYPE_BROKEN_MRM		0x00000020
#define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK	0x00000040
	u32 indirect_type;
	/* Currently, we limit ourselves to 1 IO range and 3 mem
	 * ranges since the common pci_bus structure can't handle more
	 */
	struct resource	io_resource;
	struct resource mem_resources[3];
	resource_size_t mem_offset[3];
	int global_number;		/* PCI domain number */

	resource_size_t dma_window_base_cur;
	resource_size_t dma_window_size;

#ifdef CONFIG_PPC64
	unsigned long buid;
	struct pci_dn *pci_data;
#endif	/* CONFIG_PPC64 */

	void *private_data;
	struct npu *npu;
};

/* These are used for config access before all the PCI probing
   has been done. */
extern int early_read_config_byte(struct pci_controller *hose, int bus,
			int dev_fn, int where, u8 *val);
extern int early_read_config_word(struct pci_controller *hose, int bus,
			int dev_fn, int where, u16 *val);
extern int early_read_config_dword(struct pci_controller *hose, int bus,
			int dev_fn, int where, u32 *val);
extern int early_write_config_byte(struct pci_controller *hose, int bus,
			int dev_fn, int where, u8 val);
extern int early_write_config_word(struct pci_controller *hose, int bus,
			int dev_fn, int where, u16 val);
extern int early_write_config_dword(struct pci_controller *hose, int bus,
			int dev_fn, int where, u32 val);

extern int early_find_capability(struct pci_controller *hose, int bus,
				 int dev_fn, int cap);

extern void setup_indirect_pci(struct pci_controller* hose,
			       resource_size_t cfg_addr,
			       resource_size_t cfg_data, u32 flags);

extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
				int offset, int len, u32 *val);

extern int __indirect_read_config(struct pci_controller *hose,
				  unsigned char bus_number, unsigned int devfn,
				  int offset, int len, u32 *val);

extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
				 int offset, int len, u32 val);

static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
{
	return bus->sysdata;
}

#ifndef CONFIG_PPC64

extern int pci_device_from_OF_node(struct device_node *node,
				   u8 *bus, u8 *devfn);
extern void pci_create_OF_bus_map(void);

#else	/* CONFIG_PPC64 */

/*
 * PCI stuff, for nodes representing PCI devices, pointed to
 * by device_node->data.
 */
struct iommu_table;

struct pci_dn {
	int     flags;
#define PCI_DN_FLAG_IOV_VF	0x01

	int	busno;			/* pci bus number */
	int	devfn;			/* pci device and function number */
	int	vendor_id;		/* Vendor ID */
	int	device_id;		/* Device ID */
	int	class_code;		/* Device class code */

	struct  pci_dn *parent;
	struct  pci_controller *phb;	/* for pci devices */
	struct	iommu_table_group *table_group;	/* for phb's or bridges */

	int	pci_ext_config_space;	/* for pci devices */
#ifdef CONFIG_EEH
	struct eeh_dev *edev;		/* eeh device */
#endif
#define IODA_INVALID_PE		0xFFFFFFFF
	unsigned int pe_number;
#ifdef CONFIG_PCI_IOV
	int     vf_index;		/* VF index in the PF */
	u16     vfs_expanded;		/* number of VFs IOV BAR expanded */
	u16     num_vfs;		/* number of VFs enabled*/
	unsigned int *pe_num_map;	/* PE# for the first VF PE or array */
	bool    m64_single_mode;	/* Use M64 BAR in Single Mode */
#define IODA_INVALID_M64        (-1)
	int     (*m64_map)[PCI_SRIOV_NUM_BARS];	/* Only used on powernv */
	int     last_allow_rc;			/* Only used on pseries */
#endif /* CONFIG_PCI_IOV */
	int	mps;			/* Maximum Payload Size */
	struct list_head child_list;
	struct list_head list;
	struct resource holes[PCI_SRIOV_NUM_BARS];
};

/* Get the pointer to a device_node's pci_dn */
#define PCI_DN(dn)	((struct pci_dn *) (dn)->data)

extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
					   int devfn);
extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
extern struct pci_dn *add_dev_pci_data(struct pci_dev *pdev);
extern void remove_dev_pci_data(struct pci_dev *pdev);
extern struct pci_dn *pci_add_device_node_info(struct pci_controller *hose,
					       struct device_node *dn);
extern void pci_remove_device_node_info(struct device_node *dn);

static inline int pci_device_from_OF_node(struct device_node *np,
					  u8 *bus, u8 *devfn)
{
	if (!PCI_DN(np))
		return -ENODEV;
	*bus = PCI_DN(np)->busno;
	*devfn = PCI_DN(np)->devfn;
	return 0;
}

#if defined(CONFIG_EEH)
static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn)
{
	return pdn ? pdn->edev : NULL;
}
#else
#define pdn_to_eeh_dev(x)	(NULL)
#endif

/** Find the bus corresponding to the indicated device node */
extern struct pci_bus *pci_find_bus_by_node(struct device_node *dn);

/** Remove all of the PCI devices under this bus */
extern void pci_hp_remove_devices(struct pci_bus *bus);

/** Discover new pci devices under this bus, and add them */
extern void pci_hp_add_devices(struct pci_bus *bus);

extern int pcibios_unmap_io_space(struct pci_bus *bus);
extern int pcibios_map_io_space(struct pci_bus *bus);

#ifdef CONFIG_NUMA
#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = (NODE))
#else
#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = NUMA_NO_NODE)
#endif

#endif	/* CONFIG_PPC64 */

/* Get the PCI host controller for an OF device */
extern struct pci_controller *pci_find_hose_for_OF_device(
			struct device_node* node);

extern struct pci_controller *pci_find_controller_for_domain(int domain_nr);

/* Fill up host controller resources from the OF node */
extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
			struct device_node *dev, int primary);

/* Allocate & free a PCI host bridge structure */
extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
extern void pcibios_free_controller(struct pci_controller *phb);
extern void pcibios_free_controller_deferred(struct pci_host_bridge *bridge);

#ifdef CONFIG_PCI
extern int pcibios_vaddr_is_ioport(void __iomem *address);
#else
static inline int pcibios_vaddr_is_ioport(void __iomem *address)
{
	return 0;
}
#endif	/* CONFIG_PCI */

#endif	/* __KERNEL__ */
#endif	/* _ASM_POWERPC_PCI_BRIDGE_H */
Commit	Line	Data
047ea784 PM	1	#ifndef _ASM_POWERPC_PCI_BRIDGE_H
047ea784 PM	2	#define _ASM_POWERPC_PCI_BRIDGE_H
88ced031	3	#ifdef __KERNEL__
7cd1de6b SR	4	/*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version
	8	* 2 of the License, or (at your option) any later version.
	9	*/
5531e41b	10	#include <linux/pci.h>
a4c9e328 KG	11	#include <linux/list.h>
a4c9e328 KG	12	#include <linux/ioport.h>
98fa15f3	13	#include <linux/numa.h>
a4c9e328	14
44ef3390 SR	15	struct device_node;
44ef3390 SR	16
e02def5b DA	17	/*
	18	* PCI controller operations
	19	*/
	20	struct pci_controller_ops {
062b26ba	21	void (dma_dev_setup)(struct pci_dev pdev);
b122c954	22	void (dma_bus_setup)(struct pci_bus bus);
8617a5c5 CH	23	bool (iommu_bypass_supported)(struct pci_dev pdev,
8617a5c5 CH	24	u64 mask);
ff9df8c8	25
062b26ba	26	int (probe_mode)(struct pci_bus bus);
b31e79f8 DA	27
	28	/* Called when pci_enable_device() is called. Returns true to
	29	* allow assignment/enabling of the device. */
062b26ba	30	bool (enable_device_hook)(struct pci_dev pdev);
542070ba	31
062b26ba	32	void (disable_device)(struct pci_dev pdev);
abeeed6d	33
062b26ba	34	void (release_device)(struct pci_dev pdev);
10e79630	35
542070ba	36	/* Called during PCI resource reassignment */
062b26ba GS	37	resource_size_t (window_alignment)(struct pci_bus bus,
062b26ba GS	38	unsigned long type);
c5fcb29a GS	39	void (setup_bridge)(struct pci_bus bus,
c5fcb29a GS	40	unsigned long type);
062b26ba	41	void (reset_secondary_bus)(struct pci_dev pdev);
e059b105 DA	42
e059b105 DA	43	#ifdef CONFIG_PCI_MSI
062b26ba	44	int (setup_msi_irqs)(struct pci_dev pdev,
e059b105	45	int nvec, int type);
062b26ba	46	void (teardown_msi_irqs)(struct pci_dev pdev);
e059b105	47	#endif
3405c257	48
062b26ba	49	void (shutdown)(struct pci_controller hose);
e02def5b DA	50	};
e02def5b DA	51
5531e41b KG	52	/*
	53	* Structure of a PCI controller (host bridge)
	54	*/
	55	struct pci_controller {
	56	struct pci_bus *bus;
a4c9e328	57	char is_dynamic;
7211991f SR	58	#ifdef CONFIG_PPC64
	59	int node;
	60	#endif
44ef3390	61	struct device_node *dn;
a4c9e328	62	struct list_head list_node;
5531e41b KG	63	struct device *parent;
	64
	65	int first_busno;
	66	int last_busno;
	67	int self_busno;
be8e60d8	68	struct resource busn;
5531e41b KG	69
5531e41b KG	70	void __iomem *io_base_virt;
7211991f SR	71	#ifdef CONFIG_PPC64
	72	void *io_base_alloc;
	73	#endif
5531e41b	74	resource_size_t io_base_phys;
13dccb9e	75	resource_size_t pci_io_size;
5531e41b	76
e9f82cb7 BH	77	/* Some machines have a special region to forward the ISA
	78	* "memory" cycles such as VGA memory regions. Left to 0
	79	* if unsupported
	80	*/
	81	resource_size_t isa_mem_phys;
	82	resource_size_t isa_mem_size;
	83
e02def5b	84	struct pci_controller_ops controller_ops;
5531e41b	85	struct pci_ops *ops;
70fbb938 SR	86	unsigned int __iomem *cfg_addr;
70fbb938 SR	87	void __iomem *cfg_data;
5531e41b KG	88
	89	/*
	90	* Used for variants of PCI indirect handling and possible quirks:
	91	* SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
	92	* EXT_REG - provides access to PCI-e extended registers
25985edc	93	* SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
5531e41b KG	94	* on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
	95	* to determine which bus number to match on when generating type0
	96	* config cycles
62c66c8e KG	97	* NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
	98	* hanging if we don't have link and try to do config cycles to
	99	* anything but the PHB. Only allow talking to the PHB if this is
	100	* set.
2e56ff20	101	* BIG_ENDIAN - cfg_addr is a big endian register
5ce4b596 JB	102	* BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
5ce4b596 JB	103	* the PLB4. Effectively disable MRM commands by setting this.
34642bbb KG	104	* FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
34642bbb KG	105	* link status is in a RC PCIe cfg register (vs being a SoC register)
5531e41b	106	*/
7cd1de6b SR	107	#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
	108	#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
	109	#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
	110	#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
	111	#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
5ce4b596	112	#define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
34642bbb	113	#define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040
5531e41b	114	u32 indirect_type;
5531e41b KG	115	/* Currently, we limit ourselves to 1 IO range and 3 mem
	116	* ranges since the common pci_bus structure can't handle more
	117	*/
	118	struct resource io_resource;
	119	struct resource mem_resources[3];
3fd47f06	120	resource_size_t mem_offset[3];
5516b540	121	int global_number; /* PCI domain number */
89d93347 BB	122
	123	resource_size_t dma_window_base_cur;
	124	resource_size_t dma_window_size;
	125
7211991f SR	126	#ifdef CONFIG_PPC64
7211991f SR	127	unsigned long buid;
cca87d30	128	struct pci_dn *pci_data;
34642bbb	129	#endif /* CONFIG_PPC64 */
7211991f SR	130
7211991f SR	131	void *private_data;
46a1449d	132	struct npu *npu;
5531e41b KG	133	};
5531e41b KG	134
5531e41b KG	135	/* These are used for config access before all the PCI probing
5531e41b KG	136	has been done. */
7cd1de6b SR	137	extern int early_read_config_byte(struct pci_controller *hose, int bus,
	138	int dev_fn, int where, u8 *val);
	139	extern int early_read_config_word(struct pci_controller *hose, int bus,
	140	int dev_fn, int where, u16 *val);
	141	extern int early_read_config_dword(struct pci_controller *hose, int bus,
	142	int dev_fn, int where, u32 *val);
	143	extern int early_write_config_byte(struct pci_controller *hose, int bus,
	144	int dev_fn, int where, u8 val);
	145	extern int early_write_config_word(struct pci_controller *hose, int bus,
	146	int dev_fn, int where, u16 val);
	147	extern int early_write_config_dword(struct pci_controller *hose, int bus,
	148	int dev_fn, int where, u32 val);
5531e41b	149
38805e5f KG	150	extern int early_find_capability(struct pci_controller *hose, int bus,
	151	int dev_fn, int cap);
	152
5531e41b	153	extern void setup_indirect_pci(struct pci_controller* hose,
d94bad82 VB	154	resource_size_t cfg_addr,
d94bad82 VB	155	resource_size_t cfg_data, u32 flags);
89c2dd62	156
50d8f87d RI	157	extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
	158	int offset, int len, u32 *val);
	159
6d5f6a0e KP	160	extern int __indirect_read_config(struct pci_controller *hose,
	161	unsigned char bus_number, unsigned int devfn,
	162	int offset, int len, u32 *val);
	163
50d8f87d RI	164	extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
	165	int offset, int len, u32 val);
	166
89c2dd62 KG	167	static inline struct pci_controller pci_bus_to_host(const struct pci_bus bus)
	168	{
	169	return bus->sysdata;
	170	}
	171
98d9f30c BH	172	#ifndef CONFIG_PPC64
	173
	174	extern int pci_device_from_OF_node(struct device_node *node,
	175	u8 bus, u8 devfn);
	176	extern void pci_create_OF_bus_map(void);
	177
7cd1de6b	178	#else /* CONFIG_PPC64 */
1da177e4	179
1635317f PM	180	/*
	181	* PCI stuff, for nodes representing PCI devices, pointed to
	182	* by device_node->data.
	183	*/
1635317f PM	184	struct iommu_table;
	185
	186	struct pci_dn {
cca87d30	187	int flags;
a8b2f828	188	#define PCI_DN_FLAG_IOV_VF 0x01
cca87d30	189
7684b40c	190	int busno; /* pci bus number */
7684b40c	191	int devfn; /* pci device and function number */
c035ff1d GS	192	int vendor_id; /* Vendor ID */
	193	int device_id; /* Device ID */
	194	int class_code; /* Device class code */
b5166cc2	195
cca87d30	196	struct pci_dn *parent;
c2e221e8	197	struct pci_controller phb; / for pci devices */
b348aa65	198	struct iommu_table_group table_group; / for phb's or bridges */
c2e221e8 LV	199
c2e221e8 LV	200	int pci_ext_config_space; /* for pci devices */
184cd4a3	201	#ifdef CONFIG_EEH
2a0352fa	202	struct eeh_dev edev; / eeh device */
c2e221e8	203	#endif
689ee8c9	204	#define IODA_INVALID_PE 0xFFFFFFFF
689ee8c9	205	unsigned int pe_number;
6e628c7d	206	#ifdef CONFIG_PCI_IOV
988fc3ba	207	int vf_index; /* VF index in the PF */
6e628c7d	208	u16 vfs_expanded; /* number of VFs IOV BAR expanded */
781a868f	209	u16 num_vfs; /* number of VFs enabled*/
689ee8c9	210	unsigned int pe_num_map; / PE# for the first VF PE or array */
ee8222fe	211	bool m64_single_mode; /* Use M64 BAR in Single Mode */
781a868f	212	#define IODA_INVALID_M64 (-1)
565a744d BL	213	int (m64_map)[PCI_SRIOV_NUM_BARS]; / Only used on powernv */
565a744d BL	214	int last_allow_rc; /* Only used on pseries */
6e628c7d	215	#endif /* CONFIG_PCI_IOV */
0dc2830e	216	int mps; /* Maximum Payload Size */
cca87d30 GS	217	struct list_head child_list;
cca87d30 GS	218	struct list_head list;
d6f934fd	219	struct resource holes[PCI_SRIOV_NUM_BARS];
1635317f PM	220	};
	221
	222	/* Get the pointer to a device_node's pci_dn */
	223	#define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
	224
cca87d30 GS	225	extern struct pci_dn pci_get_pdn_by_devfn(struct pci_bus bus,
cca87d30 GS	226	int devfn);
b72c1f65	227	extern struct pci_dn pci_get_pdn(struct pci_dev pdev);
a8b2f828 GS	228	extern struct pci_dn add_dev_pci_data(struct pci_dev pdev);
a8b2f828 GS	229	extern void remove_dev_pci_data(struct pci_dev *pdev);
d8f66f41 GS	230	extern struct pci_dn pci_add_device_node_info(struct pci_controller hose,
d8f66f41 GS	231	struct device_node *dn);
de5a28ac	232	extern void pci_remove_device_node_info(struct device_node *dn);
1da177e4	233
40ef8cbc PM	234	static inline int pci_device_from_OF_node(struct device_node *np,
	235	u8 bus, u8 devfn)
	236	{
	237	if (!PCI_DN(np))
	238	return -ENODEV;
	239	*bus = PCI_DN(np)->busno;
	240	*devfn = PCI_DN(np)->devfn;
	241	return 0;
	242	}
	243
2a0352fa	244	#if defined(CONFIG_EEH)
e8e9b34c GS	245	static inline struct eeh_dev pdn_to_eeh_dev(struct pci_dn pdn)
	246	{
	247	return pdn ? pdn->edev : NULL;
	248	}
f8f7d63f	249	#else
e8e9b34c	250	#define pdn_to_eeh_dev(x) (NULL)
2a0352fa GS	251	#endif
2a0352fa GS	252
2bf6a8fa	253	/** Find the bus corresponding to the indicated device node */
3773dd25	254	extern struct pci_bus pci_find_bus_by_node(struct device_node dn);
2bf6a8fa	255
2bf6a8fa	256	/** Remove all of the PCI devices under this bus */
bd251b89	257	extern void pci_hp_remove_devices(struct pci_bus *bus);
2bf6a8fa LV	258
2bf6a8fa LV	259	/** Discover new pci devices under this bus, and add them */
bd251b89	260	extern void pci_hp_add_devices(struct pci_bus *bus);
1da177e4	261
3d5134ee BH	262	extern int pcibios_unmap_io_space(struct pci_bus *bus);
	263	extern int pcibios_map_io_space(struct pci_bus *bus);
	264
357518fa AB	265	#ifdef CONFIG_NUMA
	266	#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
	267	#else
98fa15f3	268	#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = NUMA_NO_NODE)
357518fa AB	269	#endif
357518fa AB	270
7cd1de6b	271	#endif /* CONFIG_PPC64 */
5531e41b KG	272
5531e41b KG	273	/* Get the PCI host controller for an OF device */
7cd1de6b SR	274	extern struct pci_controller *pci_find_hose_for_OF_device(
7cd1de6b SR	275	struct device_node* node);
5531e41b	276
67060cb1 OH	277	extern struct pci_controller *pci_find_controller_for_domain(int domain_nr);
67060cb1 OH	278
5531e41b	279	/* Fill up host controller resources from the OF node */
7cd1de6b SR	280	extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
7cd1de6b SR	281	struct device_node *dev, int primary);
5531e41b	282
5131d4d8	283	/* Allocate & free a PCI host bridge structure */
7cd1de6b	284	extern struct pci_controller pcibios_alloc_controller(struct device_node dev);
5131d4d8	285	extern void pcibios_free_controller(struct pci_controller *phb);
2dd9c11b	286	extern void pcibios_free_controller_deferred(struct pci_host_bridge *bridge);
5131d4d8	287
5531e41b	288	#ifdef CONFIG_PCI
6dfbde20	289	extern int pcibios_vaddr_is_ioport(void __iomem *address);
5531e41b	290	#else
6dfbde20 BH	291	static inline int pcibios_vaddr_is_ioport(void __iomem *address)
	292	{
	293	return 0;
	294	}
7cd1de6b	295	#endif /* CONFIG_PCI */
5531e41b	296
7cd1de6b SR	297	#endif /* __KERNEL__ */
7cd1de6b SR	298	#endif /* _ASM_POWERPC_PCI_BRIDGE_H */