[linux-2.6-block.git] / arch / powerpc / include / asm / pci-bridge.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef _ASM_POWERPC_PCI_BRIDGE_H
#define _ASM_POWERPC_PCI_BRIDGE_H
#ifdef __KERNEL__
/*
 */
#include <linux/pci.h>
#include <linux/list.h>
#include <linux/ioport.h>
#include <linux/numa.h>
#include <linux/iommu.h>

struct device_node;

/*
 * PCI controller operations
 */
struct pci_controller_ops {
	void		(*dma_dev_setup)(struct pci_dev *pdev);
	void		(*dma_bus_setup)(struct pci_bus *bus);
	bool		(*iommu_bypass_supported)(struct pci_dev *pdev,
				u64 mask);

	int		(*probe_mode)(struct pci_bus *bus);

	/* Called when pci_enable_device() is called. Returns true to
	 * allow assignment/enabling of the device. */
	bool		(*enable_device_hook)(struct pci_dev *pdev);

	void		(*disable_device)(struct pci_dev *pdev);

	void		(*release_device)(struct pci_dev *pdev);

	/* Called during PCI resource reassignment */
	resource_size_t (*window_alignment)(struct pci_bus *bus,
					    unsigned long type);
	void		(*setup_bridge)(struct pci_bus *bus,
					unsigned long type);
	void		(*reset_secondary_bus)(struct pci_dev *pdev);

#ifdef CONFIG_PCI_MSI
	int		(*setup_msi_irqs)(struct pci_dev *pdev,
					  int nvec, int type);
	void		(*teardown_msi_irqs)(struct pci_dev *pdev);
#endif

	void		(*shutdown)(struct pci_controller *hose);

	struct iommu_group *(*device_group)(struct pci_controller *hose,
					    struct pci_dev *pdev);
};

/*
 * Structure of a PCI controller (host bridge)
 */
struct pci_controller {
	struct pci_bus *bus;
	char is_dynamic;
#ifdef CONFIG_PPC64
	int node;
#endif
	struct device_node *dn;
	struct list_head list_node;
	struct device *parent;

	int first_busno;
	int last_busno;
	int self_busno;
	struct resource busn;

	void __iomem *io_base_virt;
#ifdef CONFIG_PPC64
	void __iomem *io_base_alloc;
#endif
	resource_size_t io_base_phys;
	resource_size_t pci_io_size;

	/* Some machines have a special region to forward the ISA
	 * "memory" cycles such as VGA memory regions. Left to 0
	 * if unsupported
	 */
	resource_size_t	isa_mem_phys;
	resource_size_t	isa_mem_size;

	struct pci_controller_ops controller_ops;
	struct pci_ops *ops;
	unsigned int __iomem *cfg_addr;
	void __iomem *cfg_data;

	/*
	 * Used for variants of PCI indirect handling and possible quirks:
	 *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
	 *  EXT_REG - provides access to PCI-e extended registers
	 *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
	 *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
	 *   to determine which bus number to match on when generating type0
	 *   config cycles
	 *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
	 *   hanging if we don't have link and try to do config cycles to
	 *   anything but the PHB.  Only allow talking to the PHB if this is
	 *   set.
	 *  BIG_ENDIAN - cfg_addr is a big endian register
	 *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
	 *   the PLB4.  Effectively disable MRM commands by setting this.
	 *  FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
	 *   link status is in a RC PCIe cfg register (vs being a SoC register)
	 */
#define PPC_INDIRECT_TYPE_SET_CFG_TYPE		0x00000001
#define PPC_INDIRECT_TYPE_EXT_REG		0x00000002
#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS	0x00000004
#define PPC_INDIRECT_TYPE_NO_PCIE_LINK		0x00000008
#define PPC_INDIRECT_TYPE_BIG_ENDIAN		0x00000010
#define PPC_INDIRECT_TYPE_BROKEN_MRM		0x00000020
#define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK	0x00000040
	u32 indirect_type;
	/* Currently, we limit ourselves to 1 IO range and 3 mem
	 * ranges since the common pci_bus structure can't handle more
	 */
	struct resource	io_resource;
	struct resource mem_resources[3];
	resource_size_t mem_offset[3];
	int global_number;		/* PCI domain number */

	resource_size_t dma_window_base_cur;
	resource_size_t dma_window_size;

#ifdef CONFIG_PPC64
	unsigned long buid;
	struct pci_dn *pci_data;
#endif	/* CONFIG_PPC64 */

	void *private_data;

	/* IRQ domain hierarchy */
	struct irq_domain	*dev_domain;
	struct irq_domain	*msi_domain;
	struct fwnode_handle	*fwnode;

	/* iommu_ops support */
	struct iommu_device	iommu;
};

/* These are used for config access before all the PCI probing
   has been done. */
extern int early_read_config_byte(struct pci_controller *hose, int bus,
			int dev_fn, int where, u8 *val);
extern int early_read_config_word(struct pci_controller *hose, int bus,
			int dev_fn, int where, u16 *val);
extern int early_read_config_dword(struct pci_controller *hose, int bus,
			int dev_fn, int where, u32 *val);
extern int early_write_config_byte(struct pci_controller *hose, int bus,
			int dev_fn, int where, u8 val);
extern int early_write_config_word(struct pci_controller *hose, int bus,
			int dev_fn, int where, u16 val);
extern int early_write_config_dword(struct pci_controller *hose, int bus,
			int dev_fn, int where, u32 val);

extern int early_find_capability(struct pci_controller *hose, int bus,
				 int dev_fn, int cap);

extern void setup_indirect_pci(struct pci_controller* hose,
			       resource_size_t cfg_addr,
			       resource_size_t cfg_data, u32 flags);

extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
				int offset, int len, u32 *val);

extern int __indirect_read_config(struct pci_controller *hose,
				  unsigned char bus_number, unsigned int devfn,
				  int offset, int len, u32 *val);

extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
				 int offset, int len, u32 val);

static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
{
	return bus->sysdata;
}

#ifdef CONFIG_PPC_PMAC
extern int pci_device_from_OF_node(struct device_node *node,
				   u8 *bus, u8 *devfn);
#endif
#ifndef CONFIG_PPC64

#ifdef CONFIG_PPC_PCI_OF_BUS_MAP
extern void pci_create_OF_bus_map(void);
#else
static inline void pci_create_OF_bus_map(void) {}
#endif

#else	/* CONFIG_PPC64 */

/*
 * PCI stuff, for nodes representing PCI devices, pointed to
 * by device_node->data.
 */
struct iommu_table;

struct pci_dn {
	int     flags;
#define PCI_DN_FLAG_IOV_VF	0x01
#define PCI_DN_FLAG_DEAD	0x02    /* Device has been hot-removed */

	int	busno;			/* pci bus number */
	int	devfn;			/* pci device and function number */
	int	vendor_id;		/* Vendor ID */
	int	device_id;		/* Device ID */
	int	class_code;		/* Device class code */

	struct  pci_dn *parent;
	struct  pci_controller *phb;	/* for pci devices */
	struct	iommu_table_group *table_group;	/* for phb's or bridges */

	int	pci_ext_config_space;	/* for pci devices */
#ifdef CONFIG_EEH
	struct eeh_dev *edev;		/* eeh device */
#endif
#define IODA_INVALID_PE		0xFFFFFFFF
	unsigned int pe_number;
#ifdef CONFIG_PCI_IOV
	u16     vfs_expanded;		/* number of VFs IOV BAR expanded */
	u16     num_vfs;		/* number of VFs enabled*/
	unsigned int *pe_num_map;	/* PE# for the first VF PE or array */
	bool    m64_single_mode;	/* Use M64 BAR in Single Mode */
#define IODA_INVALID_M64        (-1)
	int     (*m64_map)[PCI_SRIOV_NUM_BARS];	/* Only used on powernv */
	int     last_allow_rc;			/* Only used on pseries */
#endif /* CONFIG_PCI_IOV */
	int	mps;			/* Maximum Payload Size */
	struct list_head child_list;
	struct list_head list;
	struct resource holes[PCI_SRIOV_NUM_BARS];
};

/* Get the pointer to a device_node's pci_dn */
#define PCI_DN(dn)	((struct pci_dn *) (dn)->data)

extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
					   int devfn);
extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
extern struct pci_dn *pci_add_device_node_info(struct pci_controller *hose,
					       struct device_node *dn);
extern void pci_remove_device_node_info(struct device_node *dn);

#ifdef CONFIG_PCI_IOV
struct pci_dn *add_sriov_vf_pdns(struct pci_dev *pdev);
void remove_sriov_vf_pdns(struct pci_dev *pdev);
#endif

#if defined(CONFIG_EEH)
static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn)
{
	return pdn ? pdn->edev : NULL;
}
#else
#define pdn_to_eeh_dev(x)	(NULL)
#endif

/** Find the bus corresponding to the indicated device node */
extern struct pci_bus *pci_find_bus_by_node(struct device_node *dn);

/** Remove all of the PCI devices under this bus */
extern void pci_hp_remove_devices(struct pci_bus *bus);

/** Discover new pci devices under this bus, and add them */
extern void pci_hp_add_devices(struct pci_bus *bus);

extern int pcibios_unmap_io_space(struct pci_bus *bus);
extern int pcibios_map_io_space(struct pci_bus *bus);

#ifdef CONFIG_NUMA
#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = (NODE))
#else
#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = NUMA_NO_NODE)
#endif

#endif	/* CONFIG_PPC64 */

/* Get the PCI host controller for an OF device */
extern struct pci_controller *pci_find_hose_for_OF_device(
			struct device_node* node);

extern struct pci_controller *pci_find_controller_for_domain(int domain_nr);

/* Fill up host controller resources from the OF node */
extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
			struct device_node *dev, int primary);

/* Allocate & free a PCI host bridge structure */
extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
extern void pcibios_free_controller(struct pci_controller *phb);
extern void pcibios_free_controller_deferred(struct pci_host_bridge *bridge);

#ifdef CONFIG_PCI
extern int pcibios_vaddr_is_ioport(void __iomem *address);
#else
static inline int pcibios_vaddr_is_ioport(void __iomem *address)
{
	return 0;
}
#endif	/* CONFIG_PCI */

#endif	/* __KERNEL__ */
#endif	/* _ASM_POWERPC_PCI_BRIDGE_H */
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
047ea784 PM	2	#ifndef _ASM_POWERPC_PCI_BRIDGE_H
047ea784 PM	3	#define _ASM_POWERPC_PCI_BRIDGE_H
88ced031	4	#ifdef __KERNEL__
7cd1de6b	5	/*
7cd1de6b	6	*/
5531e41b	7	#include <linux/pci.h>
a4c9e328 KG	8	#include <linux/list.h>
a4c9e328 KG	9	#include <linux/ioport.h>
98fa15f3	10	#include <linux/numa.h>
a9409044	11	#include <linux/iommu.h>
a4c9e328	12
44ef3390 SR	13	struct device_node;
44ef3390 SR	14
e02def5b DA	15	/*
	16	* PCI controller operations
	17	*/
	18	struct pci_controller_ops {
062b26ba	19	void (dma_dev_setup)(struct pci_dev pdev);
b122c954	20	void (dma_bus_setup)(struct pci_bus bus);
8617a5c5 CH	21	bool (iommu_bypass_supported)(struct pci_dev pdev,
8617a5c5 CH	22	u64 mask);
ff9df8c8	23
062b26ba	24	int (probe_mode)(struct pci_bus bus);
b31e79f8 DA	25
	26	/* Called when pci_enable_device() is called. Returns true to
	27	* allow assignment/enabling of the device. */
062b26ba	28	bool (enable_device_hook)(struct pci_dev pdev);
542070ba	29
062b26ba	30	void (disable_device)(struct pci_dev pdev);
abeeed6d	31
062b26ba	32	void (release_device)(struct pci_dev pdev);
10e79630	33
542070ba	34	/* Called during PCI resource reassignment */
062b26ba GS	35	resource_size_t (window_alignment)(struct pci_bus bus,
062b26ba GS	36	unsigned long type);
c5fcb29a GS	37	void (setup_bridge)(struct pci_bus bus,
c5fcb29a GS	38	unsigned long type);
062b26ba	39	void (reset_secondary_bus)(struct pci_dev pdev);
e059b105 DA	40
e059b105 DA	41	#ifdef CONFIG_PCI_MSI
062b26ba	42	int (setup_msi_irqs)(struct pci_dev pdev,
e059b105	43	int nvec, int type);
062b26ba	44	void (teardown_msi_irqs)(struct pci_dev pdev);
e059b105	45	#endif
3405c257	46
062b26ba	47	void (shutdown)(struct pci_controller hose);
a9409044 AK	48
	49	struct iommu_group (device_group)(struct pci_controller *hose,
	50	struct pci_dev *pdev);
e02def5b DA	51	};
e02def5b DA	52
5531e41b KG	53	/*
	54	* Structure of a PCI controller (host bridge)
	55	*/
	56	struct pci_controller {
	57	struct pci_bus *bus;
a4c9e328	58	char is_dynamic;
7211991f SR	59	#ifdef CONFIG_PPC64
	60	int node;
	61	#endif
44ef3390	62	struct device_node *dn;
a4c9e328	63	struct list_head list_node;
5531e41b KG	64	struct device *parent;
	65
	66	int first_busno;
	67	int last_busno;
	68	int self_busno;
be8e60d8	69	struct resource busn;
5531e41b KG	70
5531e41b KG	71	void __iomem *io_base_virt;
7211991f	72	#ifdef CONFIG_PPC64
b274014c	73	void __iomem *io_base_alloc;
7211991f	74	#endif
5531e41b	75	resource_size_t io_base_phys;
13dccb9e	76	resource_size_t pci_io_size;
5531e41b	77
e9f82cb7 BH	78	/* Some machines have a special region to forward the ISA
	79	* "memory" cycles such as VGA memory regions. Left to 0
	80	* if unsupported
	81	*/
	82	resource_size_t isa_mem_phys;
	83	resource_size_t isa_mem_size;
	84
e02def5b	85	struct pci_controller_ops controller_ops;
5531e41b	86	struct pci_ops *ops;
70fbb938 SR	87	unsigned int __iomem *cfg_addr;
70fbb938 SR	88	void __iomem *cfg_data;
5531e41b KG	89
	90	/*
	91	* Used for variants of PCI indirect handling and possible quirks:
	92	* SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
	93	* EXT_REG - provides access to PCI-e extended registers
25985edc	94	* SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
5531e41b KG	95	* on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
	96	* to determine which bus number to match on when generating type0
	97	* config cycles
62c66c8e KG	98	* NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
	99	* hanging if we don't have link and try to do config cycles to
	100	* anything but the PHB. Only allow talking to the PHB if this is
	101	* set.
2e56ff20	102	* BIG_ENDIAN - cfg_addr is a big endian register
5ce4b596 JB	103	* BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
5ce4b596 JB	104	* the PLB4. Effectively disable MRM commands by setting this.
34642bbb KG	105	* FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
34642bbb KG	106	* link status is in a RC PCIe cfg register (vs being a SoC register)
5531e41b	107	*/
7cd1de6b SR	108	#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
	109	#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
	110	#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
	111	#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
	112	#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
5ce4b596	113	#define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
34642bbb	114	#define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040
5531e41b	115	u32 indirect_type;
5531e41b KG	116	/* Currently, we limit ourselves to 1 IO range and 3 mem
	117	* ranges since the common pci_bus structure can't handle more
	118	*/
	119	struct resource io_resource;
	120	struct resource mem_resources[3];
3fd47f06	121	resource_size_t mem_offset[3];
5516b540	122	int global_number; /* PCI domain number */
89d93347 BB	123
	124	resource_size_t dma_window_base_cur;
	125	resource_size_t dma_window_size;
	126
7211991f SR	127	#ifdef CONFIG_PPC64
7211991f SR	128	unsigned long buid;
cca87d30	129	struct pci_dn *pci_data;
34642bbb	130	#endif /* CONFIG_PPC64 */
7211991f SR	131
7211991f SR	132	void *private_data;
a5f3d2c1 CLG	133
	134	/* IRQ domain hierarchy */
	135	struct irq_domain *dev_domain;
	136	struct irq_domain *msi_domain;
	137	struct fwnode_handle *fwnode;
a9409044 AK	138
	139	/* iommu_ops support */
	140	struct iommu_device iommu;
5531e41b KG	141	};
5531e41b KG	142
5531e41b KG	143	/* These are used for config access before all the PCI probing
5531e41b KG	144	has been done. */
7cd1de6b SR	145	extern int early_read_config_byte(struct pci_controller *hose, int bus,
	146	int dev_fn, int where, u8 *val);
	147	extern int early_read_config_word(struct pci_controller *hose, int bus,
	148	int dev_fn, int where, u16 *val);
	149	extern int early_read_config_dword(struct pci_controller *hose, int bus,
	150	int dev_fn, int where, u32 *val);
	151	extern int early_write_config_byte(struct pci_controller *hose, int bus,
	152	int dev_fn, int where, u8 val);
	153	extern int early_write_config_word(struct pci_controller *hose, int bus,
	154	int dev_fn, int where, u16 val);
	155	extern int early_write_config_dword(struct pci_controller *hose, int bus,
	156	int dev_fn, int where, u32 val);
5531e41b	157
38805e5f KG	158	extern int early_find_capability(struct pci_controller *hose, int bus,
	159	int dev_fn, int cap);
	160
5531e41b	161	extern void setup_indirect_pci(struct pci_controller* hose,
d94bad82 VB	162	resource_size_t cfg_addr,
d94bad82 VB	163	resource_size_t cfg_data, u32 flags);
89c2dd62	164
50d8f87d RI	165	extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
	166	int offset, int len, u32 *val);
	167
6d5f6a0e KP	168	extern int __indirect_read_config(struct pci_controller *hose,
	169	unsigned char bus_number, unsigned int devfn,
	170	int offset, int len, u32 *val);
	171
50d8f87d RI	172	extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
	173	int offset, int len, u32 val);
	174
89c2dd62 KG	175	static inline struct pci_controller pci_bus_to_host(const struct pci_bus bus)
	176	{
	177	return bus->sysdata;
	178	}
	179
a2954a7e	180	#ifdef CONFIG_PPC_PMAC
98d9f30c BH	181	extern int pci_device_from_OF_node(struct device_node *node,
98d9f30c BH	182	u8 bus, u8 devfn);
a2954a7e	183	#endif
0aa297e7 CL	184	#ifndef CONFIG_PPC64
0aa297e7 CL	185
5d2eb73a	186	#ifdef CONFIG_PPC_PCI_OF_BUS_MAP
98d9f30c	187	extern void pci_create_OF_bus_map(void);
5d2eb73a PR	188	#else
5d2eb73a PR	189	static inline void pci_create_OF_bus_map(void) {}
70454458	190	#endif
98d9f30c	191
7cd1de6b	192	#else /* CONFIG_PPC64 */
1da177e4	193
1635317f PM	194	/*
	195	* PCI stuff, for nodes representing PCI devices, pointed to
	196	* by device_node->data.
	197	*/
1635317f PM	198	struct iommu_table;
	199
	200	struct pci_dn {
cca87d30	201	int flags;
a8b2f828	202	#define PCI_DN_FLAG_IOV_VF 0x01
5ef753ae	203	#define PCI_DN_FLAG_DEAD 0x02 /* Device has been hot-removed */
cca87d30	204
7684b40c	205	int busno; /* pci bus number */
7684b40c	206	int devfn; /* pci device and function number */
c035ff1d GS	207	int vendor_id; /* Vendor ID */
	208	int device_id; /* Device ID */
	209	int class_code; /* Device class code */
b5166cc2	210
cca87d30	211	struct pci_dn *parent;
c2e221e8	212	struct pci_controller phb; / for pci devices */
b348aa65	213	struct iommu_table_group table_group; / for phb's or bridges */
c2e221e8 LV	214
c2e221e8 LV	215	int pci_ext_config_space; /* for pci devices */
184cd4a3	216	#ifdef CONFIG_EEH
2a0352fa	217	struct eeh_dev edev; / eeh device */
c2e221e8	218	#endif
689ee8c9	219	#define IODA_INVALID_PE 0xFFFFFFFF
689ee8c9	220	unsigned int pe_number;
6e628c7d WY	221	#ifdef CONFIG_PCI_IOV
6e628c7d WY	222	u16 vfs_expanded; /* number of VFs IOV BAR expanded */
781a868f	223	u16 num_vfs; /* number of VFs enabled*/
689ee8c9	224	unsigned int pe_num_map; / PE# for the first VF PE or array */
ee8222fe	225	bool m64_single_mode; /* Use M64 BAR in Single Mode */
781a868f	226	#define IODA_INVALID_M64 (-1)
565a744d BL	227	int (m64_map)[PCI_SRIOV_NUM_BARS]; / Only used on powernv */
565a744d BL	228	int last_allow_rc; /* Only used on pseries */
6e628c7d	229	#endif /* CONFIG_PCI_IOV */
0dc2830e	230	int mps; /* Maximum Payload Size */
cca87d30 GS	231	struct list_head child_list;
cca87d30 GS	232	struct list_head list;
d6f934fd	233	struct resource holes[PCI_SRIOV_NUM_BARS];
1635317f PM	234	};
	235
	236	/* Get the pointer to a device_node's pci_dn */
	237	#define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
	238
cca87d30 GS	239	extern struct pci_dn pci_get_pdn_by_devfn(struct pci_bus bus,
cca87d30 GS	240	int devfn);
b72c1f65	241	extern struct pci_dn pci_get_pdn(struct pci_dev pdev);
d8f66f41 GS	242	extern struct pci_dn pci_add_device_node_info(struct pci_controller hose,
d8f66f41 GS	243	struct device_node *dn);
de5a28ac	244	extern void pci_remove_device_node_info(struct device_node *dn);
1da177e4	245
8cd6aacc OH	246	#ifdef CONFIG_PCI_IOV
	247	struct pci_dn add_sriov_vf_pdns(struct pci_dev pdev);
	248	void remove_sriov_vf_pdns(struct pci_dev *pdev);
	249	#endif
	250
2a0352fa	251	#if defined(CONFIG_EEH)
e8e9b34c GS	252	static inline struct eeh_dev pdn_to_eeh_dev(struct pci_dn pdn)
	253	{
	254	return pdn ? pdn->edev : NULL;
	255	}
f8f7d63f	256	#else
e8e9b34c	257	#define pdn_to_eeh_dev(x) (NULL)
2a0352fa GS	258	#endif
2a0352fa GS	259
2bf6a8fa	260	/** Find the bus corresponding to the indicated device node */
3773dd25	261	extern struct pci_bus pci_find_bus_by_node(struct device_node dn);
2bf6a8fa	262
2bf6a8fa	263	/** Remove all of the PCI devices under this bus */
bd251b89	264	extern void pci_hp_remove_devices(struct pci_bus *bus);
2bf6a8fa LV	265
2bf6a8fa LV	266	/** Discover new pci devices under this bus, and add them */
bd251b89	267	extern void pci_hp_add_devices(struct pci_bus *bus);
1da177e4	268
3d5134ee BH	269	extern int pcibios_unmap_io_space(struct pci_bus *bus);
	270	extern int pcibios_map_io_space(struct pci_bus *bus);
	271
357518fa AB	272	#ifdef CONFIG_NUMA
	273	#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
	274	#else
98fa15f3	275	#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = NUMA_NO_NODE)
357518fa AB	276	#endif
357518fa AB	277
7cd1de6b	278	#endif /* CONFIG_PPC64 */
5531e41b KG	279
5531e41b KG	280	/* Get the PCI host controller for an OF device */
7cd1de6b SR	281	extern struct pci_controller *pci_find_hose_for_OF_device(
7cd1de6b SR	282	struct device_node* node);
5531e41b	283
67060cb1 OH	284	extern struct pci_controller *pci_find_controller_for_domain(int domain_nr);
67060cb1 OH	285
5531e41b	286	/* Fill up host controller resources from the OF node */
7cd1de6b SR	287	extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
7cd1de6b SR	288	struct device_node *dev, int primary);
5531e41b	289
5131d4d8	290	/* Allocate & free a PCI host bridge structure */
7cd1de6b	291	extern struct pci_controller pcibios_alloc_controller(struct device_node dev);
5131d4d8	292	extern void pcibios_free_controller(struct pci_controller *phb);
2dd9c11b	293	extern void pcibios_free_controller_deferred(struct pci_host_bridge *bridge);
5131d4d8	294
5531e41b	295	#ifdef CONFIG_PCI
6dfbde20	296	extern int pcibios_vaddr_is_ioport(void __iomem *address);
5531e41b	297	#else
6dfbde20 BH	298	static inline int pcibios_vaddr_is_ioport(void __iomem *address)
	299	{
	300	return 0;
	301	}
7cd1de6b	302	#endif /* CONFIG_PCI */
5531e41b	303
7cd1de6b SR	304	#endif /* __KERNEL__ */
7cd1de6b SR	305	#endif /* _ASM_POWERPC_PCI_BRIDGE_H */