[linux-2.6-block.git] / arch / powerpc / include / asm / paca.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * This control block defines the PACA which defines the processor
 * specific data for each logical processor on the system.
 * There are some pointers defined that are utilized by PLIC.
 *
 * C 2001 PPC 64 Team, IBM Corp
 */
#ifndef _ASM_POWERPC_PACA_H
#define _ASM_POWERPC_PACA_H
#ifdef __KERNEL__

#ifdef CONFIG_PPC64

#include <linux/cache.h>
#include <linux/string.h>
#include <asm/types.h>
#include <asm/lppaca.h>
#include <asm/mmu.h>
#include <asm/page.h>
#ifdef CONFIG_PPC_BOOK3E_64
#include <asm/exception-64e.h>
#else
#include <asm/exception-64s.h>
#endif
#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
#include <asm/kvm_book3s_asm.h>
#endif
#include <asm/accounting.h>
#include <asm/hmi.h>
#include <asm/cpuidle.h>
#include <asm/atomic.h>
#include <asm/mce.h>

#include <asm-generic/mmiowb_types.h>

register struct paca_struct *local_paca asm("r13");

#if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP)
extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */
/*
 * Add standard checks that preemption cannot occur when using get_paca():
 * otherwise the paca_struct it points to may be the wrong one just after.
 */
#define get_paca()	((void) debug_smp_processor_id(), local_paca)
#else
#define get_paca()	local_paca
#endif

#ifdef CONFIG_PPC_PSERIES
#define get_lppaca()	(get_paca()->lppaca_ptr)
#endif

#define get_slb_shadow()	(get_paca()->slb_shadow_ptr)

struct task_struct;
struct rtas_args;

/*
 * Defines the layout of the paca.
 *
 * This structure is not directly accessed by firmware or the service
 * processor.
 */
struct paca_struct {
#ifdef CONFIG_PPC_PSERIES
	/*
	 * Because hw_cpu_id, unlike other paca fields, is accessed
	 * routinely from other CPUs (from the IRQ code), we stick to
	 * read-only (after boot) fields in the first cacheline to
	 * avoid cacheline bouncing.
	 */

	struct lppaca *lppaca_ptr;	/* Pointer to LpPaca for PLIC */
#endif /* CONFIG_PPC_PSERIES */

	/*
	 * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c 
	 * load lock_token and paca_index with a single lwz
	 * instruction.  They must travel together and be properly
	 * aligned.
	 */
#ifdef __BIG_ENDIAN__
	u16 lock_token;			/* Constant 0x8000, used in locks */
	u16 paca_index;			/* Logical processor number */
#else
	u16 paca_index;			/* Logical processor number */
	u16 lock_token;			/* Constant 0x8000, used in locks */
#endif

	u64 kernel_toc;			/* Kernel TOC address */
	u64 kernelbase;			/* Base address of kernel */
	u64 kernel_msr;			/* MSR while running in kernel */
	void *emergency_sp;		/* pointer to emergency stack */
	u64 data_offset;		/* per cpu data offset */
	s16 hw_cpu_id;			/* Physical processor number */
	u8 cpu_start;			/* At startup, processor spins until */
					/* this becomes non-zero. */
	u8 kexec_state;		/* set when kexec down has irqs off */
#ifdef CONFIG_PPC_BOOK3S_64
#ifdef CONFIG_PPC_64S_HASH_MMU
	struct slb_shadow *slb_shadow_ptr;
#endif
	struct dtl_entry *dispatch_log;
	struct dtl_entry *dispatch_log_end;
#endif
	u64 dscr_default;		/* per-CPU default DSCR */

#ifdef CONFIG_PPC_BOOK3S_64
	/*
	 * Now, starting in cacheline 2, the exception save areas
	 */
	/* used for most interrupts/exceptions */
	u64 exgen[EX_SIZE] __attribute__((aligned(0x80)));

#ifdef CONFIG_PPC_64S_HASH_MMU
	/* SLB related definitions */
	u16 vmalloc_sllp;
	u8 slb_cache_ptr;
	u8 stab_rr;			/* stab/slb round-robin counter */
#ifdef CONFIG_DEBUG_VM
	u8 in_kernel_slb_handler;
#endif
	u32 slb_used_bitmap;		/* Bitmaps for first 32 SLB entries. */
	u32 slb_kern_bitmap;
	u32 slb_cache[SLB_CACHE_ENTRIES];
#endif
#endif /* CONFIG_PPC_BOOK3S_64 */

#ifdef CONFIG_PPC_BOOK3E_64
	u64 exgen[8] __aligned(0x40);
	/* Keep pgd in the same cacheline as the start of extlb */
	pgd_t *pgd __aligned(0x40); /* Current PGD */
	pgd_t *kernel_pgd;		/* Kernel PGD */

	/* Shared by all threads of a core -- points to tcd of first thread */
	struct tlb_core_data *tcd_ptr;

	/*
	 * We can have up to 3 levels of reentrancy in the TLB miss handler,
	 * in each of four exception levels (normal, crit, mcheck, debug).
	 */
	u64 extlb[12][EX_TLB_SIZE / sizeof(u64)];
	u64 exmc[8];		/* used for machine checks */
	u64 excrit[8];		/* used for crit interrupts */
	u64 exdbg[8];		/* used for debug interrupts */

	/* Kernel stack pointers for use by special exceptions */
	void *mc_kstack;
	void *crit_kstack;
	void *dbg_kstack;

	struct tlb_core_data tcd;
#endif /* CONFIG_PPC_BOOK3E_64 */

#ifdef CONFIG_PPC_64S_HASH_MMU
	unsigned char mm_ctx_low_slices_psize[BITS_PER_LONG / BITS_PER_BYTE];
	unsigned char mm_ctx_high_slices_psize[SLICE_ARRAY_SIZE];
#endif

	/*
	 * then miscellaneous read-write fields
	 */
	struct task_struct *__current;	/* Pointer to current */
	u64 kstack;			/* Saved Kernel stack addr */
	u64 saved_r1;			/* r1 save for RTAS calls or PM or EE=0 */
	u64 saved_msr;			/* MSR saved here by enter_rtas */
#ifdef CONFIG_PPC64
	u64 exit_save_r1;		/* Syscall/interrupt R1 save */
#endif
#ifdef CONFIG_PPC_BOOK3E_64
	u16 trap_save;			/* Used when bad stack is encountered */
#endif
#ifdef CONFIG_PPC_BOOK3S_64
	u8 hsrr_valid;			/* HSRRs set for HRFID */
	u8 srr_valid;			/* SRRs set for RFID */
#endif
	u8 irq_soft_mask;		/* mask for irq soft masking */
	u8 irq_happened;		/* irq happened while soft-disabled */
	u8 irq_work_pending;		/* IRQ_WORK interrupt while soft-disable */
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
	u8 pmcregs_in_use;		/* pseries puts this in lppaca */
#endif
	u64 sprg_vdso;			/* Saved user-visible sprg */
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
	u64 tm_scratch;                 /* TM scratch area for reclaim */
#endif

#ifdef CONFIG_PPC_POWERNV
	/* PowerNV idle fields */
	/* PNV_CORE_IDLE_* bits, all siblings work on thread 0 paca */
	unsigned long idle_state;
	union {
		/* P7/P8 specific fields */
		struct {
			/* PNV_THREAD_RUNNING/NAP/SLEEP	*/
			u8 thread_idle_state;
			/* Mask to denote subcore sibling threads */
			u8 subcore_sibling_mask;
		};

		/* P9 specific fields */
		struct {
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
			/* The PSSCR value that the kernel requested before going to stop */
			u64 requested_psscr;
			/* Flag to request this thread not to stop */
			atomic_t dont_stop;
#endif
		};
	};
#endif

#ifdef CONFIG_PPC_BOOK3S_64
	/* Non-maskable exceptions that are not performance critical */
	u64 exnmi[EX_SIZE];	/* used for system reset (nmi) */
	u64 exmc[EX_SIZE];	/* used for machine checks */
#endif
#ifdef CONFIG_PPC_BOOK3S_64
	/* Exclusive stacks for system reset and machine check exception. */
	void *nmi_emergency_sp;
	void *mc_emergency_sp;

	u16 in_nmi;			/* In nmi handler */

	/*
	 * Flag to check whether we are in machine check early handler
	 * and already using emergency stack.
	 */
	u16 in_mce;
	u8 hmi_event_available;		/* HMI event is available */
	u8 hmi_p9_special_emu;		/* HMI P9 special emulation */
	u32 hmi_irqs;			/* HMI irq stat */
#endif
	u8 ftrace_enabled;		/* Hard disable ftrace */

	/* Stuff for accurate time accounting */
	struct cpu_accounting_data accounting;
	u64 dtl_ridx;			/* read index in dispatch log */
	struct dtl_entry *dtl_curr;	/* pointer corresponding to dtl_ridx */

#ifdef CONFIG_KVM_BOOK3S_HANDLER
#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
	/* We use this to store guest state in */
	struct kvmppc_book3s_shadow_vcpu shadow_vcpu;
#endif
	struct kvmppc_host_state kvm_hstate;
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
	/*
	 * Bitmap for sibling subcore status. See kvm/book3s_hv_ras.c for
	 * more details
	 */
	struct sibling_subcore_state *sibling_subcore_state;
#endif
#endif
#ifdef CONFIG_PPC_BOOK3S_64
	/*
	 * rfi fallback flush must be in its own cacheline to prevent
	 * other paca data leaking into the L1d
	 */
	u64 exrfi[EX_SIZE] __aligned(0x80);
	void *rfi_flush_fallback_area;
	u64 l1d_flush_size;
#endif
#ifdef CONFIG_PPC_PSERIES
	u8 *mce_data_buf;		/* buffer to hold per cpu rtas errlog */
#endif /* CONFIG_PPC_PSERIES */

#ifdef CONFIG_PPC_BOOK3S_64
#ifdef CONFIG_PPC_64S_HASH_MMU
	/* Capture SLB related old contents in MCE handler. */
	struct slb_entry *mce_faulty_slbs;
	u16 slb_save_cache_ptr;
#endif
#endif /* CONFIG_PPC_BOOK3S_64 */
#ifdef CONFIG_STACKPROTECTOR
	unsigned long canary;
#endif
#ifdef CONFIG_MMIOWB
	struct mmiowb_state mmiowb_state;
#endif
#ifdef CONFIG_PPC_BOOK3S_64
	struct mce_info *mce_info;
	u8 mce_pending_irq_work;
#endif /* CONFIG_PPC_BOOK3S_64 */
} ____cacheline_aligned;

extern void copy_mm_to_paca(struct mm_struct *mm);
extern struct paca_struct **paca_ptrs;
extern void initialise_paca(struct paca_struct *new_paca, int cpu);
extern void setup_paca(struct paca_struct *new_paca);
extern void allocate_paca_ptrs(void);
extern void allocate_paca(int cpu);
extern void free_unused_pacas(void);

#else /* CONFIG_PPC64 */

static inline void allocate_paca_ptrs(void) { }
static inline void allocate_paca(int cpu) { }
static inline void free_unused_pacas(void) { }

#endif /* CONFIG_PPC64 */

#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_PACA_H */
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
1da177e4	2	/*
8882a4da DG	3	* This control block defines the PACA which defines the processor
8882a4da DG	4	* specific data for each logical processor on the system.
1da177e4 LT	5	* There are some pointers defined that are utilized by PLIC.
	6	*
	7	* C 2001 PPC 64 Team, IBM Corp
8882a4da DG	8	*/
	9	#ifndef _ASM_POWERPC_PACA_H
	10	#define _ASM_POWERPC_PACA_H
88ced031	11	#ifdef __KERNEL__
1da177e4	12
1426d5a3 ME	13	#ifdef CONFIG_PPC64
1426d5a3 ME	14
dcf280e6	15	#include <linux/cache.h>
2fc251a8	16	#include <linux/string.h>
dce6670a BH	17	#include <asm/types.h>
	18	#include <asm/lppaca.h>
	19	#include <asm/mmu.h>
	20	#include <asm/page.h>
e0d68273	21	#ifdef CONFIG_PPC_BOOK3E_64
dce6670a	22	#include <asm/exception-64e.h>
8c388514 NP	23	#else
	24	#include <asm/exception-64s.h>
	25	#endif
7e57cba0	26	#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
2191d657	27	#include <asm/kvm_book3s_asm.h>
7e57cba0	28	#endif
c223c903	29	#include <asm/accounting.h>
fd7bacbc	30	#include <asm/hmi.h>
e1c1cfed	31	#include <asm/cpuidle.h>
7672691a	32	#include <asm/atomic.h>
923b3cf0	33	#include <asm/mce.h>
1da177e4	34
420af155 WD	35	#include <asm-generic/mmiowb_types.h>
420af155 WD	36
1da177e4	37	register struct paca_struct *local_paca asm("r13");
048c8bc9 HD	38
	39	#if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP)
	40	extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */
	41	/*
	42	* Add standard checks that preemption cannot occur when using get_paca():
	43	* otherwise the paca_struct it points to may be the wrong one just after.
	44	*/
	45	#define get_paca() ((void) debug_smp_processor_id(), local_paca)
	46	#else
1da177e4	47	#define get_paca() local_paca
048c8bc9 HD	48	#endif
048c8bc9 HD	49
8e0b634b	50	#ifdef CONFIG_PPC_PSERIES
3356bb9f	51	#define get_lppaca() (get_paca()->lppaca_ptr)
8e0b634b NP	52	#endif
8e0b634b NP	53
2f6093c8	54	#define get_slb_shadow() (get_paca()->slb_shadow_ptr)
1da177e4 LT	55
1da177e4 LT	56	struct task_struct;
d6bdceb6	57	struct rtas_args;
1da177e4 LT	58
	59	/*
	60	* Defines the layout of the paca.
	61	*
	62	* This structure is not directly accessed by firmware or the service
30ff2e87	63	* processor.
1da177e4 LT	64	*/
1da177e4 LT	65	struct paca_struct {
8e0b634b	66	#ifdef CONFIG_PPC_PSERIES
1da177e4 LT	67	/*
	68	* Because hw_cpu_id, unlike other paca fields, is accessed
	69	* routinely from other CPUs (from the IRQ code), we stick to
	70	* read-only (after boot) fields in the first cacheline to
	71	* avoid cacheline bouncing.
	72	*/
	73
1da177e4	74	struct lppaca lppaca_ptr; / Pointer to LpPaca for PLIC */
8e0b634b NP	75	#endif /* CONFIG_PPC_PSERIES */
8e0b634b NP	76
1da177e4	77	/*
2ef9481e	78	* MAGIC: the spinlock functions in arch/powerpc/lib/locks.c
1da177e4 LT	79	* load lock_token and paca_index with a single lwz
	80	* instruction. They must travel together and be properly
	81	* aligned.
	82	*/
54bb7f4b	83	#ifdef __BIG_ENDIAN__
1da177e4 LT	84	u16 lock_token; /* Constant 0x8000, used in locks */
1da177e4 LT	85	u16 paca_index; /* Logical processor number */
54bb7f4b AB	86	#else
	87	u16 paca_index; /* Logical processor number */
	88	u16 lock_token; /* Constant 0x8000, used in locks */
	89	#endif
1da177e4	90
1da177e4	91	u64 kernel_toc; /* Kernel TOC address */
1f6a93e4 PM	92	u64 kernelbase; /* Base address of kernel */
1f6a93e4 PM	93	u64 kernel_msr; /* MSR while running in kernel */
1da177e4	94	void emergency_sp; / pointer to emergency stack */
7a0268fa	95	u64 data_offset; /* per cpu data offset */
1da177e4 LT	96	s16 hw_cpu_id; /* Physical processor number */
	97	u8 cpu_start; /* At startup, processor spins until */
	98	/* this becomes non-zero. */
1fc711f7	99	u8 kexec_state; /* set when kexec down has irqs off */
4e003747	100	#ifdef CONFIG_PPC_BOOK3S_64
387e220a	101	#ifdef CONFIG_PPC_64S_HASH_MMU
e91948fd	102	struct slb_shadow *slb_shadow_ptr;
387e220a	103	#endif
cf9efce0 PM	104	struct dtl_entry *dispatch_log;
cf9efce0 PM	105	struct dtl_entry *dispatch_log_end;
4e003747	106	#endif
1739ea9e	107	u64 dscr_default; /* per-CPU default DSCR */
1da177e4	108
4e003747	109	#ifdef CONFIG_PPC_BOOK3S_64
1da177e4 LT	110	/*
	111	* Now, starting in cacheline 2, the exception save areas
	112	*/
3c726f8d	113	/* used for most interrupts/exceptions */
8c388514	114	u64 exgen[EX_SIZE] __attribute__((aligned(0x80)));
ac7c5e9b	115
387e220a	116	#ifdef CONFIG_PPC_64S_HASH_MMU
91c60b5b	117	/* SLB related definitions */
bf72aeba	118	u16 vmalloc_sllp;
126b11b2 NP	119	u8 slb_cache_ptr;
126b11b2 NP	120	u8 stab_rr; /* stab/slb round-robin counter */
e15a4fea NP	121	#ifdef CONFIG_DEBUG_VM
	122	u8 in_kernel_slb_handler;
	123	#endif
126b11b2 NP	124	u32 slb_used_bitmap; /* Bitmaps for first 32 SLB entries. */
126b11b2 NP	125	u32 slb_kern_bitmap;
735cafc3	126	u32 slb_cache[SLB_CACHE_ENTRIES];
387e220a	127	#endif
4e003747	128	#endif /* CONFIG_PPC_BOOK3S_64 */
91c60b5b	129
e0d68273	130	#ifdef CONFIG_PPC_BOOK3E_64
016f8cf0	131	u64 exgen[8] __aligned(0x40);
f67f4ef5	132	/* Keep pgd in the same cacheline as the start of extlb */
016f8cf0	133	pgd_t pgd __aligned(0x40); / Current PGD */
f67f4ef5	134	pgd_t kernel_pgd; / Kernel PGD */
28efc35f SW	135
	136	/* Shared by all threads of a core -- points to tcd of first thread */
	137	struct tlb_core_data *tcd_ptr;
	138
609af38f SW	139	/*
	140	* We can have up to 3 levels of reentrancy in the TLB miss handler,
	141	* in each of four exception levels (normal, crit, mcheck, debug).
	142	*/
	143	u64 extlb[12][EX_TLB_SIZE / sizeof(u64)];
dce6670a BH	144	u64 exmc[8]; /* used for machine checks */
	145	u64 excrit[8]; /* used for crit interrupts */
	146	u64 exdbg[8]; /* used for debug interrupts */
	147
	148	/* Kernel stack pointers for use by special exceptions */
	149	void *mc_kstack;
	150	void *crit_kstack;
	151	void *dbg_kstack;
28efc35f SW	152
28efc35f SW	153	struct tlb_core_data tcd;
e0d68273	154	#endif /* CONFIG_PPC_BOOK3E_64 */
dce6670a	155
387e220a	156	#ifdef CONFIG_PPC_64S_HASH_MMU
54be0b9c ME	157	unsigned char mm_ctx_low_slices_psize[BITS_PER_LONG / BITS_PER_BYTE];
54be0b9c ME	158	unsigned char mm_ctx_high_slices_psize[SLICE_ARRAY_SIZE];
54be0b9c ME	159	#endif
54be0b9c ME	160
1da177e4 LT	161	/*
	162	* then miscellaneous read-write fields
	163	*/
	164	struct task_struct __current; / Pointer to current */
	165	u64 kstack; /* Saved Kernel stack addr */
7b08729c	166	u64 saved_r1; /* r1 save for RTAS calls or PM or EE=0 */
1da177e4	167	u64 saved_msr; /* MSR saved here by enter_rtas */
13799748 NP	168	#ifdef CONFIG_PPC64
	169	u64 exit_save_r1; /* Syscall/interrupt R1 save */
	170	#endif
e0d68273	171	#ifdef CONFIG_PPC_BOOK3E_64
68730401	172	u16 trap_save; /* Used when bad stack is encountered */
59dc5bfc NP	173	#endif
	174	#ifdef CONFIG_PPC_BOOK3S_64
	175	u8 hsrr_valid; /* HSRRs set for HRFID */
	176	u8 srr_valid; /* SRRs set for RFID */
0a882e28	177	#endif
4e26bc4a	178	u8 irq_soft_mask; /* mask for irq soft masking */
7230c564	179	u8 irq_happened; /* irq happened while soft-disabled */
e360adbe	180	u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */
8e0b634b NP	181	#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
	182	u8 pmcregs_in_use; /* pseries puts this in lppaca */
	183	#endif
9d378dfa	184	u64 sprg_vdso; /* Saved user-visible sprg */
afc07701 MN	185	#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
	186	u64 tm_scratch; /* TM scratch area for reclaim */
	187	#endif
c6622f63	188
7cba160a	189	#ifdef CONFIG_PPC_POWERNV
10d91611 NP	190	/* PowerNV idle fields */
	191	/* PNV_CORE_IDLE_* bits, all siblings work on thread 0 paca */
	192	unsigned long idle_state;
	193	union {
	194	/* P7/P8 specific fields */
	195	struct {
	196	/* PNV_THREAD_RUNNING/NAP/SLEEP */
	197	u8 thread_idle_state;
	198	/* Mask to denote subcore sibling threads */
	199	u8 subcore_sibling_mask;
	200	};
	201
	202	/* P9 specific fields */
	203	struct {
	204	#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
	205	/* The PSSCR value that the kernel requested before going to stop */
	206	u64 requested_psscr;
	207	/* Flag to request this thread not to stop */
	208	atomic_t dont_stop;
	209	#endif
	210	};
	211	};
7cba160a SP	212	#endif
7cba160a SP	213
4e003747	214	#ifdef CONFIG_PPC_BOOK3S_64
a3d96f70	215	/* Non-maskable exceptions that are not performance critical */
8c388514 NP	216	u64 exnmi[EX_SIZE]; /* used for system reset (nmi) */
8c388514 NP	217	u64 exmc[EX_SIZE]; /* used for machine checks */
a3d96f70	218	#endif
729b0f71	219	#ifdef CONFIG_PPC_BOOK3S_64
b1ee8a3d NP	220	/* Exclusive stacks for system reset and machine check exception. */
b1ee8a3d NP	221	void *nmi_emergency_sp;
729b0f71	222	void *mc_emergency_sp;
c4f3b52c NP	223
	224	u16 in_nmi; /* In nmi handler */
	225
729b0f71 MS	226	/*
	227	* Flag to check whether we are in machine check early handler
	228	* and already using emergency stack.
	229	*/
	230	u16 in_mce;
c4f3b52c	231	u8 hmi_event_available; /* HMI event is available */
5080332c	232	u8 hmi_p9_special_emu; /* HMI P9 special emulation */
ada68a66	233	u32 hmi_irqs; /* HMI irq stat */
729b0f71	234	#endif
ea678ac6	235	u8 ftrace_enabled; /* Hard disable ftrace */
ed79ba9e	236
c6622f63	237	/* Stuff for accurate time accounting */
c223c903	238	struct cpu_accounting_data accounting;
cf9efce0 PM	239	u64 dtl_ridx; /* read index in dispatch log */
cf9efce0 PM	240	struct dtl_entry dtl_curr; / pointer corresponding to dtl_ridx */
4b7ae55d	241
c14dea04	242	#ifdef CONFIG_KVM_BOOK3S_HANDLER
7aa79938	243	#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
7e57cba0 AG	244	/* We use this to store guest state in */
7e57cba0 AG	245	struct kvmppc_book3s_shadow_vcpu shadow_vcpu;
de56a948	246	#endif
3c42bf8a	247	struct kvmppc_host_state kvm_hstate;
7c379526 PB	248	#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
	249	/*
	250	* Bitmap for sibling subcore status. See kvm/book3s_hv_ras.c for
	251	* more details
	252	*/
	253	struct sibling_subcore_state *sibling_subcore_state;
	254	#endif
4b7ae55d	255	#endif
aa8a5e00 ME	256	#ifdef CONFIG_PPC_BOOK3S_64
	257	/*
	258	* rfi fallback flush must be in its own cacheline to prevent
	259	* other paca data leaking into the L1d
	260	*/
	261	u64 exrfi[EX_SIZE] __aligned(0x80);
	262	void *rfi_flush_fallback_area;
bdcb1aef	263	u64 l1d_flush_size;
aa8a5e00	264	#endif
94675cce MS	265	#ifdef CONFIG_PPC_PSERIES
	266	u8 mce_data_buf; / buffer to hold per cpu rtas errlog */
	267	#endif /* CONFIG_PPC_PSERIES */
c6d15258 MS	268
c6d15258 MS	269	#ifdef CONFIG_PPC_BOOK3S_64
387e220a	270	#ifdef CONFIG_PPC_64S_HASH_MMU
c6d15258 MS	271	/* Capture SLB related old contents in MCE handler. */
	272	struct slb_entry *mce_faulty_slbs;
	273	u16 slb_save_cache_ptr;
387e220a	274	#endif
c6d15258	275	#endif /* CONFIG_PPC_BOOK3S_64 */
06ec27ae CL	276	#ifdef CONFIG_STACKPROTECTOR
	277	unsigned long canary;
	278	#endif
420af155 WD	279	#ifdef CONFIG_MMIOWB
	280	struct mmiowb_state mmiowb_state;
	281	#endif
923b3cf0 GG	282	#ifdef CONFIG_PPC_BOOK3S_64
923b3cf0 GG	283	struct mce_info *mce_info;
cc15ff32	284	u8 mce_pending_irq_work;
923b3cf0	285	#endif /* CONFIG_PPC_BOOK3S_64 */
d2e60075	286	} ____cacheline_aligned;
1da177e4	287
54be0b9c	288	extern void copy_mm_to_paca(struct mm_struct *mm);
d2e60075	289	extern struct paca_struct **paca_ptrs;
1426d5a3	290	extern void initialise_paca(struct paca_struct *new_paca, int cpu);
fc53b420	291	extern void setup_paca(struct paca_struct *new_paca);
59f57774 NP	292	extern void allocate_paca_ptrs(void);
59f57774 NP	293	extern void allocate_paca(int cpu);
1426d5a3 ME	294	extern void free_unused_pacas(void);
	295
	296	#else /* CONFIG_PPC64 */
	297
6c6fdbb2 CF	298	static inline void allocate_paca_ptrs(void) { }
	299	static inline void allocate_paca(int cpu) { }
	300	static inline void free_unused_pacas(void) { }
1426d5a3 ME	301
1426d5a3 ME	302	#endif /* CONFIG_PPC64 */
1da177e4	303
88ced031	304	#endif /* __KERNEL__ */
8882a4da	305	#endif /* _ASM_POWERPC_PACA_H */