[linux-2.6-block.git] / arch / powerpc / include / asm / opal.h

/*
 * PowerNV OPAL definitions.
 *
 * Copyright 2011 IBM Corp.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#ifndef __OPAL_H
#define __OPAL_H

/****** Takeover interface ********/

/* PAPR H-Call used to querty the HAL existence and/or instanciate
 * it from within pHyp (tech preview only).
 *
 * This is exclusively used in prom_init.c
 */

#ifndef __ASSEMBLY__

struct opal_takeover_args {
	u64	k_image;		/* r4 */
	u64	k_size;			/* r5 */
	u64	k_entry;		/* r6 */
	u64	k_entry2;		/* r7 */
	u64	hal_addr;		/* r8 */
	u64	rd_image;		/* r9 */
	u64	rd_size;		/* r10 */
	u64	rd_loc;			/* r11 */
};

extern long opal_query_takeover(u64 *hal_size, u64 *hal_align);

extern long opal_do_takeover(struct opal_takeover_args *args);

struct rtas_args;
extern int opal_enter_rtas(struct rtas_args *args,
			   unsigned long data,
			   unsigned long entry);

#endif /* __ASSEMBLY__ */

/****** OPAL APIs ******/

/* Return codes */
#define OPAL_SUCCESS 		0
#define OPAL_PARAMETER		-1
#define OPAL_BUSY		-2
#define OPAL_PARTIAL		-3
#define OPAL_CONSTRAINED	-4
#define OPAL_CLOSED		-5
#define OPAL_HARDWARE		-6
#define OPAL_UNSUPPORTED	-7
#define OPAL_PERMISSION		-8
#define OPAL_NO_MEM		-9
#define OPAL_RESOURCE		-10
#define OPAL_INTERNAL_ERROR	-11
#define OPAL_BUSY_EVENT		-12
#define OPAL_HARDWARE_FROZEN	-13

/* API Tokens (in r0) */
#define OPAL_CONSOLE_WRITE			1
#define OPAL_CONSOLE_READ			2
#define OPAL_RTC_READ				3
#define OPAL_RTC_WRITE				4
#define OPAL_CEC_POWER_DOWN			5
#define OPAL_CEC_REBOOT				6
#define OPAL_READ_NVRAM				7
#define OPAL_WRITE_NVRAM			8
#define OPAL_HANDLE_INTERRUPT			9
#define OPAL_POLL_EVENTS			10
#define OPAL_PCI_SET_HUB_TCE_MEMORY		11
#define OPAL_PCI_SET_PHB_TCE_MEMORY		12
#define OPAL_PCI_CONFIG_READ_BYTE		13
#define OPAL_PCI_CONFIG_READ_HALF_WORD  	14
#define OPAL_PCI_CONFIG_READ_WORD		15
#define OPAL_PCI_CONFIG_WRITE_BYTE		16
#define OPAL_PCI_CONFIG_WRITE_HALF_WORD		17
#define OPAL_PCI_CONFIG_WRITE_WORD		18
#define OPAL_SET_XIVE				19
#define OPAL_GET_XIVE				20
#define OPAL_GET_COMPLETION_TOKEN_STATUS	21 /* obsolete */
#define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER	22
#define OPAL_PCI_EEH_FREEZE_STATUS		23
#define OPAL_PCI_SHPC				24
#define OPAL_CONSOLE_WRITE_BUFFER_SPACE		25
#define OPAL_PCI_EEH_FREEZE_CLEAR		26
#define OPAL_PCI_PHB_MMIO_ENABLE		27
#define OPAL_PCI_SET_PHB_MEM_WINDOW		28
#define OPAL_PCI_MAP_PE_MMIO_WINDOW		29
#define OPAL_PCI_SET_PHB_TABLE_MEMORY		30
#define OPAL_PCI_SET_PE				31
#define OPAL_PCI_SET_PELTV			32
#define OPAL_PCI_SET_MVE			33
#define OPAL_PCI_SET_MVE_ENABLE			34
#define OPAL_PCI_GET_XIVE_REISSUE		35
#define OPAL_PCI_SET_XIVE_REISSUE		36
#define OPAL_PCI_SET_XIVE_PE			37
#define OPAL_GET_XIVE_SOURCE			38
#define OPAL_GET_MSI_32				39
#define OPAL_GET_MSI_64				40
#define OPAL_START_CPU				41
#define OPAL_QUERY_CPU_STATUS			42
#define OPAL_WRITE_OPPANEL			43
#define OPAL_PCI_MAP_PE_DMA_WINDOW		44
#define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL		45
#define OPAL_PCI_RESET				49

#ifndef __ASSEMBLY__

/* Other enums */
enum OpalVendorApiTokens {
	OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
};
enum OpalFreezeState {
	OPAL_EEH_STOPPED_NOT_FROZEN = 0,
	OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
	OPAL_EEH_STOPPED_DMA_FREEZE = 2,
	OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
	OPAL_EEH_STOPPED_RESET = 4,
	OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
	OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
};
enum OpalEehFreezeActionToken {
	OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
	OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
	OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
};
enum OpalPciStatusToken {
	OPAL_EEH_PHB_NO_ERROR = 0,
	OPAL_EEH_PHB_FATAL = 1,
	OPAL_EEH_PHB_RECOVERABLE = 2,
	OPAL_EEH_PHB_BUS_ERROR = 3,
	OPAL_EEH_PCI_NO_DEVSEL = 4,
	OPAL_EEH_PCI_TA = 5,
	OPAL_EEH_PCIEX_UR = 6,
	OPAL_EEH_PCIEX_CA = 7,
	OPAL_EEH_PCI_MMIO_ERROR = 8,
	OPAL_EEH_PCI_DMA_ERROR = 9
};
enum OpalShpcAction {
	OPAL_SHPC_GET_LINK_STATE = 0,
	OPAL_SHPC_GET_SLOT_STATE = 1
};
enum OpalShpcLinkState {
	OPAL_SHPC_LINK_DOWN = 0,
	OPAL_SHPC_LINK_UP = 1
};
enum OpalMmioWindowType {
	OPAL_M32_WINDOW_TYPE = 1,
	OPAL_M64_WINDOW_TYPE = 2,
	OPAL_IO_WINDOW_TYPE = 3
};
enum OpalShpcSlotState {
	OPAL_SHPC_DEV_NOT_PRESENT = 0,
	OPAL_SHPC_DEV_PRESENT = 1
};
enum OpalExceptionHandler {
	OPAL_MACHINE_CHECK_HANDLER = 1,
	OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
	OPAL_SOFTPATCH_HANDLER = 3
};
enum OpalPendingState {
	OPAL_EVENT_OPAL_INTERNAL = 0x1,
	OPAL_EVENT_NVRAM = 0x2,
	OPAL_EVENT_RTC = 0x4,
	OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
	OPAL_EVENT_CONSOLE_INPUT = 0x10
};

/* Machine check related definitions */
enum OpalMCE_Version {
	OpalMCE_V1 = 1,
};

enum OpalMCE_Severity {
	OpalMCE_SEV_NO_ERROR = 0,
	OpalMCE_SEV_WARNING = 1,
	OpalMCE_SEV_ERROR_SYNC = 2,
	OpalMCE_SEV_FATAL = 3,
};

enum OpalMCE_Disposition {
	OpalMCE_DISPOSITION_RECOVERED = 0,
	OpalMCE_DISPOSITION_NOT_RECOVERED = 1,
};

enum OpalMCE_Initiator {
	OpalMCE_INITIATOR_UNKNOWN = 0,
	OpalMCE_INITIATOR_CPU = 1,
};

enum OpalMCE_ErrorType {
	OpalMCE_ERROR_TYPE_UNKNOWN = 0,
	OpalMCE_ERROR_TYPE_UE = 1,
	OpalMCE_ERROR_TYPE_SLB = 2,
	OpalMCE_ERROR_TYPE_ERAT = 3,
	OpalMCE_ERROR_TYPE_TLB = 4,
};

enum OpalMCE_UeErrorType {
	OpalMCE_UE_ERROR_INDETERMINATE = 0,
	OpalMCE_UE_ERROR_IFETCH = 1,
	OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
	OpalMCE_UE_ERROR_LOAD_STORE = 3,
	OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
};

enum OpalMCE_SlbErrorType {
	OpalMCE_SLB_ERROR_INDETERMINATE = 0,
	OpalMCE_SLB_ERROR_PARITY = 1,
	OpalMCE_SLB_ERROR_MULTIHIT = 2,
};

enum OpalMCE_EratErrorType {
	OpalMCE_ERAT_ERROR_INDETERMINATE = 0,
	OpalMCE_ERAT_ERROR_PARITY = 1,
	OpalMCE_ERAT_ERROR_MULTIHIT = 2,
};

enum OpalMCE_TlbErrorType {
	OpalMCE_TLB_ERROR_INDETERMINATE = 0,
	OpalMCE_TLB_ERROR_PARITY = 1,
	OpalMCE_TLB_ERROR_MULTIHIT = 2,
};

enum OpalThreadStatus {
	OPAL_THREAD_INACTIVE = 0x0,
	OPAL_THREAD_STARTED = 0x1
};

enum OpalPciBusCompare {
	OpalPciBusAny	= 0,	/* Any bus number match */
	OpalPciBus3Bits	= 2,	/* Match top 3 bits of bus number */
	OpalPciBus4Bits	= 3,	/* Match top 4 bits of bus number */
	OpalPciBus5Bits	= 4,	/* Match top 5 bits of bus number */
	OpalPciBus6Bits	= 5,	/* Match top 6 bits of bus number */
	OpalPciBus7Bits	= 6,	/* Match top 7 bits of bus number */
	OpalPciBusAll	= 7,	/* Match bus number exactly */
};

enum OpalDeviceCompare {
	OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
	OPAL_COMPARE_RID_DEVICE_NUMBER = 1
};

enum OpalFuncCompare {
	OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
	OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
};

enum OpalPeAction {
	OPAL_UNMAP_PE = 0,
	OPAL_MAP_PE = 1
};

enum OpalPciResetAndReinitScope {
	OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
	OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
	OPAL_PCI_IODA_RESET = 6,
};

enum OpalPciResetState { OPAL_DEASSERT_RESET = 0, OPAL_ASSERT_RESET = 1 };

struct opal_machine_check_event {
	enum OpalMCE_Version	version:8;	/* 0x00 */
	uint8_t			in_use;		/* 0x01 */
	enum OpalMCE_Severity	severity:8;	/* 0x02 */
	enum OpalMCE_Initiator	initiator:8;	/* 0x03 */
	enum OpalMCE_ErrorType	error_type:8;	/* 0x04 */
	enum OpalMCE_Disposition disposition:8; /* 0x05 */
	uint8_t			reserved_1[2];	/* 0x06 */
	uint64_t		gpr3;		/* 0x08 */
	uint64_t		srr0;		/* 0x10 */
	uint64_t		srr1;		/* 0x18 */
	union {					/* 0x20 */
		struct {
			enum OpalMCE_UeErrorType ue_error_type:8;
			uint8_t		effective_address_provided;
			uint8_t		physical_address_provided;
			uint8_t		reserved_1[5];
			uint64_t	effective_address;
			uint64_t	physical_address;
			uint8_t		reserved_2[8];
		} ue_error;

		struct {
			enum OpalMCE_SlbErrorType slb_error_type:8;
			uint8_t		effective_address_provided;
			uint8_t		reserved_1[6];
			uint64_t	effective_address;
			uint8_t		reserved_2[16];
		} slb_error;

		struct {
			enum OpalMCE_EratErrorType erat_error_type:8;
			uint8_t		effective_address_provided;
			uint8_t		reserved_1[6];
			uint64_t	effective_address;
			uint8_t		reserved_2[16];
		} erat_error;

		struct {
			enum OpalMCE_TlbErrorType tlb_error_type:8;
			uint8_t		effective_address_provided;
			uint8_t		reserved_1[6];
			uint64_t	effective_address;
			uint8_t		reserved_2[16];
		} tlb_error;
	} u;
};

typedef struct oppanel_line {
	/* XXX */
} oppanel_line_t;

/* API functions */
int64_t opal_console_write(int64_t term_number, int64_t *length,
			   const uint8_t *buffer);
int64_t opal_console_read(int64_t term_number, int64_t *length,
			  uint8_t *buffer);
int64_t opal_console_write_buffer_space(int64_t term_number,
					int64_t *length);
int64_t opal_rtc_read(uint32_t *year_month_day,
		      uint64_t *hour_minute_second_millisecond);
int64_t opal_rtc_write(uint32_t year_month_day,
		       uint64_t hour_minute_second_millisecond);
int64_t opal_cec_power_down(uint64_t request);
int64_t opal_cec_reboot(void);
int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
int64_t opal_handle_interrupt(uint64_t isn, uint64_t *outstanding_event_mask);
int64_t opal_poll_events(uint64_t *outstanding_event_mask);
int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
				    uint64_t tce_mem_size);
int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
				    uint64_t tce_mem_size);
int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
				  uint64_t offset, uint8_t *data);
int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
				       uint64_t offset, uint16_t *data);
int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
				  uint64_t offset, uint32_t *data);
int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
				   uint64_t offset, uint8_t data);
int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
					uint64_t offset, uint16_t data);
int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
				   uint64_t offset, uint32_t data);
int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
int64_t opal_get_xive(uint32_t isn, uint16_t *server, uint8_t *priority);
int64_t opal_register_exception_handler(uint64_t opal_exception,
					uint64_t handler_address,
					uint64_t glue_cache_line);
int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
				   uint8_t *freeze_state,
				   uint16_t *pci_error_type,
				   uint64_t *phb_status);
int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
				  uint64_t eeh_action_token);
int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);


int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
				 uint16_t window_num, uint16_t enable);
int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
				    uint16_t window_num,
				    uint64_t starting_real_address,
				    uint64_t starting_pci_address,
				    uint16_t segment_size);
int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
				    uint16_t window_type, uint16_t window_num,
				    uint16_t segment_num);
int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
				      uint64_t ivt_addr, uint64_t ivt_len,
				      uint64_t reject_array_addr,
				      uint64_t peltv_addr);
int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
			uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
			uint8_t pe_action);
int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
			   uint8_t state);
int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
				uint32_t state);
int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
				  uint8_t *p_bit, uint8_t *q_bit);
int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
				  uint8_t p_bit, uint8_t q_bit);
int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
			     uint32_t xive_num);
int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
			     int32_t *interrupt_source_number);
int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
			uint8_t msi_range, uint32_t *msi_address,
			uint32_t *message_data);
int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
			uint32_t xive_num, uint8_t msi_range,
			uint64_t *msi_address, uint32_t *message_data);
int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
				   uint16_t tce_levels, uint64_t tce_table_addr,
				   uint64_t tce_table_size, uint64_t tce_page_size);
int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
					uint16_t dma_window_number, uint64_t pci_start_addr,
					uint64_t pci_mem_size);
int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);

/* Internal functions */
extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);

extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);

extern void hvc_opal_init_early(void);

/* Internal functions */
extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
				   int depth, void *data);

extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);

extern void hvc_opal_init_early(void);

#endif /* __ASSEMBLY__ */

#endif /* __OPAL_H */
Commit	Line	Data
27f44888 BH	1	/*
	2	* PowerNV OPAL definitions.
	3	*
	4	* Copyright 2011 IBM Corp.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the License, or (at your option) any later version.
	10	*/
	11
	12	#ifndef __OPAL_H
	13	#define __OPAL_H
	14
	15	/**** Takeover interface ******/
	16
	17	/* PAPR H-Call used to querty the HAL existence and/or instanciate
	18	* it from within pHyp (tech preview only).
	19	*
	20	* This is exclusively used in prom_init.c
	21	*/
	22
	23	#ifndef __ASSEMBLY__
	24
	25	struct opal_takeover_args {
	26	u64 k_image; /* r4 */
	27	u64 k_size; /* r5 */
	28	u64 k_entry; /* r6 */
	29	u64 k_entry2; /* r7 */
	30	u64 hal_addr; /* r8 */
	31	u64 rd_image; /* r9 */
	32	u64 rd_size; /* r10 */
	33	u64 rd_loc; /* r11 */
	34	};
	35
	36	extern long opal_query_takeover(u64 hal_size, u64 hal_align);
	37
	38	extern long opal_do_takeover(struct opal_takeover_args *args);
	39
14a43e69	40	struct rtas_args;
27f44888 BH	41	extern int opal_enter_rtas(struct rtas_args *args,
	42	unsigned long data,
	43	unsigned long entry);
	44
27f44888 BH	45	#endif /* __ASSEMBLY__ */
	46
	47	/**** OPAL APIs ****/
	48
14a43e69 BH	49	/* Return codes */
	50	#define OPAL_SUCCESS 0
	51	#define OPAL_PARAMETER -1
	52	#define OPAL_BUSY -2
	53	#define OPAL_PARTIAL -3
	54	#define OPAL_CONSTRAINED -4
	55	#define OPAL_CLOSED -5
	56	#define OPAL_HARDWARE -6
	57	#define OPAL_UNSUPPORTED -7
	58	#define OPAL_PERMISSION -8
	59	#define OPAL_NO_MEM -9
	60	#define OPAL_RESOURCE -10
	61	#define OPAL_INTERNAL_ERROR -11
	62	#define OPAL_BUSY_EVENT -12
	63	#define OPAL_HARDWARE_FROZEN -13
	64
	65	/* API Tokens (in r0) */
	66	#define OPAL_CONSOLE_WRITE 1
	67	#define OPAL_CONSOLE_READ 2
	68	#define OPAL_RTC_READ 3
	69	#define OPAL_RTC_WRITE 4
	70	#define OPAL_CEC_POWER_DOWN 5
	71	#define OPAL_CEC_REBOOT 6
	72	#define OPAL_READ_NVRAM 7
	73	#define OPAL_WRITE_NVRAM 8
	74	#define OPAL_HANDLE_INTERRUPT 9
	75	#define OPAL_POLL_EVENTS 10
	76	#define OPAL_PCI_SET_HUB_TCE_MEMORY 11
	77	#define OPAL_PCI_SET_PHB_TCE_MEMORY 12
	78	#define OPAL_PCI_CONFIG_READ_BYTE 13
	79	#define OPAL_PCI_CONFIG_READ_HALF_WORD 14
	80	#define OPAL_PCI_CONFIG_READ_WORD 15
	81	#define OPAL_PCI_CONFIG_WRITE_BYTE 16
	82	#define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
	83	#define OPAL_PCI_CONFIG_WRITE_WORD 18
	84	#define OPAL_SET_XIVE 19
	85	#define OPAL_GET_XIVE 20
	86	#define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
	87	#define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
	88	#define OPAL_PCI_EEH_FREEZE_STATUS 23
	89	#define OPAL_PCI_SHPC 24
	90	#define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
	91	#define OPAL_PCI_EEH_FREEZE_CLEAR 26
	92	#define OPAL_PCI_PHB_MMIO_ENABLE 27
	93	#define OPAL_PCI_SET_PHB_MEM_WINDOW 28
	94	#define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
	95	#define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
	96	#define OPAL_PCI_SET_PE 31
	97	#define OPAL_PCI_SET_PELTV 32
	98	#define OPAL_PCI_SET_MVE 33
	99	#define OPAL_PCI_SET_MVE_ENABLE 34
	100	#define OPAL_PCI_GET_XIVE_REISSUE 35
	101	#define OPAL_PCI_SET_XIVE_REISSUE 36
	102	#define OPAL_PCI_SET_XIVE_PE 37
	103	#define OPAL_GET_XIVE_SOURCE 38
	104	#define OPAL_GET_MSI_32 39
	105	#define OPAL_GET_MSI_64 40
	106	#define OPAL_START_CPU 41
	107	#define OPAL_QUERY_CPU_STATUS 42
	108	#define OPAL_WRITE_OPPANEL 43
	109	#define OPAL_PCI_MAP_PE_DMA_WINDOW 44
	110	#define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
	111	#define OPAL_PCI_RESET 49
	112
113	#ifndef __ASSEMBLY__
114
115	/* Other enums */
116	enum OpalVendorApiTokens {
117	OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
118	};
119	enum OpalFreezeState {
120	OPAL_EEH_STOPPED_NOT_FROZEN = 0,
121	OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
122	OPAL_EEH_STOPPED_DMA_FREEZE = 2,
123	OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
124	OPAL_EEH_STOPPED_RESET = 4,
125	OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
126	OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
127	};
128	enum OpalEehFreezeActionToken {
129	OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
130	OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
131	OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
132	};
133	enum OpalPciStatusToken {
134	OPAL_EEH_PHB_NO_ERROR = 0,
135	OPAL_EEH_PHB_FATAL = 1,
136	OPAL_EEH_PHB_RECOVERABLE = 2,
137	OPAL_EEH_PHB_BUS_ERROR = 3,
138	OPAL_EEH_PCI_NO_DEVSEL = 4,
139	OPAL_EEH_PCI_TA = 5,
140	OPAL_EEH_PCIEX_UR = 6,
141	OPAL_EEH_PCIEX_CA = 7,
142	OPAL_EEH_PCI_MMIO_ERROR = 8,
143	OPAL_EEH_PCI_DMA_ERROR = 9
144	};
145	enum OpalShpcAction {
146	OPAL_SHPC_GET_LINK_STATE = 0,
147	OPAL_SHPC_GET_SLOT_STATE = 1
148	};
149	enum OpalShpcLinkState {
150	OPAL_SHPC_LINK_DOWN = 0,
151	OPAL_SHPC_LINK_UP = 1
152	};
153	enum OpalMmioWindowType {
154	OPAL_M32_WINDOW_TYPE = 1,
155	OPAL_M64_WINDOW_TYPE = 2,
156	OPAL_IO_WINDOW_TYPE = 3
157	};
158	enum OpalShpcSlotState {
159	OPAL_SHPC_DEV_NOT_PRESENT = 0,
160	OPAL_SHPC_DEV_PRESENT = 1
161	};
162	enum OpalExceptionHandler {
163	OPAL_MACHINE_CHECK_HANDLER = 1,
164	OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
165	OPAL_SOFTPATCH_HANDLER = 3
166	};
167	enum OpalPendingState {
168	OPAL_EVENT_OPAL_INTERNAL = 0x1,
169	OPAL_EVENT_NVRAM = 0x2,
170	OPAL_EVENT_RTC = 0x4,
171	OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
172	OPAL_EVENT_CONSOLE_INPUT = 0x10
173	};
174
175	/* Machine check related definitions */
176	enum OpalMCE_Version {
177	OpalMCE_V1 = 1,
178	};
179
180	enum OpalMCE_Severity {
181	OpalMCE_SEV_NO_ERROR = 0,
182	OpalMCE_SEV_WARNING = 1,
183	OpalMCE_SEV_ERROR_SYNC = 2,
184	OpalMCE_SEV_FATAL = 3,
185	};
186
187	enum OpalMCE_Disposition {
188	OpalMCE_DISPOSITION_RECOVERED = 0,
189	OpalMCE_DISPOSITION_NOT_RECOVERED = 1,
190	};
191
192	enum OpalMCE_Initiator {
193	OpalMCE_INITIATOR_UNKNOWN = 0,
194	OpalMCE_INITIATOR_CPU = 1,
195	};
196
197	enum OpalMCE_ErrorType {
198	OpalMCE_ERROR_TYPE_UNKNOWN = 0,
199	OpalMCE_ERROR_TYPE_UE = 1,
200	OpalMCE_ERROR_TYPE_SLB = 2,
201	OpalMCE_ERROR_TYPE_ERAT = 3,
202	OpalMCE_ERROR_TYPE_TLB = 4,
203	};
204
205	enum OpalMCE_UeErrorType {
206	OpalMCE_UE_ERROR_INDETERMINATE = 0,
207	OpalMCE_UE_ERROR_IFETCH = 1,
208	OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
209	OpalMCE_UE_ERROR_LOAD_STORE = 3,
210	OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
211	};
212
213	enum OpalMCE_SlbErrorType {
214	OpalMCE_SLB_ERROR_INDETERMINATE = 0,
215	OpalMCE_SLB_ERROR_PARITY = 1,
216	OpalMCE_SLB_ERROR_MULTIHIT = 2,
217	};
218
219	enum OpalMCE_EratErrorType {
220	OpalMCE_ERAT_ERROR_INDETERMINATE = 0,
221	OpalMCE_ERAT_ERROR_PARITY = 1,
222	OpalMCE_ERAT_ERROR_MULTIHIT = 2,
223	};
224
225	enum OpalMCE_TlbErrorType {
226	OpalMCE_TLB_ERROR_INDETERMINATE = 0,
227	OpalMCE_TLB_ERROR_PARITY = 1,
228	OpalMCE_TLB_ERROR_MULTIHIT = 2,
229	};
230
231	enum OpalThreadStatus {
232	OPAL_THREAD_INACTIVE = 0x0,
233	OPAL_THREAD_STARTED = 0x1
234	};
235
236	enum OpalPciBusCompare {
237	OpalPciBusAny = 0, /* Any bus number match */
238	OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */
239	OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */
240	OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */
241	OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */
242	OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */
243	OpalPciBusAll = 7, /* Match bus number exactly */
244	};
245
246	enum OpalDeviceCompare {
247	OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
248	OPAL_COMPARE_RID_DEVICE_NUMBER = 1
249	};
250
251	enum OpalFuncCompare {
252	OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
253	OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
254	};
255
256	enum OpalPeAction {
257	OPAL_UNMAP_PE = 0,
258	OPAL_MAP_PE = 1
259	};
260
261	enum OpalPciResetAndReinitScope {
262	OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
263	OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
264	OPAL_PCI_IODA_RESET = 6,
265	};
266
267	enum OpalPciResetState { OPAL_DEASSERT_RESET = 0, OPAL_ASSERT_RESET = 1 };
268
269	struct opal_machine_check_event {
270	enum OpalMCE_Version version:8; /* 0x00 */
271	uint8_t in_use; /* 0x01 */
272	enum OpalMCE_Severity severity:8; /* 0x02 */
273	enum OpalMCE_Initiator initiator:8; /* 0x03 */
274	enum OpalMCE_ErrorType error_type:8; /* 0x04 */
275	enum OpalMCE_Disposition disposition:8; /* 0x05 */
276	uint8_t reserved_1[2]; /* 0x06 */
277	uint64_t gpr3; /* 0x08 */
278	uint64_t srr0; /* 0x10 */
279	uint64_t srr1; /* 0x18 */
280	union { /* 0x20 */
281	struct {
282	enum OpalMCE_UeErrorType ue_error_type:8;
283	uint8_t effective_address_provided;
284	uint8_t physical_address_provided;
285	uint8_t reserved_1[5];
286	uint64_t effective_address;
287	uint64_t physical_address;
288	uint8_t reserved_2[8];
289	} ue_error;
290
291	struct {
292	enum OpalMCE_SlbErrorType slb_error_type:8;
293	uint8_t effective_address_provided;
294	uint8_t reserved_1[6];
295	uint64_t effective_address;
296	uint8_t reserved_2[16];
297	} slb_error;
298
299	struct {
300	enum OpalMCE_EratErrorType erat_error_type:8;
301	uint8_t effective_address_provided;
302	uint8_t reserved_1[6];
303	uint64_t effective_address;
304	uint8_t reserved_2[16];
305	} erat_error;
306
307	struct {
308	enum OpalMCE_TlbErrorType tlb_error_type:8;
309	uint8_t effective_address_provided;
310	uint8_t reserved_1[6];
311	uint64_t effective_address;
312	uint8_t reserved_2[16];
313	} tlb_error;
314	} u;
315	};
316
317	typedef struct oppanel_line {
318	/* XXX */
319	} oppanel_line_t;
320
321	/* API functions */
322	int64_t opal_console_write(int64_t term_number, int64_t *length,
323	const uint8_t *buffer);
324	int64_t opal_console_read(int64_t term_number, int64_t *length,
325	uint8_t *buffer);
326	int64_t opal_console_write_buffer_space(int64_t term_number,
327	int64_t *length);
328	int64_t opal_rtc_read(uint32_t *year_month_day,
329	uint64_t *hour_minute_second_millisecond);
330	int64_t opal_rtc_write(uint32_t year_month_day,
331	uint64_t hour_minute_second_millisecond);
332	int64_t opal_cec_power_down(uint64_t request);
333	int64_t opal_cec_reboot(void);
334	int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
335	int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
336	int64_t opal_handle_interrupt(uint64_t isn, uint64_t *outstanding_event_mask);
337	int64_t opal_poll_events(uint64_t *outstanding_event_mask);
338	int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
339	uint64_t tce_mem_size);
340	int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
341	uint64_t tce_mem_size);
342	int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
343	uint64_t offset, uint8_t *data);
344	int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
345	uint64_t offset, uint16_t *data);
346	int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
347	uint64_t offset, uint32_t *data);
348	int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
349	uint64_t offset, uint8_t data);
350	int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
351	uint64_t offset, uint16_t data);
352	int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
353	uint64_t offset, uint32_t data);
354	int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
355	int64_t opal_get_xive(uint32_t isn, uint16_t server, uint8_t priority);
356	int64_t opal_register_exception_handler(uint64_t opal_exception,
357	uint64_t handler_address,
358	uint64_t glue_cache_line);
359	int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
360	uint8_t *freeze_state,
361	uint16_t *pci_error_type,
362	uint64_t *phb_status);
363	int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
364	uint64_t eeh_action_token);
365	int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
366
367
368
369	int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
370	uint16_t window_num, uint16_t enable);
371	int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
372	uint16_t window_num,
373	uint64_t starting_real_address,
374	uint64_t starting_pci_address,
375	uint16_t segment_size);
376	int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
377	uint16_t window_type, uint16_t window_num,
378	uint16_t segment_num);
379	int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
380	uint64_t ivt_addr, uint64_t ivt_len,
381	uint64_t reject_array_addr,
382	uint64_t peltv_addr);
383	int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
384	uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
385	uint8_t pe_action);
386	int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
387	uint8_t state);
388	int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
389	int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
390	uint32_t state);
391	int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
392	uint8_t p_bit, uint8_t q_bit);
393	int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
394	uint8_t p_bit, uint8_t q_bit);
395	int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
396	uint32_t xive_num);
397	int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
398	int32_t *interrupt_source_number);
399	int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
400	uint8_t msi_range, uint32_t *msi_address,
401	uint32_t *message_data);
402	int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
403	uint32_t xive_num, uint8_t msi_range,
404	uint64_t msi_address, uint32_t message_data);
405	int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
406	int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
407	int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
408	int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
409	uint16_t tce_levels, uint64_t tce_table_addr,
410	uint64_t tce_table_size, uint64_t tce_page_size);
411	int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
412	uint16_t dma_window_number, uint64_t pci_start_addr,
413	uint64_t pci_mem_size);
414	int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
415
416	/* Internal functions */
417	extern int early_init_dt_scan_opal(unsigned long node, const char uname, int depth, void data);
418
419	extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
420	extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
421
422	extern void hvc_opal_init_early(void);
423
424	/* Internal functions */
425	extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
426	int depth, void *data);
427
daea1175 BH	428	extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
	429	extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
	430
	431	extern void hvc_opal_init_early(void);
	432
14a43e69	433	#endif /* __ASSEMBLY__ */
27f44888 BH	434
27f44888 BH	435	#endif /* __OPAL_H */