Commit | Line | Data |
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27f44888 BH |
1 | /* |
2 | * PowerNV OPAL definitions. | |
3 | * | |
4 | * Copyright 2011 IBM Corp. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
d800ba12 ME |
12 | #ifndef _ASM_POWERPC_OPAL_H |
13 | #define _ASM_POWERPC_OPAL_H | |
27f44888 | 14 | |
d800ba12 | 15 | #include <asm/opal-api.h> |
8eb8ac89 | 16 | |
14a43e69 BH |
17 | #ifndef __ASSEMBLY__ |
18 | ||
bfd25d72 MN |
19 | #include <linux/notifier.h> |
20 | ||
d800ba12 ME |
21 | /* We calculate number of sg entries based on PAGE_SIZE */ |
22 | #define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry)) | |
47083450 | 23 | |
34dd25de NP |
24 | /* Default time to sleep or delay between OPAL_BUSY/OPAL_BUSY_EVENT loops */ |
25 | #define OPAL_BUSY_DELAY_MS 10 | |
26 | ||
6f68b5e2 VH |
27 | /* /sys/firmware/opal */ |
28 | extern struct kobject *opal_kobj; | |
29 | ||
bfc36894 JS |
30 | /* /ibm,opal */ |
31 | extern struct device_node *opal_node; | |
32 | ||
14a43e69 | 33 | /* API functions */ |
e28b05e7 | 34 | int64_t opal_invalid_call(void); |
1ab66d1f AP |
35 | int64_t opal_npu_destroy_context(uint64_t phb_id, uint64_t pid, uint64_t bdf); |
36 | int64_t opal_npu_init_context(uint64_t phb_id, int pasid, uint64_t msr, | |
37 | uint64_t bdf); | |
38 | int64_t opal_npu_map_lpar(uint64_t phb_id, uint64_t bdf, uint64_t lparid, | |
39 | uint64_t lpcr); | |
74d656d2 FB |
40 | int64_t opal_npu_spa_setup(uint64_t phb_id, uint32_t bdfn, |
41 | uint64_t addr, uint64_t PE_mask); | |
42 | int64_t opal_npu_spa_clear_cache(uint64_t phb_id, uint32_t bdfn, | |
43 | uint64_t PE_handle); | |
44 | int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t bdfn, long cap, | |
45 | uint64_t rate_phys, uint32_t size); | |
4f89363b | 46 | int64_t opal_console_write(int64_t term_number, __be64 *length, |
14a43e69 | 47 | const uint8_t *buffer); |
4f89363b | 48 | int64_t opal_console_read(int64_t term_number, __be64 *length, |
14a43e69 BH |
49 | uint8_t *buffer); |
50 | int64_t opal_console_write_buffer_space(int64_t term_number, | |
4f89363b | 51 | __be64 *length); |
c88c5d43 | 52 | int64_t opal_console_flush(int64_t term_number); |
6feff6d4 AB |
53 | int64_t opal_rtc_read(__be32 *year_month_day, |
54 | __be64 *hour_minute_second_millisecond); | |
14a43e69 BH |
55 | int64_t opal_rtc_write(uint32_t year_month_day, |
56 | uint64_t hour_minute_second_millisecond); | |
16b1d26e NG |
57 | int64_t opal_tpo_read(uint64_t token, __be32 *year_mon_day, __be32 *hour_min); |
58 | int64_t opal_tpo_write(uint64_t token, uint32_t year_mon_day, | |
59 | uint32_t hour_min); | |
14a43e69 BH |
60 | int64_t opal_cec_power_down(uint64_t request); |
61 | int64_t opal_cec_reboot(void); | |
b746e3e0 | 62 | int64_t opal_cec_reboot2(uint32_t reboot_type, const char *diag); |
14a43e69 BH |
63 | int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset); |
64 | int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset); | |
5e4da530 | 65 | int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask); |
4f89363b | 66 | int64_t opal_poll_events(__be64 *outstanding_event_mask); |
14a43e69 BH |
67 | int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr, |
68 | uint64_t tce_mem_size); | |
69 | int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr, | |
70 | uint64_t tce_mem_size); | |
71 | int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func, | |
72 | uint64_t offset, uint8_t *data); | |
73 | int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func, | |
5e4da530 | 74 | uint64_t offset, __be16 *data); |
14a43e69 | 75 | int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func, |
5e4da530 | 76 | uint64_t offset, __be32 *data); |
14a43e69 BH |
77 | int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func, |
78 | uint64_t offset, uint8_t data); | |
79 | int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func, | |
80 | uint64_t offset, uint16_t data); | |
81 | int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func, | |
82 | uint64_t offset, uint32_t data); | |
83 | int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority); | |
5e4da530 | 84 | int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority); |
14a43e69 BH |
85 | int64_t opal_register_exception_handler(uint64_t opal_exception, |
86 | uint64_t handler_address, | |
87 | uint64_t glue_cache_line); | |
88 | int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number, | |
89 | uint8_t *freeze_state, | |
5e4da530 AB |
90 | __be16 *pci_error_type, |
91 | __be64 *phb_status); | |
14a43e69 BH |
92 | int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number, |
93 | uint64_t eeh_action_token); | |
5ca27efb GS |
94 | int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number, |
95 | uint64_t eeh_action_token); | |
5b642340 GS |
96 | int64_t opal_pci_err_inject(uint64_t phb_id, uint32_t pe_no, uint32_t type, |
97 | uint32_t func, uint64_t addr, uint64_t mask); | |
14a43e69 BH |
98 | int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state); |
99 | ||
100 | ||
101 | ||
102 | int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type, | |
103 | uint16_t window_num, uint16_t enable); | |
104 | int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type, | |
105 | uint16_t window_num, | |
106 | uint64_t starting_real_address, | |
107 | uint64_t starting_pci_address, | |
262af557 | 108 | uint64_t size); |
14a43e69 BH |
109 | int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number, |
110 | uint16_t window_type, uint16_t window_num, | |
111 | uint16_t segment_num); | |
112 | int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr, | |
113 | uint64_t ivt_addr, uint64_t ivt_len, | |
114 | uint64_t reject_array_addr, | |
115 | uint64_t peltv_addr); | |
116 | int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func, | |
117 | uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare, | |
118 | uint8_t pe_action); | |
119 | int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe, | |
120 | uint8_t state); | |
121 | int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number); | |
122 | int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number, | |
123 | uint32_t state); | |
124 | int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number, | |
125 | uint8_t *p_bit, uint8_t *q_bit); | |
126 | int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number, | |
127 | uint8_t p_bit, uint8_t q_bit); | |
137436c9 | 128 | int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq); |
14a43e69 BH |
129 | int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number, |
130 | uint32_t xive_num); | |
131 | int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num, | |
5e4da530 | 132 | __be32 *interrupt_source_number); |
14a43e69 | 133 | int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num, |
5e4da530 AB |
134 | uint8_t msi_range, __be32 *msi_address, |
135 | __be32 *message_data); | |
14a43e69 BH |
136 | int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number, |
137 | uint32_t xive_num, uint8_t msi_range, | |
5e4da530 | 138 | __be64 *msi_address, __be32 *message_data); |
14a43e69 BH |
139 | int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address); |
140 | int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status); | |
141 | int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines); | |
142 | int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id, | |
143 | uint16_t tce_levels, uint64_t tce_table_addr, | |
144 | uint64_t tce_table_size, uint64_t tce_page_size); | |
145 | int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number, | |
146 | uint16_t dma_window_number, uint64_t pci_start_addr, | |
147 | uint64_t pci_mem_size); | |
ebe22531 | 148 | int64_t opal_pci_reset(uint64_t id, uint8_t reset_scope, uint8_t assert_state); |
14a43e69 | 149 | |
23773230 GS |
150 | int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer, |
151 | uint64_t diag_buffer_len); | |
152 | int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer, | |
153 | uint64_t diag_buffer_len); | |
154 | int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer, | |
155 | uint64_t diag_buffer_len); | |
f11fe552 | 156 | int64_t opal_pci_fence_phb(uint64_t phb_id); |
9be3becc | 157 | int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data); |
f11fe552 BH |
158 | int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action); |
159 | int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action); | |
3b476aad VP |
160 | int64_t opal_get_epow_status(__be16 *epow_status, __be16 *num_epow_classes); |
161 | int64_t opal_get_dpo_status(__be64 *dpo_timeout); | |
f11fe552 | 162 | int64_t opal_set_system_attention_led(uint8_t led_action); |
ddf0322a GC |
163 | int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe, |
164 | __be16 *pci_error_type, __be16 *severity); | |
ebe22531 | 165 | int64_t opal_pci_poll(uint64_t id); |
13906db6 | 166 | int64_t opal_return_cpu(void); |
bffe6bda | 167 | int64_t opal_check_token(uint64_t token); |
4926616c | 168 | int64_t opal_reinit_cpus(uint64_t flags); |
f11fe552 | 169 | |
2f3f38e4 BH |
170 | int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val); |
171 | int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val); | |
cc0efb57 BH |
172 | |
173 | int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type, | |
174 | uint32_t addr, uint32_t data, uint32_t sz); | |
175 | int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type, | |
803c2d2f | 176 | uint32_t addr, __be32 *data, uint32_t sz); |
774fea1a | 177 | |
2bad7423 | 178 | int64_t opal_read_elog(uint64_t buffer, uint64_t size, uint64_t log_id); |
14ad0c58 | 179 | int64_t opal_get_elog_size(__be64 *log_id, __be64 *size, __be64 *elog_type); |
774fea1a SS |
180 | int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset); |
181 | int64_t opal_send_ack_elog(uint64_t log_id); | |
182 | void opal_resend_pending_logs(void); | |
183 | ||
50bd6153 VH |
184 | int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result); |
185 | int64_t opal_manage_flash(uint8_t op); | |
186 | int64_t opal_update_flash(uint64_t blk_list); | |
c7e64b9c | 187 | int64_t opal_dump_init(uint8_t dump_type); |
2d6b63bb AB |
188 | int64_t opal_dump_info(__be32 *dump_id, __be32 *dump_size); |
189 | int64_t opal_dump_info2(__be32 *dump_id, __be32 *dump_size, __be32 *dump_type); | |
c7e64b9c SS |
190 | int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer); |
191 | int64_t opal_dump_ack(uint32_t dump_id); | |
192 | int64_t opal_dump_resend_notification(void); | |
cc0efb57 | 193 | |
2bad7423 | 194 | int64_t opal_get_msg(uint64_t buffer, uint64_t size); |
43a1dd9b SJS |
195 | int64_t opal_write_oppanel_async(uint64_t token, oppanel_line_t *lines, |
196 | uint64_t num_lines); | |
2bad7423 | 197 | int64_t opal_check_completion(uint64_t buffer, uint64_t size, uint64_t token); |
f7d98d18 | 198 | int64_t opal_sync_host_reboot(void); |
4029cd66 | 199 | int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer, |
2bad7423 | 200 | uint64_t length); |
4029cd66 | 201 | int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer, |
2bad7423 | 202 | uint64_t length); |
9000c17d | 203 | int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data); |
5cdcb01e | 204 | int64_t opal_sensor_read_u64(u32 sensor_hndl, int token, __be64 *sensor_data); |
0ef95b41 | 205 | int64_t opal_handle_hmi(void); |
b09c2ec4 VH |
206 | int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end); |
207 | int64_t opal_unregister_dump_region(uint32_t id); | |
77b54e9f | 208 | int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val); |
5703d2f4 | 209 | int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t flag); |
09521736 | 210 | int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id, uint64_t mode, uint64_t pe_number); |
d6a90bb8 PB |
211 | int64_t opal_pci_get_pbcq_tunnel_bar(uint64_t phb_id, uint64_t *addr); |
212 | int64_t opal_pci_set_pbcq_tunnel_bar(uint64_t phb_id, uint64_t addr); | |
608b286d JK |
213 | int64_t opal_ipmi_send(uint64_t interface, struct opal_ipmi_msg *msg, |
214 | uint64_t msg_len); | |
215 | int64_t opal_ipmi_recv(uint64_t interface, struct opal_ipmi_msg *msg, | |
216 | uint64_t *msg_len); | |
47083450 NG |
217 | int64_t opal_i2c_request(uint64_t async_token, uint32_t bus_id, |
218 | struct opal_i2c_request *oreq); | |
0d7cd855 | 219 | int64_t opal_prd_msg(struct opal_prd_msg *msg); |
8a8d9181 AK |
220 | int64_t opal_leds_get_ind(char *loc_code, __be64 *led_mask, |
221 | __be64 *led_value, __be64 *max_led_type); | |
222 | int64_t opal_leds_set_ind(uint64_t token, char *loc_code, const u64 led_mask, | |
223 | const u64 led_value, __be64 *max_led_type); | |
24366360 | 224 | |
ed59190e CB |
225 | int64_t opal_flash_read(uint64_t id, uint64_t offset, uint64_t buf, |
226 | uint64_t size, uint64_t token); | |
227 | int64_t opal_flash_write(uint64_t id, uint64_t offset, uint64_t buf, | |
228 | uint64_t size, uint64_t token); | |
229 | int64_t opal_flash_erase(uint64_t id, uint64_t offset, uint64_t size, | |
230 | uint64_t token); | |
ea0d856c GS |
231 | int64_t opal_get_device_tree(uint32_t phandle, uint64_t buf, uint64_t len); |
232 | int64_t opal_pci_get_presence_state(uint64_t id, uint64_t data); | |
233 | int64_t opal_pci_get_power_state(uint64_t id, uint64_t data); | |
234 | int64_t opal_pci_set_power_state(uint64_t async_token, uint64_t id, | |
235 | uint64_t data); | |
236 | int64_t opal_pci_poll2(uint64_t id, uint64_t data); | |
ed59190e | 237 | |
9fedd3f8 BH |
238 | int64_t opal_int_get_xirr(uint32_t *out_xirr, bool just_poll); |
239 | int64_t opal_int_set_cppr(uint8_t cppr); | |
240 | int64_t opal_int_eoi(uint32_t xirr); | |
241 | int64_t opal_int_set_mfrr(uint32_t cpu, uint8_t mfrr); | |
69c592ed BH |
242 | int64_t opal_pci_tce_kill(uint64_t phb_id, uint32_t kill_type, |
243 | uint32_t pe_num, uint32_t tce_size, | |
244 | uint64_t dma_addr, uint32_t npages); | |
1d0761d2 | 245 | int64_t opal_nmmu_set_ptcr(uint64_t chip_id, uint64_t ptcr); |
eeea1a43 BH |
246 | int64_t opal_xive_reset(uint64_t version); |
247 | int64_t opal_xive_get_irq_info(uint32_t girq, | |
248 | __be64 *out_flags, | |
249 | __be64 *out_eoi_page, | |
250 | __be64 *out_trig_page, | |
251 | __be32 *out_esb_shift, | |
252 | __be32 *out_src_chip); | |
253 | int64_t opal_xive_get_irq_config(uint32_t girq, __be64 *out_vp, | |
254 | uint8_t *out_prio, __be32 *out_lirq); | |
255 | int64_t opal_xive_set_irq_config(uint32_t girq, uint64_t vp, uint8_t prio, | |
256 | uint32_t lirq); | |
257 | int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio, | |
258 | __be64 *out_qpage, | |
259 | __be64 *out_qsize, | |
260 | __be64 *out_qeoi_page, | |
261 | __be32 *out_escalate_irq, | |
262 | __be64 *out_qflags); | |
263 | int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio, | |
264 | uint64_t qpage, | |
265 | uint64_t qsize, | |
266 | uint64_t qflags); | |
267 | int64_t opal_xive_donate_page(uint32_t chip_id, uint64_t addr); | |
268 | int64_t opal_xive_alloc_vp_block(uint32_t alloc_order); | |
269 | int64_t opal_xive_free_vp_block(uint64_t vp); | |
270 | int64_t opal_xive_get_vp_info(uint64_t vp, | |
271 | __be64 *out_flags, | |
272 | __be64 *out_cam_value, | |
273 | __be64 *out_report_cl_pair, | |
274 | __be32 *out_chip_id); | |
275 | int64_t opal_xive_set_vp_info(uint64_t vp, | |
276 | uint64_t flags, | |
277 | uint64_t report_cl_pair); | |
278 | int64_t opal_xive_allocate_irq(uint32_t chip_id); | |
279 | int64_t opal_xive_free_irq(uint32_t girq); | |
280 | int64_t opal_xive_sync(uint32_t type, uint32_t id); | |
281 | int64_t opal_xive_dump(uint32_t type, uint32_t id); | |
25529100 FB |
282 | int64_t opal_pci_set_p2p(uint64_t phb_init, uint64_t phb_target, |
283 | uint64_t desc, uint16_t pe_number); | |
9fedd3f8 | 284 | |
28a5db00 MS |
285 | int64_t opal_imc_counters_init(uint32_t type, uint64_t address, |
286 | uint64_t cpu_pir); | |
287 | int64_t opal_imc_counters_start(uint32_t type, uint64_t cpu_pir); | |
288 | int64_t opal_imc_counters_stop(uint32_t type, uint64_t cpu_pir); | |
289 | ||
cb8b340d SB |
290 | int opal_get_powercap(u32 handle, int token, u32 *pcap); |
291 | int opal_set_powercap(u32 handle, int token, u32 pcap); | |
8e84b2d1 SB |
292 | int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr); |
293 | int opal_set_power_shift_ratio(u32 handle, int token, u32 psr); | |
bf957155 | 294 | int opal_sensor_group_clear(u32 group_hndl, int token); |
04baaf28 | 295 | int opal_sensor_group_enable(u32 group_hndl, int token, bool enable); |
656ecc16 | 296 | int opal_nx_coproc_init(uint32_t chip_id, uint32_t ct); |
cb8b340d | 297 | |
e36d0a2e | 298 | s64 opal_signal_system_reset(s32 cpu); |
ee03b9b4 | 299 | s64 opal_quiesce(u64 shutdown_type, s32 cpu); |
e36d0a2e | 300 | |
14a43e69 | 301 | /* Internal functions */ |
e2c8b93e AB |
302 | extern int early_init_dt_scan_opal(unsigned long node, const char *uname, |
303 | int depth, void *data); | |
55672ecf MS |
304 | extern int early_init_dt_scan_recoverable_ranges(unsigned long node, |
305 | const char *uname, int depth, void *data); | |
d3cbff1b | 306 | extern void opal_configure_cores(void); |
14a43e69 BH |
307 | |
308 | extern int opal_get_chars(uint32_t vtermno, char *buf, int count); | |
309 | extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len); | |
17cc1dd4 | 310 | extern int opal_put_chars_atomic(uint32_t vtermno, const char *buf, int total_len); |
95b861a7 | 311 | extern int opal_flush_chars(uint32_t vtermno, bool wait); |
d2a2262e | 312 | extern int opal_flush_console(uint32_t vtermno); |
14a43e69 BH |
313 | |
314 | extern void hvc_opal_init_early(void); | |
315 | ||
1bc98de2 | 316 | extern int opal_notifier_register(struct notifier_block *nb); |
798af00c BH |
317 | extern int opal_notifier_unregister(struct notifier_block *nb); |
318 | ||
d7cf83fc | 319 | extern int opal_message_notifier_register(enum opal_msg_type msg_type, |
24366360 | 320 | struct notifier_block *nb); |
df60f576 | 321 | extern int opal_message_notifier_unregister(enum opal_msg_type msg_type, |
b921e902 | 322 | struct notifier_block *nb); |
1bc98de2 GS |
323 | extern void opal_notifier_enable(void); |
324 | extern void opal_notifier_disable(void); | |
325 | extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val); | |
326 | ||
8d724823 | 327 | extern int opal_async_get_token_interruptible(void); |
8d724823 NG |
328 | extern int opal_async_release_token(int token); |
329 | extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg); | |
9aab2449 CB |
330 | extern int opal_async_wait_response_interruptible(uint64_t token, |
331 | struct opal_msg *msg); | |
7224adbb | 332 | extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data); |
5cdcb01e | 333 | extern int opal_get_sensor_data_u64(u32 sensor_hndl, u64 *sensor_data); |
04baaf28 | 334 | extern int sensor_group_enable(u32 grp_hndl, bool enable); |
8d724823 | 335 | |
628daa8d | 336 | struct rtc_time; |
5bfd6435 | 337 | extern time64_t opal_get_boot_time(void); |
628daa8d | 338 | extern void opal_nvram_init(void); |
ed59190e | 339 | extern void opal_flash_update_init(void); |
f2748bdf | 340 | extern void opal_flash_update_print_message(void); |
774fea1a | 341 | extern int opal_elog_init(void); |
c7e64b9c | 342 | extern void opal_platform_dump_init(void); |
4029cd66 | 343 | extern void opal_sys_param_init(void); |
bfc36894 | 344 | extern void opal_msglog_init(void); |
9b4fffa1 | 345 | extern void opal_msglog_sysfs_init(void); |
96e023e7 AP |
346 | extern int opal_async_comp_init(void); |
347 | extern int opal_sensor_init(void); | |
348 | extern int opal_hmi_handler_init(void); | |
9f0fd049 | 349 | extern int opal_event_init(void); |
08fb726d | 350 | int opal_power_control_init(void); |
628daa8d | 351 | |
ed79ba9e | 352 | extern int opal_machine_check(struct pt_regs *regs); |
55672ecf | 353 | extern bool opal_mce_check_early_recovery(struct pt_regs *regs); |
0869b6fd MS |
354 | extern int opal_hmi_exception_early(struct pt_regs *regs); |
355 | extern int opal_handle_hmi_exception(struct pt_regs *regs); | |
ed79ba9e | 356 | |
73ed148a | 357 | extern void opal_shutdown(void); |
97eb001f | 358 | extern int opal_resync_timebase(void); |
73ed148a | 359 | |
3fafe9c2 BH |
360 | extern void opal_lpc_init(void); |
361 | ||
affddff6 RC |
362 | extern void opal_kmsg_init(void); |
363 | ||
9f0fd049 AP |
364 | extern int opal_event_request(unsigned int opal_event_nr); |
365 | ||
3441f04b AB |
366 | struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr, |
367 | unsigned long vmalloc_size); | |
368 | void opal_free_sg_list(struct opal_sg_list *sg); | |
369 | ||
e3c5c2e0 CLG |
370 | extern int opal_error_code(int rc); |
371 | ||
9b4fffa1 AD |
372 | ssize_t opal_msglog_copy(char *to, loff_t pos, size_t count); |
373 | ||
d0226d31 SJS |
374 | static inline int opal_get_async_rc(struct opal_msg msg) |
375 | { | |
376 | if (msg.msg_type != OPAL_MSG_ASYNC_COMP) | |
377 | return OPAL_PARAMETER; | |
378 | else | |
379 | return be64_to_cpu(msg.params[1]); | |
380 | } | |
381 | ||
a203658b BH |
382 | void opal_wake_poller(void); |
383 | ||
cb8b340d | 384 | void opal_powercap_init(void); |
8e84b2d1 | 385 | void opal_psr_init(void); |
bf957155 | 386 | void opal_sensor_groups_init(void); |
cb8b340d | 387 | |
14a43e69 | 388 | #endif /* __ASSEMBLY__ */ |
27f44888 | 389 | |
d800ba12 | 390 | #endif /* _ASM_POWERPC_OPAL_H */ |