[linux-block.git] / arch / powerpc / include / asm / nohash / 32 / pgtable.h

#ifndef _ASM_POWERPC_NOHASH_32_PGTABLE_H
#define _ASM_POWERPC_NOHASH_32_PGTABLE_H

#include <asm-generic/pgtable-nopmd.h>

#ifndef __ASSEMBLY__
#include <linux/sched.h>
#include <linux/threads.h>
#include <asm/io.h>			/* For sub-arch specific PPC_PIN_SIZE */

extern unsigned long ioremap_bot;

#ifdef CONFIG_44x
extern int icache_44x_need_flush;
#endif

#endif /* __ASSEMBLY__ */

#define PTE_INDEX_SIZE	PTE_SHIFT
#define PMD_INDEX_SIZE	0
#define PUD_INDEX_SIZE	0
#define PGD_INDEX_SIZE	(32 - PGDIR_SHIFT)

#define PMD_CACHE_INDEX	PMD_INDEX_SIZE

#ifndef __ASSEMBLY__
#define PTE_TABLE_SIZE	(sizeof(pte_t) << PTE_INDEX_SIZE)
#define PMD_TABLE_SIZE	0
#define PUD_TABLE_SIZE	0
#define PGD_TABLE_SIZE	(sizeof(pgd_t) << PGD_INDEX_SIZE)
#endif	/* __ASSEMBLY__ */

#define PTRS_PER_PTE	(1 << PTE_INDEX_SIZE)
#define PTRS_PER_PGD	(1 << PGD_INDEX_SIZE)

/*
 * The normal case is that PTEs are 32-bits and we have a 1-page
 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages.  -- paulus
 *
 * For any >32-bit physical address platform, we can use the following
 * two level page table layout where the pgdir is 8KB and the MS 13 bits
 * are an index to the second level table.  The combined pgdir/pmd first
 * level has 2048 entries and the second level has 512 64-bit PTE entries.
 * -Matt
 */
/* PGDIR_SHIFT determines what a top-level page table entry can map */
#define PGDIR_SHIFT	(PAGE_SHIFT + PTE_INDEX_SIZE)
#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
#define PGDIR_MASK	(~(PGDIR_SIZE-1))

/* Bits to mask out from a PGD to get to the PUD page */
#define PGD_MASKED_BITS		0

#define USER_PTRS_PER_PGD	(TASK_SIZE / PGDIR_SIZE)
#define FIRST_USER_ADDRESS	0UL

#define pte_ERROR(e) \
	pr_err("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
		(unsigned long long)pte_val(e))
#define pgd_ERROR(e) \
	pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))

/*
 * This is the bottom of the PKMAP area with HIGHMEM or an arbitrary
 * value (for now) on others, from where we can start layout kernel
 * virtual space that goes below PKMAP and FIXMAP
 */
#ifdef CONFIG_HIGHMEM
#define KVIRT_TOP	PKMAP_BASE
#else
#define KVIRT_TOP	(0xfe000000UL)	/* for now, could be FIXMAP_BASE ? */
#endif

/*
 * ioremap_bot starts at that address. Early ioremaps move down from there,
 * until mem_init() at which point this becomes the top of the vmalloc
 * and ioremap space
 */
#ifdef CONFIG_NOT_COHERENT_CACHE
#define IOREMAP_TOP	((KVIRT_TOP - CONFIG_CONSISTENT_SIZE) & PAGE_MASK)
#else
#define IOREMAP_TOP	KVIRT_TOP
#endif

/*
 * Just any arbitrary offset to the start of the vmalloc VM area: the
 * current 16MB value just means that there will be a 64MB "hole" after the
 * physical memory until the kernel virtual memory starts.  That means that
 * any out-of-bounds memory accesses will hopefully be caught.
 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
 * area for the same reason. ;)
 *
 * We no longer map larger than phys RAM with the BATs so we don't have
 * to worry about the VMALLOC_OFFSET causing problems.  We do have to worry
 * about clashes between our early calls to ioremap() that start growing down
 * from IOREMAP_TOP being run into the VM area allocations (growing upwards
 * from VMALLOC_START).  For this reason we have ioremap_bot to check when
 * we actually run into our mappings setup in the early boot with the VM
 * system.  This really does become a problem for machines with good amounts
 * of RAM.  -- Cort
 */
#define VMALLOC_OFFSET (0x1000000) /* 16M */
#ifdef PPC_PIN_SIZE
#define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
#else
#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
#endif
#define VMALLOC_END	ioremap_bot

/*
 * Bits in a linux-style PTE.  These match the bits in the
 * (hardware-defined) PowerPC PTE as closely as possible.
 */

#if defined(CONFIG_40x)
#include <asm/nohash/32/pte-40x.h>
#elif defined(CONFIG_44x)
#include <asm/nohash/32/pte-44x.h>
#elif defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
#include <asm/nohash/pte-book3e.h>
#elif defined(CONFIG_FSL_BOOKE)
#include <asm/nohash/32/pte-fsl-booke.h>
#elif defined(CONFIG_8xx)
#include <asm/nohash/32/pte-8xx.h>
#endif

/* And here we include common definitions */
#include <asm/pte-common.h>

#ifndef __ASSEMBLY__

#define pte_clear(mm, addr, ptep) \
	do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)

#define pmd_none(pmd)		(!pmd_val(pmd))
#define	pmd_bad(pmd)		(pmd_val(pmd) & _PMD_BAD)
#define	pmd_present(pmd)	(pmd_val(pmd) & _PMD_PRESENT_MASK)
static inline void pmd_clear(pmd_t *pmdp)
{
	*pmdp = __pmd(0);
}


/*
 * When flushing the tlb entry for a page, we also need to flush the hash
 * table entry.  flush_hash_pages is assembler (for speed) in hashtable.S.
 */
extern int flush_hash_pages(unsigned context, unsigned long va,
			    unsigned long pmdval, int count);

/* Add an HPTE to the hash table */
extern void add_hash_page(unsigned context, unsigned long va,
			  unsigned long pmdval);

/* Flush an entry from the TLB/hash table */
extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
			     unsigned long address);

/*
 * PTE updates. This function is called whenever an existing
 * valid PTE is updated. This does -not- include set_pte_at()
 * which nowadays only sets a new PTE.
 *
 * Depending on the type of MMU, we may need to use atomic updates
 * and the PTE may be either 32 or 64 bit wide. In the later case,
 * when using atomic updates, only the low part of the PTE is
 * accessed atomically.
 *
 * In addition, on 44x, we also maintain a global flag indicating
 * that an executable user mapping was modified, which is needed
 * to properly flush the virtually tagged instruction cache of
 * those implementations.
 */
#ifndef CONFIG_PTE_64BIT
static inline unsigned long pte_update(pte_t *p,
				       unsigned long clr,
				       unsigned long set)
{
#ifdef PTE_ATOMIC_UPDATES
	unsigned long old, tmp;

	__asm__ __volatile__("\
1:	lwarx	%0,0,%3\n\
	andc	%1,%0,%4\n\
	or	%1,%1,%5\n"
	PPC405_ERR77(0,%3)
"	stwcx.	%1,0,%3\n\
	bne-	1b"
	: "=&r" (old), "=&r" (tmp), "=m" (*p)
	: "r" (p), "r" (clr), "r" (set), "m" (*p)
	: "cc" );
#else /* PTE_ATOMIC_UPDATES */
	unsigned long old = pte_val(*p);
	*p = __pte((old & ~clr) | set);
#endif /* !PTE_ATOMIC_UPDATES */

#ifdef CONFIG_44x
	if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
		icache_44x_need_flush = 1;
#endif
	return old;
}
#else /* CONFIG_PTE_64BIT */
static inline unsigned long long pte_update(pte_t *p,
					    unsigned long clr,
					    unsigned long set)
{
#ifdef PTE_ATOMIC_UPDATES
	unsigned long long old;
	unsigned long tmp;

	__asm__ __volatile__("\
1:	lwarx	%L0,0,%4\n\
	lwzx	%0,0,%3\n\
	andc	%1,%L0,%5\n\
	or	%1,%1,%6\n"
	PPC405_ERR77(0,%3)
"	stwcx.	%1,0,%4\n\
	bne-	1b"
	: "=&r" (old), "=&r" (tmp), "=m" (*p)
	: "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
	: "cc" );
#else /* PTE_ATOMIC_UPDATES */
	unsigned long long old = pte_val(*p);
	*p = __pte((old & ~(unsigned long long)clr) | set);
#endif /* !PTE_ATOMIC_UPDATES */

#ifdef CONFIG_44x
	if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
		icache_44x_need_flush = 1;
#endif
	return old;
}
#endif /* CONFIG_PTE_64BIT */

/*
 * 2.6 calls this without flushing the TLB entry; this is wrong
 * for our hash-based implementation, we fix that up here.
 */
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
{
	unsigned long old;
	old = pte_update(ptep, _PAGE_ACCESSED, 0);
#if _PAGE_HASHPTE != 0
	if (old & _PAGE_HASHPTE) {
		unsigned long ptephys = __pa(ptep) & PAGE_MASK;
		flush_hash_pages(context, addr, ptephys, 1);
	}
#endif
	return (old & _PAGE_ACCESSED) != 0;
}
#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
	__ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)

#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
				       pte_t *ptep)
{
	return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
}

#define __HAVE_ARCH_PTEP_SET_WRPROTECT
static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
				      pte_t *ptep)
{
	pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), _PAGE_RO);
}
static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
					   unsigned long addr, pte_t *ptep)
{
	ptep_set_wrprotect(mm, addr, ptep);
}


static inline void __ptep_set_access_flags(struct mm_struct *mm,
					   pte_t *ptep, pte_t entry,
					   unsigned long address)
{
	unsigned long set = pte_val(entry) &
		(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
	unsigned long clr = ~pte_val(entry) & _PAGE_RO;

	pte_update(ptep, clr, set);
}

#define __HAVE_ARCH_PTE_SAME
#define pte_same(A,B)	(((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)

/*
 * Note that on Book E processors, the pmd contains the kernel virtual
 * (lowmem) address of the pte page.  The physical address is less useful
 * because everything runs with translation enabled (even the TLB miss
 * handler).  On everything else the pmd contains the physical address
 * of the pte page.  -- paulus
 */
#ifndef CONFIG_BOOKE
#define pmd_page_vaddr(pmd)	\
	((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
#define pmd_page(pmd)		\
	pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
#else
#define pmd_page_vaddr(pmd)	\
	((unsigned long) (pmd_val(pmd) & PAGE_MASK))
#define pmd_page(pmd)		\
	pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT))
#endif

/* to find an entry in a kernel page-table-directory */
#define pgd_offset_k(address) pgd_offset(&init_mm, address)

/* to find an entry in a page-table-directory */
#define pgd_index(address)	 ((address) >> PGDIR_SHIFT)
#define pgd_offset(mm, address)	 ((mm)->pgd + pgd_index(address))

/* Find an entry in the third-level page table.. */
#define pte_index(address)		\
	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
#define pte_offset_kernel(dir, addr)	\
	(pmd_bad(*(dir)) ? NULL : (pte_t *)pmd_page_vaddr(*(dir)) + \
				  pte_index(addr))
#define pte_offset_map(dir, addr)		\
	((pte_t *) kmap_atomic(pmd_page(*(dir))) + pte_index(addr))
#define pte_unmap(pte)		kunmap_atomic(pte)

/*
 * Encode and decode a swap entry.
 * Note that the bits we use in a PTE for representing a swap entry
 * must not include the _PAGE_PRESENT bit or the _PAGE_HASHPTE bit (if used).
 *   -- paulus
 */
#define __swp_type(entry)		((entry).val & 0x1f)
#define __swp_offset(entry)		((entry).val >> 5)
#define __swp_entry(type, offset)	((swp_entry_t) { (type) | ((offset) << 5) })
#define __pte_to_swp_entry(pte)		((swp_entry_t) { pte_val(pte) >> 3 })
#define __swp_entry_to_pte(x)		((pte_t) { (x).val << 3 })

extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
		      pmd_t **pmdp);

#endif /* !__ASSEMBLY__ */

#endif /* __ASM_POWERPC_NOHASH_32_PGTABLE_H */
Commit	Line	Data
17ed9e31 AK	1	#ifndef _ASM_POWERPC_NOHASH_32_PGTABLE_H
17ed9e31 AK	2	#define _ASM_POWERPC_NOHASH_32_PGTABLE_H
f88df14b	3
d1953c88	4	#include <asm-generic/pgtable-nopmd.h>
f88df14b DG	5
	6	#ifndef __ASSEMBLY__
	7	#include <linux/sched.h>
	8	#include <linux/threads.h>
f88df14b	9	#include <asm/io.h> /* For sub-arch specific PPC_PIN_SIZE */
f88df14b	10
f637a49e	11	extern unsigned long ioremap_bot;
b98ac05d BH	12
	13	#ifdef CONFIG_44x
	14	extern int icache_44x_need_flush;
	15	#endif
	16
f88df14b DG	17	#endif /* __ASSEMBLY__ */
f88df14b DG	18
9b081e10 CL	19	#define PTE_INDEX_SIZE PTE_SHIFT
	20	#define PMD_INDEX_SIZE 0
	21	#define PUD_INDEX_SIZE 0
	22	#define PGD_INDEX_SIZE (32 - PGDIR_SHIFT)
	23
	24	#define PMD_CACHE_INDEX PMD_INDEX_SIZE
	25
	26	#ifndef __ASSEMBLY__
	27	#define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE)
	28	#define PMD_TABLE_SIZE 0
	29	#define PUD_TABLE_SIZE 0
	30	#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
	31	#endif /* __ASSEMBLY__ */
	32
	33	#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
	34	#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
	35
f88df14b DG	36	/*
	37	* The normal case is that PTEs are 32-bits and we have a 1-page
	38	* 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
	39	*
	40	* For any >32-bit physical address platform, we can use the following
	41	* two level page table layout where the pgdir is 8KB and the MS 13 bits
	42	* are an index to the second level table. The combined pgdir/pmd first
	43	* level has 2048 entries and the second level has 512 64-bit PTE entries.
	44	* -Matt
	45	*/
f88df14b	46	/* PGDIR_SHIFT determines what a top-level page table entry can map */
9b081e10	47	#define PGDIR_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
f88df14b DG	48	#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
	49	#define PGDIR_MASK (~(PGDIR_SIZE-1))
	50
9b081e10 CL	51	/* Bits to mask out from a PGD to get to the PUD page */
9b081e10 CL	52	#define PGD_MASKED_BITS 0
f88df14b DG	53
f88df14b DG	54	#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
d016bf7e	55	#define FIRST_USER_ADDRESS 0UL
f88df14b	56
f88df14b	57	#define pte_ERROR(e) \
a7696b36	58	pr_err("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
0aeafb0c	59	(unsigned long long)pte_val(e))
f88df14b	60	#define pgd_ERROR(e) \
a7696b36	61	pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
f88df14b	62
f637a49e BH	63	/*
	64	* This is the bottom of the PKMAP area with HIGHMEM or an arbitrary
	65	* value (for now) on others, from where we can start layout kernel
	66	* virtual space that goes below PKMAP and FIXMAP
	67	*/
	68	#ifdef CONFIG_HIGHMEM
	69	#define KVIRT_TOP PKMAP_BASE
	70	#else
	71	#define KVIRT_TOP (0xfe000000UL) /* for now, could be FIXMAP_BASE ? */
	72	#endif
	73
	74	/*
	75	* ioremap_bot starts at that address. Early ioremaps move down from there,
	76	* until mem_init() at which point this becomes the top of the vmalloc
	77	* and ioremap space
	78	*/
8b31e49d BH	79	#ifdef CONFIG_NOT_COHERENT_CACHE
	80	#define IOREMAP_TOP ((KVIRT_TOP - CONFIG_CONSISTENT_SIZE) & PAGE_MASK)
	81	#else
f637a49e	82	#define IOREMAP_TOP KVIRT_TOP
8b31e49d	83	#endif
f637a49e	84
f88df14b DG	85	/*
f88df14b DG	86	* Just any arbitrary offset to the start of the vmalloc VM area: the
f637a49e	87	* current 16MB value just means that there will be a 64MB "hole" after the
f88df14b DG	88	* physical memory until the kernel virtual memory starts. That means that
	89	* any out-of-bounds memory accesses will hopefully be caught.
	90	* The vmalloc() routines leaves a hole of 4kB between each vmalloced
	91	* area for the same reason. ;)
	92	*
	93	* We no longer map larger than phys RAM with the BATs so we don't have
	94	* to worry about the VMALLOC_OFFSET causing problems. We do have to worry
	95	* about clashes between our early calls to ioremap() that start growing down
e974cd4b	96	* from IOREMAP_TOP being run into the VM area allocations (growing upwards
f88df14b DG	97	* from VMALLOC_START). For this reason we have ioremap_bot to check when
	98	* we actually run into our mappings setup in the early boot with the VM
	99	* system. This really does become a problem for machines with good amounts
	100	* of RAM. -- Cort
	101	*/
	102	#define VMALLOC_OFFSET (0x1000000) /* 16M */
	103	#ifdef PPC_PIN_SIZE
	104	#define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
	105	#else
	106	#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
	107	#endif
	108	#define VMALLOC_END ioremap_bot
	109
	110	/*
	111	* Bits in a linux-style PTE. These match the bits in the
	112	* (hardware-defined) PowerPC PTE as closely as possible.
	113	*/
	114
	115	#if defined(CONFIG_40x)
17ed9e31	116	#include <asm/nohash/32/pte-40x.h>
f88df14b	117	#elif defined(CONFIG_44x)
17ed9e31	118	#include <asm/nohash/32/pte-44x.h>
76acc2c1	119	#elif defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
17ed9e31	120	#include <asm/nohash/pte-book3e.h>
f88df14b	121	#elif defined(CONFIG_FSL_BOOKE)
17ed9e31	122	#include <asm/nohash/32/pte-fsl-booke.h>
f88df14b	123	#elif defined(CONFIG_8xx)
17ed9e31	124	#include <asm/nohash/32/pte-8xx.h>
4ee7084e	125	#endif
f88df14b	126
71087002 BH	127	/* And here we include common definitions */
71087002 BH	128	#include <asm/pte-common.h>
f88df14b DG	129
f88df14b DG	130	#ifndef __ASSEMBLY__
f88df14b	131
9bf2b5cd KG	132	#define pte_clear(mm, addr, ptep) \
9bf2b5cd KG	133	do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
f88df14b DG	134
	135	#define pmd_none(pmd) (!pmd_val(pmd))
	136	#define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD)
	137	#define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK)
f281b5d5 AK	138	static inline void pmd_clear(pmd_t *pmdp)
	139	{
	140	*pmdp = __pmd(0);
	141	}
	142
	143
f88df14b	144
f88df14b DG	145	/*
	146	* When flushing the tlb entry for a page, we also need to flush the hash
	147	* table entry. flush_hash_pages is assembler (for speed) in hashtable.S.
	148	*/
	149	extern int flush_hash_pages(unsigned context, unsigned long va,
	150	unsigned long pmdval, int count);
	151
	152	/* Add an HPTE to the hash table */
	153	extern void add_hash_page(unsigned context, unsigned long va,
	154	unsigned long pmdval);
	155
4ee7084e BB	156	/* Flush an entry from the TLB/hash table */
	157	extern void flush_hash_entry(struct mm_struct mm, pte_t ptep,
	158	unsigned long address);
	159
f88df14b	160	/*
c605782b BH	161	* PTE updates. This function is called whenever an existing
	162	* valid PTE is updated. This does -not- include set_pte_at()
	163	* which nowadays only sets a new PTE.
	164	*
	165	* Depending on the type of MMU, we may need to use atomic updates
	166	* and the PTE may be either 32 or 64 bit wide. In the later case,
	167	* when using atomic updates, only the low part of the PTE is
	168	* accessed atomically.
f88df14b	169	*
c605782b BH	170	* In addition, on 44x, we also maintain a global flag indicating
	171	* that an executable user mapping was modified, which is needed
	172	* to properly flush the virtually tagged instruction cache of
	173	* those implementations.
f88df14b DG	174	*/
f88df14b DG	175	#ifndef CONFIG_PTE_64BIT
1bc54c03 BH	176	static inline unsigned long pte_update(pte_t *p,
1bc54c03 BH	177	unsigned long clr,
f88df14b DG	178	unsigned long set)
f88df14b DG	179	{
1bc54c03	180	#ifdef PTE_ATOMIC_UPDATES
f88df14b DG	181	unsigned long old, tmp;
	182
	183	__asm__ __volatile__("\
	184	1: lwarx %0,0,%3\n\
	185	andc %1,%0,%4\n\
	186	or %1,%1,%5\n"
	187	PPC405_ERR77(0,%3)
	188	" stwcx. %1,0,%3\n\
	189	bne- 1b"
	190	: "=&r" (old), "=&r" (tmp), "=m" (*p)
	191	: "r" (p), "r" (clr), "r" (set), "m" (*p)
	192	: "cc" );
1bc54c03 BH	193	#else /* PTE_ATOMIC_UPDATES */
	194	unsigned long old = pte_val(*p);
	195	*p = __pte((old & ~clr) \| set);
	196	#endif /* !PTE_ATOMIC_UPDATES */
	197
b98ac05d	198	#ifdef CONFIG_44x
ea3cc330	199	if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
b98ac05d BH	200	icache_44x_need_flush = 1;
b98ac05d BH	201	#endif
f88df14b DG	202	return old;
f88df14b DG	203	}
1bc54c03	204	#else /* CONFIG_PTE_64BIT */
1bc54c03 BH	205	static inline unsigned long long pte_update(pte_t *p,
	206	unsigned long clr,
	207	unsigned long set)
f88df14b	208	{
1bc54c03	209	#ifdef PTE_ATOMIC_UPDATES
f88df14b DG	210	unsigned long long old;
	211	unsigned long tmp;
	212
	213	__asm__ __volatile__("\
	214	1: lwarx %L0,0,%4\n\
	215	lwzx %0,0,%3\n\
	216	andc %1,%L0,%5\n\
	217	or %1,%1,%6\n"
	218	PPC405_ERR77(0,%3)
	219	" stwcx. %1,0,%4\n\
	220	bne- 1b"
	221	: "=&r" (old), "=&r" (tmp), "=m" (*p)
	222	: "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
	223	: "cc" );
1bc54c03 BH	224	#else /* PTE_ATOMIC_UPDATES */
1bc54c03 BH	225	unsigned long long old = pte_val(*p);
585583d9	226	*p = __pte((old & ~(unsigned long long)clr) \| set);
1bc54c03 BH	227	#endif /* !PTE_ATOMIC_UPDATES */
1bc54c03 BH	228
b98ac05d	229	#ifdef CONFIG_44x
ea3cc330	230	if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
b98ac05d BH	231	icache_44x_need_flush = 1;
b98ac05d BH	232	#endif
f88df14b DG	233	return old;
f88df14b DG	234	}
1bc54c03	235	#endif /* CONFIG_PTE_64BIT */
f88df14b	236
f88df14b	237	/*
bf2737f7 BB	238	* 2.6 calls this without flushing the TLB entry; this is wrong
bf2737f7 BB	239	* for our hash-based implementation, we fix that up here.
f88df14b DG	240	*/
	241	#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
	242	static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
	243	{
	244	unsigned long old;
	245	old = pte_update(ptep, _PAGE_ACCESSED, 0);
	246	#if _PAGE_HASHPTE != 0
	247	if (old & _PAGE_HASHPTE) {
	248	unsigned long ptephys = __pa(ptep) & PAGE_MASK;
	249	flush_hash_pages(context, addr, ptephys, 1);
	250	}
	251	#endif
	252	return (old & _PAGE_ACCESSED) != 0;
	253	}
	254	#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
	255	__ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
	256
f88df14b DG	257	#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
	258	static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
	259	pte_t *ptep)
	260	{
	261	return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
	262	}
	263
	264	#define __HAVE_ARCH_PTEP_SET_WRPROTECT
	265	static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
	266	pte_t *ptep)
	267	{
a7b9f671	268	pte_update(ptep, (_PAGE_RW \| _PAGE_HWWRITE), _PAGE_RO);
f88df14b	269	}
016b33c4 AW	270	static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
	271	unsigned long addr, pte_t *ptep)
	272	{
	273	ptep_set_wrprotect(mm, addr, ptep);
	274	}
	275
f88df14b	276
c6d1a767	277	static inline void __ptep_set_access_flags(struct mm_struct *mm,
b3603e17 AK	278	pte_t *ptep, pte_t entry,
b3603e17 AK	279	unsigned long address)
f88df14b	280	{
a7b9f671	281	unsigned long set = pte_val(entry) &
ea3cc330	282	(_PAGE_DIRTY \| _PAGE_ACCESSED \| _PAGE_RW \| _PAGE_EXEC);
a7b9f671 LC	283	unsigned long clr = ~pte_val(entry) & _PAGE_RO;
	284
	285	pte_update(ptep, clr, set);
f88df14b DG	286	}
f88df14b DG	287
f88df14b DG	288	#define __HAVE_ARCH_PTE_SAME
	289	#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
	290
	291	/*
	292	* Note that on Book E processors, the pmd contains the kernel virtual
	293	* (lowmem) address of the pte page. The physical address is less useful
	294	* because everything runs with translation enabled (even the TLB miss
	295	* handler). On everything else the pmd contains the physical address
	296	* of the pte page. -- paulus
	297	*/
	298	#ifndef CONFIG_BOOKE
	299	#define pmd_page_vaddr(pmd) \
	300	((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
	301	#define pmd_page(pmd) \
43b5fefc	302	pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
f88df14b DG	303	#else
	304	#define pmd_page_vaddr(pmd) \
	305	((unsigned long) (pmd_val(pmd) & PAGE_MASK))
	306	#define pmd_page(pmd) \
af892e0f	307	pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT))
f88df14b DG	308	#endif
	309
	310	/* to find an entry in a kernel page-table-directory */
	311	#define pgd_offset_k(address) pgd_offset(&init_mm, address)
	312
	313	/* to find an entry in a page-table-directory */
	314	#define pgd_index(address) ((address) >> PGDIR_SHIFT)
	315	#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
	316
f88df14b DG	317	/* Find an entry in the third-level page table.. */
	318	#define pte_index(address) \
	319	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
	320	#define pte_offset_kernel(dir, addr) \
be00ed72 CL	321	(pmd_bad((dir)) ? NULL : (pte_t )pmd_page_vaddr(*(dir)) + \
be00ed72 CL	322	pte_index(addr))
f88df14b	323	#define pte_offset_map(dir, addr) \
ece0e2b6 PZ	324	((pte_t ) kmap_atomic(pmd_page((dir))) + pte_index(addr))
ece0e2b6 PZ	325	#define pte_unmap(pte) kunmap_atomic(pte)
f88df14b	326
f88df14b DG	327	/*
	328	* Encode and decode a swap entry.
	329	* Note that the bits we use in a PTE for representing a swap entry
780fc564 KS	330	* must not include the _PAGE_PRESENT bit or the _PAGE_HASHPTE bit (if used).
780fc564 KS	331	* -- paulus
f88df14b DG	332	*/
	333	#define __swp_type(entry) ((entry).val & 0x1f)
	334	#define __swp_offset(entry) ((entry).val >> 5)
	335	#define __swp_entry(type, offset) ((swp_entry_t) { (type) \| ((offset) << 5) })
	336	#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 })
	337	#define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 })
	338
f88df14b DG	339	extern int get_pteptr(struct mm_struct mm, unsigned long addr, pte_t *ptep,
	340	pmd_t **pmdp);
	341
	342	#endif /* !__ASSEMBLY__ */
	343
17ed9e31	344	#endif /* __ASM_POWERPC_NOHASH_32_PGTABLE_H */