[linux-2.6-block.git] / arch / powerpc / include / asm / mpic.h

#ifndef _ASM_POWERPC_MPIC_H
#define _ASM_POWERPC_MPIC_H
#ifdef __KERNEL__

#include <linux/irq.h>
#include <asm/dcr.h>
#include <asm/msi_bitmap.h>

/*
 * Global registers
 */

#define MPIC_GREG_BASE			0x01000

#define MPIC_GREG_FEATURE_0		0x00000
#define		MPIC_GREG_FEATURE_LAST_SRC_MASK		0x07ff0000
#define		MPIC_GREG_FEATURE_LAST_SRC_SHIFT	16
#define		MPIC_GREG_FEATURE_LAST_CPU_MASK		0x00001f00
#define		MPIC_GREG_FEATURE_LAST_CPU_SHIFT	8
#define		MPIC_GREG_FEATURE_VERSION_MASK		0xff
#define MPIC_GREG_FEATURE_1		0x00010
#define MPIC_GREG_GLOBAL_CONF_0		0x00020
#define		MPIC_GREG_GCONF_RESET			0x80000000
/* On the FSL mpic implementations the Mode field is expand to be
 * 2 bits wide:
 *	0b00 = pass through (interrupts routed to IRQ0)
 *	0b01 = Mixed mode
 *	0b10 = reserved
 *	0b11 = External proxy / coreint
 */
#define		MPIC_GREG_GCONF_COREINT			0x60000000
#define		MPIC_GREG_GCONF_8259_PTHROU_DIS		0x20000000
#define		MPIC_GREG_GCONF_NO_BIAS			0x10000000
#define		MPIC_GREG_GCONF_BASE_MASK		0x000fffff
#define		MPIC_GREG_GCONF_MCK			0x08000000
#define MPIC_GREG_GLOBAL_CONF_1		0x00030
#define MPIC_GREG_VENDOR_0		0x00040
#define MPIC_GREG_VENDOR_1		0x00050
#define MPIC_GREG_VENDOR_2		0x00060
#define MPIC_GREG_VENDOR_3		0x00070
#define MPIC_GREG_VENDOR_ID		0x00080
#define 	MPIC_GREG_VENDOR_ID_STEPPING_MASK	0x00ff0000
#define 	MPIC_GREG_VENDOR_ID_STEPPING_SHIFT	16
#define 	MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK	0x0000ff00
#define 	MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT	8
#define 	MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK	0x000000ff
#define MPIC_GREG_PROCESSOR_INIT	0x00090
#define MPIC_GREG_IPI_VECTOR_PRI_0	0x000a0
#define MPIC_GREG_IPI_VECTOR_PRI_1	0x000b0
#define MPIC_GREG_IPI_VECTOR_PRI_2	0x000c0
#define MPIC_GREG_IPI_VECTOR_PRI_3	0x000d0
#define MPIC_GREG_IPI_STRIDE		0x10
#define MPIC_GREG_SPURIOUS		0x000e0
#define MPIC_GREG_TIMER_FREQ		0x000f0

/*
 *
 * Timer registers
 */
#define MPIC_TIMER_BASE			0x01100
#define MPIC_TIMER_STRIDE		0x40
#define MPIC_TIMER_GROUP_STRIDE		0x1000

#define MPIC_TIMER_CURRENT_CNT		0x00000
#define MPIC_TIMER_BASE_CNT		0x00010
#define MPIC_TIMER_VECTOR_PRI		0x00020
#define MPIC_TIMER_DESTINATION		0x00030

/*
 * Per-Processor registers
 */

#define MPIC_CPU_THISBASE		0x00000
#define MPIC_CPU_BASE			0x20000
#define MPIC_CPU_STRIDE			0x01000

#define MPIC_CPU_IPI_DISPATCH_0		0x00040
#define MPIC_CPU_IPI_DISPATCH_1		0x00050
#define MPIC_CPU_IPI_DISPATCH_2		0x00060
#define MPIC_CPU_IPI_DISPATCH_3		0x00070
#define MPIC_CPU_IPI_DISPATCH_STRIDE	0x00010
#define MPIC_CPU_CURRENT_TASK_PRI	0x00080
#define 	MPIC_CPU_TASKPRI_MASK			0x0000000f
#define MPIC_CPU_WHOAMI			0x00090
#define 	MPIC_CPU_WHOAMI_MASK			0x0000001f
#define MPIC_CPU_INTACK			0x000a0
#define MPIC_CPU_EOI			0x000b0
#define MPIC_CPU_MCACK			0x000c0

/*
 * Per-source registers
 */

#define MPIC_IRQ_BASE			0x10000
#define MPIC_IRQ_STRIDE			0x00020
#define MPIC_IRQ_VECTOR_PRI		0x00000
#define 	MPIC_VECPRI_MASK			0x80000000
#define 	MPIC_VECPRI_ACTIVITY			0x40000000	/* Read Only */
#define 	MPIC_VECPRI_PRIORITY_MASK		0x000f0000
#define 	MPIC_VECPRI_PRIORITY_SHIFT		16
#define 	MPIC_VECPRI_VECTOR_MASK			0x000007ff
#define 	MPIC_VECPRI_POLARITY_POSITIVE		0x00800000
#define 	MPIC_VECPRI_POLARITY_NEGATIVE		0x00000000
#define 	MPIC_VECPRI_POLARITY_MASK		0x00800000
#define 	MPIC_VECPRI_SENSE_LEVEL			0x00400000
#define 	MPIC_VECPRI_SENSE_EDGE			0x00000000
#define 	MPIC_VECPRI_SENSE_MASK			0x00400000
#define MPIC_IRQ_DESTINATION		0x00010

#define MPIC_FSL_BRR1			0x00000
#define 	MPIC_FSL_BRR1_VER			0x0000ffff

#define MPIC_MAX_IRQ_SOURCES	2048
#define MPIC_MAX_CPUS		32
#define MPIC_MAX_ISU		32

#define MPIC_MAX_ERR      32
#define MPIC_FSL_ERR_INT  16

/*
 * Tsi108 implementation of MPIC has many differences from the original one
 */

/*
 * Global registers
 */

#define TSI108_GREG_BASE		0x00000
#define TSI108_GREG_FEATURE_0		0x00000
#define TSI108_GREG_GLOBAL_CONF_0	0x00004
#define TSI108_GREG_VENDOR_ID		0x0000c
#define TSI108_GREG_IPI_VECTOR_PRI_0	0x00204		/* Doorbell 0 */
#define TSI108_GREG_IPI_STRIDE		0x0c
#define TSI108_GREG_SPURIOUS		0x00010
#define TSI108_GREG_TIMER_FREQ		0x00014

/*
 * Timer registers
 */
#define TSI108_TIMER_BASE		0x0030
#define TSI108_TIMER_STRIDE		0x10
#define TSI108_TIMER_CURRENT_CNT	0x00000
#define TSI108_TIMER_BASE_CNT		0x00004
#define TSI108_TIMER_VECTOR_PRI		0x00008
#define TSI108_TIMER_DESTINATION	0x0000c

/*
 * Per-Processor registers
 */
#define TSI108_CPU_BASE			0x00300
#define TSI108_CPU_STRIDE		0x00040
#define TSI108_CPU_IPI_DISPATCH_0	0x00200
#define TSI108_CPU_IPI_DISPATCH_STRIDE	0x00000
#define TSI108_CPU_CURRENT_TASK_PRI	0x00000
#define TSI108_CPU_WHOAMI		0xffffffff
#define TSI108_CPU_INTACK		0x00004
#define TSI108_CPU_EOI			0x00008
#define TSI108_CPU_MCACK		0x00004 /* Doesn't really exist here */

/*
 * Per-source registers
 */
#define TSI108_IRQ_BASE			0x00100
#define TSI108_IRQ_STRIDE		0x00008
#define TSI108_IRQ_VECTOR_PRI		0x00000
#define TSI108_VECPRI_VECTOR_MASK	0x000000ff
#define TSI108_VECPRI_POLARITY_POSITIVE	0x01000000
#define TSI108_VECPRI_POLARITY_NEGATIVE	0x00000000
#define TSI108_VECPRI_SENSE_LEVEL	0x02000000
#define TSI108_VECPRI_SENSE_EDGE	0x00000000
#define TSI108_VECPRI_POLARITY_MASK	0x01000000
#define TSI108_VECPRI_SENSE_MASK	0x02000000
#define TSI108_IRQ_DESTINATION		0x00004

/* weird mpic register indices and mask bits in the HW info array */
enum {
	MPIC_IDX_GREG_BASE = 0,
	MPIC_IDX_GREG_FEATURE_0,
	MPIC_IDX_GREG_GLOBAL_CONF_0,
	MPIC_IDX_GREG_VENDOR_ID,
	MPIC_IDX_GREG_IPI_VECTOR_PRI_0,
	MPIC_IDX_GREG_IPI_STRIDE,
	MPIC_IDX_GREG_SPURIOUS,
	MPIC_IDX_GREG_TIMER_FREQ,

	MPIC_IDX_TIMER_BASE,
	MPIC_IDX_TIMER_STRIDE,
	MPIC_IDX_TIMER_CURRENT_CNT,
	MPIC_IDX_TIMER_BASE_CNT,
	MPIC_IDX_TIMER_VECTOR_PRI,
	MPIC_IDX_TIMER_DESTINATION,

	MPIC_IDX_CPU_BASE,
	MPIC_IDX_CPU_STRIDE,
	MPIC_IDX_CPU_IPI_DISPATCH_0,
	MPIC_IDX_CPU_IPI_DISPATCH_STRIDE,
	MPIC_IDX_CPU_CURRENT_TASK_PRI,
	MPIC_IDX_CPU_WHOAMI,
	MPIC_IDX_CPU_INTACK,
	MPIC_IDX_CPU_EOI,
	MPIC_IDX_CPU_MCACK,

	MPIC_IDX_IRQ_BASE,
	MPIC_IDX_IRQ_STRIDE,
	MPIC_IDX_IRQ_VECTOR_PRI,

	MPIC_IDX_VECPRI_VECTOR_MASK,
	MPIC_IDX_VECPRI_POLARITY_POSITIVE,
	MPIC_IDX_VECPRI_POLARITY_NEGATIVE,
	MPIC_IDX_VECPRI_SENSE_LEVEL,
	MPIC_IDX_VECPRI_SENSE_EDGE,
	MPIC_IDX_VECPRI_POLARITY_MASK,
	MPIC_IDX_VECPRI_SENSE_MASK,
	MPIC_IDX_IRQ_DESTINATION,
	MPIC_IDX_END
};


#ifdef CONFIG_MPIC_U3_HT_IRQS
/* Fixup table entry */
struct mpic_irq_fixup
{
	u8 __iomem	*base;
	u8 __iomem	*applebase;
	u32		data;
	unsigned int	index;
};
#endif /* CONFIG_MPIC_U3_HT_IRQS */


enum mpic_reg_type {
	mpic_access_mmio_le,
	mpic_access_mmio_be,
#ifdef CONFIG_PPC_DCR
	mpic_access_dcr
#endif
};

struct mpic_reg_bank {
	u32 __iomem	*base;
#ifdef CONFIG_PPC_DCR
	dcr_host_t	dhost;
#endif /* CONFIG_PPC_DCR */
};

struct mpic_irq_save {
	u32		vecprio,
			dest;
#ifdef CONFIG_MPIC_U3_HT_IRQS
	u32		fixup_data;
#endif
};

/* The instance data of a given MPIC */
struct mpic
{
	/* The OpenFirmware dt node for this MPIC */
	struct device_node *node;

	/* The remapper for this MPIC */
	struct irq_domain	*irqhost;

	/* The "linux" controller struct */
	struct irq_chip		hc_irq;
#ifdef CONFIG_MPIC_U3_HT_IRQS
	struct irq_chip		hc_ht_irq;
#endif
#ifdef CONFIG_SMP
	struct irq_chip		hc_ipi;
#endif
	struct irq_chip		hc_tm;
	struct irq_chip		hc_err;
	const char		*name;
	/* Flags */
	unsigned int		flags;
	/* How many irq sources in a given ISU */
	unsigned int		isu_size;
	unsigned int		isu_shift;
	unsigned int		isu_mask;
	/* Number of sources */
	unsigned int		num_sources;

	/* vector numbers used for internal sources (ipi/timers) */
	unsigned int		ipi_vecs[4];
	unsigned int		timer_vecs[8];
	/* vector numbers used for FSL MPIC error interrupts */
	unsigned int		err_int_vecs[MPIC_MAX_ERR];

	/* Spurious vector to program into unused sources */
	unsigned int		spurious_vec;

#ifdef CONFIG_MPIC_U3_HT_IRQS
	/* The fixup table */
	struct mpic_irq_fixup	*fixups;
	raw_spinlock_t	fixup_lock;
#endif

	/* Register access method */
	enum mpic_reg_type	reg_type;

	/* The physical base address of the MPIC */
	phys_addr_t paddr;

	/* The various ioremap'ed bases */
	struct mpic_reg_bank	thiscpuregs;
	struct mpic_reg_bank	gregs;
	struct mpic_reg_bank	tmregs;
	struct mpic_reg_bank	cpuregs[MPIC_MAX_CPUS];
	struct mpic_reg_bank	isus[MPIC_MAX_ISU];

	/* ioremap'ed base for error interrupt registers */
	u32 __iomem	*err_regs;

	/* Protected sources */
	unsigned long		*protected;

#ifdef CONFIG_MPIC_WEIRD
	/* Pointer to HW info array */
	u32			*hw_set;
#endif

#ifdef CONFIG_PCI_MSI
	struct msi_bitmap	msi_bitmap;
#endif

#ifdef CONFIG_MPIC_BROKEN_REGREAD
	u32			isu_reg0_shadow[MPIC_MAX_IRQ_SOURCES];
#endif

	/* link */
	struct mpic		*next;

#ifdef CONFIG_PM
	struct mpic_irq_save	*save_data;
#endif
};

extern struct bus_type mpic_subsys;

/*
 * MPIC flags (passed to mpic_alloc)
 *
 * The top 4 bits contain an MPIC bhw id that is used to index the
 * register offsets and some masks when CONFIG_MPIC_WEIRD is set.
 * Note setting any ID (leaving those bits to 0) means standard MPIC
 */

/*
 * This is a secondary ("chained") controller; it only uses the CPU0
 * registers.  Primary controllers have IPIs and affinity control.
 */
#define MPIC_SECONDARY			0x00000001

/* Set this for a big-endian MPIC */
#define MPIC_BIG_ENDIAN			0x00000002
/* Broken U3 MPIC */
#define MPIC_U3_HT_IRQS			0x00000004
/* Broken IPI registers (autodetected) */
#define MPIC_BROKEN_IPI			0x00000008
/* Spurious vector requires EOI */
#define MPIC_SPV_EOI			0x00000020
/* No passthrough disable */
#define MPIC_NO_PTHROU_DIS		0x00000040
/* DCR based MPIC */
#define MPIC_USES_DCR			0x00000080
/* MPIC has 11-bit vector fields (or larger) */
#define MPIC_LARGE_VECTORS		0x00000100
/* Enable delivery of prio 15 interrupts as MCK instead of EE */
#define MPIC_ENABLE_MCK			0x00000200
/* Disable bias among target selection, spread interrupts evenly */
#define MPIC_NO_BIAS			0x00000400
/* Destination only supports a single CPU at a time */
#define MPIC_SINGLE_DEST_CPU		0x00001000
/* Enable CoreInt delivery of interrupts */
#define MPIC_ENABLE_COREINT		0x00002000
/* Do not reset the MPIC during initialization */
#define MPIC_NO_RESET			0x00004000
/* Freescale MPIC (compatible includes "fsl,mpic") */
#define MPIC_FSL			0x00008000
/* Freescale MPIC supports EIMR (error interrupt mask register).
 * This flag is set for MPIC version >= 4.1 (version determined
 * from the BRR1 register).
*/
#define MPIC_FSL_HAS_EIMR		0x00010000

/* MPIC HW modification ID */
#define MPIC_REGSET_MASK		0xf0000000
#define MPIC_REGSET(val)		(((val) & 0xf ) << 28)
#define MPIC_GET_REGSET(flags)		(((flags) >> 28) & 0xf)

#define	MPIC_REGSET_STANDARD		MPIC_REGSET(0)	/* Original MPIC */
#define	MPIC_REGSET_TSI108		MPIC_REGSET(1)	/* Tsi108/109 PIC */

/* Get the version of primary MPIC */
extern u32 fsl_mpic_primary_get_version(void);

/* Allocate the controller structure and setup the linux irq descs
 * for the range if interrupts passed in. No HW initialization is
 * actually performed.
 * 
 * @phys_addr:	physial base address of the MPIC
 * @flags:	flags, see constants above
 * @isu_size:	number of interrupts in an ISU. Use 0 to use a
 *              standard ISU-less setup (aka powermac)
 * @irq_offset: first irq number to assign to this mpic
 * @irq_count:  number of irqs to use with this mpic IRQ sources. Pass 0
 *	        to match the number of sources
 * @ipi_offset: first irq number to assign to this mpic IPI sources,
 *		used only on primary mpic
 * @senses:	array of sense values
 * @senses_num: number of entries in the array
 *
 * Note about the sense array. If none is passed, all interrupts are
 * setup to be level negative unless MPIC_U3_HT_IRQS is set in which
 * case they are edge positive (and the array is ignored anyway).
 * The values in the array start at the first source of the MPIC,
 * that is senses[0] correspond to linux irq "irq_offset".
 */
extern struct mpic *mpic_alloc(struct device_node *node,
			       phys_addr_t phys_addr,
			       unsigned int flags,
			       unsigned int isu_size,
			       unsigned int irq_count,
			       const char *name);

/* Assign ISUs, to call before mpic_init()
 *
 * @mpic:	controller structure as returned by mpic_alloc()
 * @isu_num:	ISU number
 * @phys_addr:	physical address of the ISU
 */
extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
			    phys_addr_t phys_addr);


/* Initialize the controller. After this has been called, none of the above
 * should be called again for this mpic
 */
extern void mpic_init(struct mpic *mpic);

/*
 * All of the following functions must only be used after the
 * ISUs have been assigned and the controller fully initialized
 * with mpic_init()
 */


/* Change the priority of an interrupt. Default is 8 for irqs and
 * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
 * IPI number is then the offset'ed (linux irq number mapped to the IPI)
 */
extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);

/* Setup a non-boot CPU */
extern void mpic_setup_this_cpu(void);

/* Clean up for kexec (or cpu offline or ...) */
extern void mpic_teardown_this_cpu(int secondary);

/* Get the current cpu priority for this cpu (0..15) */
extern int mpic_cpu_get_priority(void);

/* Set the current cpu priority for this cpu */
extern void mpic_cpu_set_priority(int prio);

/* Request IPIs on primary mpic */
extern void mpic_request_ipis(void);

/* Send a message (IPI) to a given target (cpu number or MSG_*) */
void smp_mpic_message_pass(int target, int msg);

/* Unmask a specific virq */
extern void mpic_unmask_irq(struct irq_data *d);
/* Mask a specific virq */
extern void mpic_mask_irq(struct irq_data *d);
/* EOI a specific virq */
extern void mpic_end_irq(struct irq_data *d);

/* Fetch interrupt from a given mpic */
extern unsigned int mpic_get_one_irq(struct mpic *mpic);
/* This one gets from the primary mpic */
extern unsigned int mpic_get_irq(void);
/* This one gets from the primary mpic via CoreInt*/
extern unsigned int mpic_get_coreint_irq(void);
/* Fetch Machine Check interrupt from primary mpic */
extern unsigned int mpic_get_mcirq(void);

#endif /* __KERNEL__ */
#endif	/* _ASM_POWERPC_MPIC_H */
Commit	Line	Data
bbeb3f4c SR	1	#ifndef _ASM_POWERPC_MPIC_H
bbeb3f4c SR	2	#define _ASM_POWERPC_MPIC_H
88ced031	3	#ifdef __KERNEL__
bbeb3f4c	4
14cf11af	5	#include <linux/irq.h>
fbf0274e	6	#include <asm/dcr.h>
25235f71	7	#include <asm/msi_bitmap.h>
14cf11af PM	8
	9	/*
	10	* Global registers
	11	*/
	12
	13	#define MPIC_GREG_BASE 0x01000
	14
	15	#define MPIC_GREG_FEATURE_0 0x00000
	16	#define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
	17	#define MPIC_GREG_FEATURE_LAST_SRC_SHIFT 16
	18	#define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
	19	#define MPIC_GREG_FEATURE_LAST_CPU_SHIFT 8
	20	#define MPIC_GREG_FEATURE_VERSION_MASK 0xff
	21	#define MPIC_GREG_FEATURE_1 0x00010
	22	#define MPIC_GREG_GLOBAL_CONF_0 0x00020
	23	#define MPIC_GREG_GCONF_RESET 0x80000000
d91e4ea7 KG	24	/* On the FSL mpic implementations the Mode field is expand to be
	25	* 2 bits wide:
	26	* 0b00 = pass through (interrupts routed to IRQ0)
	27	* 0b01 = Mixed mode
	28	* 0b10 = reserved
	29	* 0b11 = External proxy / coreint
	30	*/
	31	#define MPIC_GREG_GCONF_COREINT 0x60000000
14cf11af	32	#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000
d87bf3be	33	#define MPIC_GREG_GCONF_NO_BIAS 0x10000000
14cf11af	34	#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
f365355e	35	#define MPIC_GREG_GCONF_MCK 0x08000000
14cf11af PM	36	#define MPIC_GREG_GLOBAL_CONF_1 0x00030
	37	#define MPIC_GREG_VENDOR_0 0x00040
	38	#define MPIC_GREG_VENDOR_1 0x00050
	39	#define MPIC_GREG_VENDOR_2 0x00060
	40	#define MPIC_GREG_VENDOR_3 0x00070
	41	#define MPIC_GREG_VENDOR_ID 0x00080
	42	#define MPIC_GREG_VENDOR_ID_STEPPING_MASK 0x00ff0000
	43	#define MPIC_GREG_VENDOR_ID_STEPPING_SHIFT 16
	44	#define MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00
	45	#define MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT 8
	46	#define MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK 0x000000ff
	47	#define MPIC_GREG_PROCESSOR_INIT 0x00090
	48	#define MPIC_GREG_IPI_VECTOR_PRI_0 0x000a0
	49	#define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0
	50	#define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0
	51	#define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0
7233593b	52	#define MPIC_GREG_IPI_STRIDE 0x10
14cf11af PM	53	#define MPIC_GREG_SPURIOUS 0x000e0
	54	#define MPIC_GREG_TIMER_FREQ 0x000f0
	55
	56	/*
	57	*
	58	* Timer registers
	59	*/
	60	#define MPIC_TIMER_BASE 0x01100
	61	#define MPIC_TIMER_STRIDE 0x40
03bcb7e3	62	#define MPIC_TIMER_GROUP_STRIDE 0x1000
14cf11af PM	63
	64	#define MPIC_TIMER_CURRENT_CNT 0x00000
	65	#define MPIC_TIMER_BASE_CNT 0x00010
	66	#define MPIC_TIMER_VECTOR_PRI 0x00020
	67	#define MPIC_TIMER_DESTINATION 0x00030
	68
	69	/*
	70	* Per-Processor registers
	71	*/
	72
	73	#define MPIC_CPU_THISBASE 0x00000
	74	#define MPIC_CPU_BASE 0x20000
	75	#define MPIC_CPU_STRIDE 0x01000
	76
	77	#define MPIC_CPU_IPI_DISPATCH_0 0x00040
	78	#define MPIC_CPU_IPI_DISPATCH_1 0x00050
	79	#define MPIC_CPU_IPI_DISPATCH_2 0x00060
	80	#define MPIC_CPU_IPI_DISPATCH_3 0x00070
7233593b	81	#define MPIC_CPU_IPI_DISPATCH_STRIDE 0x00010
14cf11af PM	82	#define MPIC_CPU_CURRENT_TASK_PRI 0x00080
	83	#define MPIC_CPU_TASKPRI_MASK 0x0000000f
	84	#define MPIC_CPU_WHOAMI 0x00090
	85	#define MPIC_CPU_WHOAMI_MASK 0x0000001f
	86	#define MPIC_CPU_INTACK 0x000a0
	87	#define MPIC_CPU_EOI 0x000b0
f365355e	88	#define MPIC_CPU_MCACK 0x000c0
14cf11af PM	89
	90	/*
	91	* Per-source registers
	92	*/
	93
	94	#define MPIC_IRQ_BASE 0x10000
	95	#define MPIC_IRQ_STRIDE 0x00020
	96	#define MPIC_IRQ_VECTOR_PRI 0x00000
	97	#define MPIC_VECPRI_MASK 0x80000000
	98	#define MPIC_VECPRI_ACTIVITY 0x40000000 /* Read Only */
	99	#define MPIC_VECPRI_PRIORITY_MASK 0x000f0000
	100	#define MPIC_VECPRI_PRIORITY_SHIFT 16
	101	#define MPIC_VECPRI_VECTOR_MASK 0x000007ff
	102	#define MPIC_VECPRI_POLARITY_POSITIVE 0x00800000
	103	#define MPIC_VECPRI_POLARITY_NEGATIVE 0x00000000
	104	#define MPIC_VECPRI_POLARITY_MASK 0x00800000
	105	#define MPIC_VECPRI_SENSE_LEVEL 0x00400000
	106	#define MPIC_VECPRI_SENSE_EDGE 0x00000000
	107	#define MPIC_VECPRI_SENSE_MASK 0x00400000
	108	#define MPIC_IRQ_DESTINATION 0x00010
	109
03bcb7e3 VS	110	#define MPIC_FSL_BRR1 0x00000
	111	#define MPIC_FSL_BRR1_VER 0x0000ffff
	112
14cf11af PM	113	#define MPIC_MAX_IRQ_SOURCES 2048
	114	#define MPIC_MAX_CPUS 32
	115	#define MPIC_MAX_ISU 32
	116
0a408164 VS	117	#define MPIC_MAX_ERR 32
	118	#define MPIC_FSL_ERR_INT 16
	119
7233593b ZR	120	/*
	121	* Tsi108 implementation of MPIC has many differences from the original one
	122	*/
	123
	124	/*
	125	* Global registers
	126	*/
	127
	128	#define TSI108_GREG_BASE 0x00000
	129	#define TSI108_GREG_FEATURE_0 0x00000
	130	#define TSI108_GREG_GLOBAL_CONF_0 0x00004
	131	#define TSI108_GREG_VENDOR_ID 0x0000c
	132	#define TSI108_GREG_IPI_VECTOR_PRI_0 0x00204 /* Doorbell 0 */
	133	#define TSI108_GREG_IPI_STRIDE 0x0c
	134	#define TSI108_GREG_SPURIOUS 0x00010
	135	#define TSI108_GREG_TIMER_FREQ 0x00014
	136
	137	/*
	138	* Timer registers
	139	*/
	140	#define TSI108_TIMER_BASE 0x0030
	141	#define TSI108_TIMER_STRIDE 0x10
	142	#define TSI108_TIMER_CURRENT_CNT 0x00000
	143	#define TSI108_TIMER_BASE_CNT 0x00004
	144	#define TSI108_TIMER_VECTOR_PRI 0x00008
	145	#define TSI108_TIMER_DESTINATION 0x0000c
	146
	147	/*
	148	* Per-Processor registers
	149	*/
	150	#define TSI108_CPU_BASE 0x00300
	151	#define TSI108_CPU_STRIDE 0x00040
	152	#define TSI108_CPU_IPI_DISPATCH_0 0x00200
	153	#define TSI108_CPU_IPI_DISPATCH_STRIDE 0x00000
	154	#define TSI108_CPU_CURRENT_TASK_PRI 0x00000
	155	#define TSI108_CPU_WHOAMI 0xffffffff
	156	#define TSI108_CPU_INTACK 0x00004
	157	#define TSI108_CPU_EOI 0x00008
f365355e	158	#define TSI108_CPU_MCACK 0x00004 /* Doesn't really exist here */
7233593b ZR	159
	160	/*
	161	* Per-source registers
	162	*/
	163	#define TSI108_IRQ_BASE 0x00100
	164	#define TSI108_IRQ_STRIDE 0x00008
	165	#define TSI108_IRQ_VECTOR_PRI 0x00000
	166	#define TSI108_VECPRI_VECTOR_MASK 0x000000ff
	167	#define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000
	168	#define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000
	169	#define TSI108_VECPRI_SENSE_LEVEL 0x02000000
	170	#define TSI108_VECPRI_SENSE_EDGE 0x00000000
	171	#define TSI108_VECPRI_POLARITY_MASK 0x01000000
	172	#define TSI108_VECPRI_SENSE_MASK 0x02000000
	173	#define TSI108_IRQ_DESTINATION 0x00004
	174
	175	/* weird mpic register indices and mask bits in the HW info array */
	176	enum {
	177	MPIC_IDX_GREG_BASE = 0,
	178	MPIC_IDX_GREG_FEATURE_0,
	179	MPIC_IDX_GREG_GLOBAL_CONF_0,
	180	MPIC_IDX_GREG_VENDOR_ID,
	181	MPIC_IDX_GREG_IPI_VECTOR_PRI_0,
	182	MPIC_IDX_GREG_IPI_STRIDE,
	183	MPIC_IDX_GREG_SPURIOUS,
	184	MPIC_IDX_GREG_TIMER_FREQ,
	185
	186	MPIC_IDX_TIMER_BASE,
	187	MPIC_IDX_TIMER_STRIDE,
	188	MPIC_IDX_TIMER_CURRENT_CNT,
	189	MPIC_IDX_TIMER_BASE_CNT,
	190	MPIC_IDX_TIMER_VECTOR_PRI,
	191	MPIC_IDX_TIMER_DESTINATION,
	192
	193	MPIC_IDX_CPU_BASE,
	194	MPIC_IDX_CPU_STRIDE,
	195	MPIC_IDX_CPU_IPI_DISPATCH_0,
	196	MPIC_IDX_CPU_IPI_DISPATCH_STRIDE,
	197	MPIC_IDX_CPU_CURRENT_TASK_PRI,
	198	MPIC_IDX_CPU_WHOAMI,
	199	MPIC_IDX_CPU_INTACK,
	200	MPIC_IDX_CPU_EOI,
f365355e	201	MPIC_IDX_CPU_MCACK,
7233593b ZR	202
	203	MPIC_IDX_IRQ_BASE,
	204	MPIC_IDX_IRQ_STRIDE,
	205	MPIC_IDX_IRQ_VECTOR_PRI,
	206
	207	MPIC_IDX_VECPRI_VECTOR_MASK,
	208	MPIC_IDX_VECPRI_POLARITY_POSITIVE,
	209	MPIC_IDX_VECPRI_POLARITY_NEGATIVE,
	210	MPIC_IDX_VECPRI_SENSE_LEVEL,
	211	MPIC_IDX_VECPRI_SENSE_EDGE,
	212	MPIC_IDX_VECPRI_POLARITY_MASK,
	213	MPIC_IDX_VECPRI_SENSE_MASK,
	214	MPIC_IDX_IRQ_DESTINATION,
	215	MPIC_IDX_END
	216	};
	217
	218
6cfef5b2	219	#ifdef CONFIG_MPIC_U3_HT_IRQS
14cf11af PM	220	/* Fixup table entry */
	221	struct mpic_irq_fixup
	222	{
	223	u8 __iomem *base;
1beb6a7d	224	u8 __iomem *applebase;
c4b22f26	225	u32 data;
1beb6a7d	226	unsigned int index;
14cf11af	227	};
6cfef5b2	228	#endif /* CONFIG_MPIC_U3_HT_IRQS */
14cf11af PM	229
14cf11af PM	230
fbf0274e BH	231	enum mpic_reg_type {
	232	mpic_access_mmio_le,
	233	mpic_access_mmio_be,
	234	#ifdef CONFIG_PPC_DCR
	235	mpic_access_dcr
	236	#endif
	237	};
	238
	239	struct mpic_reg_bank {
	240	u32 __iomem *base;
	241	#ifdef CONFIG_PPC_DCR
	242	dcr_host_t dhost;
fbf0274e BH	243	#endif /* CONFIG_PPC_DCR */
	244	};
	245
3669e930 JB	246	struct mpic_irq_save {
	247	u32 vecprio,
	248	dest;
	249	#ifdef CONFIG_MPIC_U3_HT_IRQS
	250	u32 fixup_data;
	251	#endif
	252	};
	253
14cf11af PM	254	/* The instance data of a given MPIC */
	255	struct mpic
	256	{
c51242e7 KM	257	/* The OpenFirmware dt node for this MPIC */
	258	struct device_node *node;
	259
0ebfff14	260	/* The remapper for this MPIC */
bae1d8f1	261	struct irq_domain *irqhost;
0ebfff14	262
14cf11af	263	/* The "linux" controller struct */
b9e5b4e6	264	struct irq_chip hc_irq;
6cfef5b2	265	#ifdef CONFIG_MPIC_U3_HT_IRQS
b9e5b4e6 BH	266	struct irq_chip hc_ht_irq;
b9e5b4e6 BH	267	#endif
14cf11af	268	#ifdef CONFIG_SMP
b9e5b4e6	269	struct irq_chip hc_ipi;
14cf11af	270	#endif
ea94187f	271	struct irq_chip hc_tm;
0a408164	272	struct irq_chip hc_err;
14cf11af PM	273	const char *name;
	274	/* Flags */
	275	unsigned int flags;
	276	/* How many irq sources in a given ISU */
	277	unsigned int isu_size;
	278	unsigned int isu_shift;
	279	unsigned int isu_mask;
14cf11af PM	280	/* Number of sources */
14cf11af PM	281	unsigned int num_sources;
14cf11af	282
7df2457d OJ	283	/* vector numbers used for internal sources (ipi/timers) */
7df2457d OJ	284	unsigned int ipi_vecs[4];
ea94187f	285	unsigned int timer_vecs[8];
0a408164 VS	286	/* vector numbers used for FSL MPIC error interrupts */
0a408164 VS	287	unsigned int err_int_vecs[MPIC_MAX_ERR];
7df2457d OJ	288
	289	/* Spurious vector to program into unused sources */
	290	unsigned int spurious_vec;
	291
6cfef5b2	292	#ifdef CONFIG_MPIC_U3_HT_IRQS
14cf11af PM	293	/* The fixup table */
14cf11af PM	294	struct mpic_irq_fixup *fixups;
203041ad	295	raw_spinlock_t fixup_lock;
14cf11af PM	296	#endif
14cf11af PM	297
fbf0274e BH	298	/* Register access method */
	299	enum mpic_reg_type reg_type;
	300
e7a98675 KM	301	/* The physical base address of the MPIC */
	302	phys_addr_t paddr;
	303
14cf11af	304	/* The various ioremap'ed bases */
03bcb7e3	305	struct mpic_reg_bank thiscpuregs;
fbf0274e BH	306	struct mpic_reg_bank gregs;
	307	struct mpic_reg_bank tmregs;
	308	struct mpic_reg_bank cpuregs[MPIC_MAX_CPUS];
	309	struct mpic_reg_bank isus[MPIC_MAX_ISU];
	310
0a408164 VS	311	/* ioremap'ed base for error interrupt registers */
	312	u32 __iomem *err_regs;
	313
7fd72186 BH	314	/* Protected sources */
	315	unsigned long *protected;
	316
7233593b ZR	317	#ifdef CONFIG_MPIC_WEIRD
	318	/* Pointer to HW info array */
	319	u32 *hw_set;
	320	#endif
	321
a7de7c74	322	#ifdef CONFIG_PCI_MSI
25235f71	323	struct msi_bitmap msi_bitmap;
a7de7c74 ME	324	#endif
a7de7c74 ME	325
0d72ba93 OJ	326	#ifdef CONFIG_MPIC_BROKEN_REGREAD
	327	u32 isu_reg0_shadow[MPIC_MAX_IRQ_SOURCES];
	328	#endif
	329
14cf11af PM	330	/* link */
14cf11af PM	331	struct mpic *next;
3669e930	332
3669e930 JB	333	#ifdef CONFIG_PM
	334	struct mpic_irq_save *save_data;
	335	#endif
14cf11af PM	336	};
14cf11af PM	337
9e6f31a9 D	338	extern struct bus_type mpic_subsys;
9e6f31a9 D	339
7233593b ZR	340	/*
	341	* MPIC flags (passed to mpic_alloc)
	342	*
	343	* The top 4 bits contain an MPIC bhw id that is used to index the
	344	* register offsets and some masks when CONFIG_MPIC_WEIRD is set.
	345	* Note setting any ID (leaving those bits to 0) means standard MPIC
	346	*/
	347
be8bec56 KM	348	/*
	349	* This is a secondary ("chained") controller; it only uses the CPU0
	350	* registers. Primary controllers have IPIs and affinity control.
14cf11af	351	*/
be8bec56	352	#define MPIC_SECONDARY 0x00000001
7233593b	353
14cf11af PM	354	/* Set this for a big-endian MPIC */
	355	#define MPIC_BIG_ENDIAN 0x00000002
	356	/* Broken U3 MPIC */
6cfef5b2	357	#define MPIC_U3_HT_IRQS 0x00000004
14cf11af PM	358	/* Broken IPI registers (autodetected) */
14cf11af PM	359	#define MPIC_BROKEN_IPI 0x00000008
7233593b ZR	360	/* Spurious vector requires EOI */
	361	#define MPIC_SPV_EOI 0x00000020
	362	/* No passthrough disable */
	363	#define MPIC_NO_PTHROU_DIS 0x00000040
fbf0274e BH	364	/* DCR based MPIC */
fbf0274e BH	365	#define MPIC_USES_DCR 0x00000080
7df2457d OJ	366	/* MPIC has 11-bit vector fields (or larger) */
7df2457d OJ	367	#define MPIC_LARGE_VECTORS 0x00000100
f365355e OJ	368	/* Enable delivery of prio 15 interrupts as MCK instead of EE */
f365355e OJ	369	#define MPIC_ENABLE_MCK 0x00000200
d87bf3be OJ	370	/* Disable bias among target selection, spread interrupts evenly */
d87bf3be OJ	371	#define MPIC_NO_BIAS 0x00000400
3c10c9c4 KG	372	/* Destination only supports a single CPU at a time */
3c10c9c4 KG	373	#define MPIC_SINGLE_DEST_CPU 0x00001000
d91e4ea7 KG	374	/* Enable CoreInt delivery of interrupts */
d91e4ea7 KG	375	#define MPIC_ENABLE_COREINT 0x00002000
e55d7f73	376	/* Do not reset the MPIC during initialization */
dfec2202	377	#define MPIC_NO_RESET 0x00004000
22d168ce SW	378	/* Freescale MPIC (compatible includes "fsl,mpic") */
22d168ce SW	379	#define MPIC_FSL 0x00008000
0a408164 VS	380	/* Freescale MPIC supports EIMR (error interrupt mask register).
	381	* This flag is set for MPIC version >= 4.1 (version determined
	382	* from the BRR1 register).
	383	*/
	384	#define MPIC_FSL_HAS_EIMR 0x00010000
7233593b ZR	385
	386	/* MPIC HW modification ID */
	387	#define MPIC_REGSET_MASK 0xf0000000
	388	#define MPIC_REGSET(val) (((val) & 0xf ) << 28)
	389	#define MPIC_GET_REGSET(flags) (((flags) >> 28) & 0xf)
	390
	391	#define MPIC_REGSET_STANDARD MPIC_REGSET(0) /* Original MPIC */
	392	#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */
14cf11af	393
807d38b7 HJ	394	/* Get the version of primary MPIC */
	395	extern u32 fsl_mpic_primary_get_version(void);
	396
14cf11af PM	397	/* Allocate the controller structure and setup the linux irq descs
	398	* for the range if interrupts passed in. No HW initialization is
	399	* actually performed.
	400	*
	401	* @phys_addr: physial base address of the MPIC
	402	* @flags: flags, see constants above
	403	* @isu_size: number of interrupts in an ISU. Use 0 to use a
	404	* standard ISU-less setup (aka powermac)
	405	* @irq_offset: first irq number to assign to this mpic
	406	* @irq_count: number of irqs to use with this mpic IRQ sources. Pass 0
	407	* to match the number of sources
	408	* @ipi_offset: first irq number to assign to this mpic IPI sources,
	409	* used only on primary mpic
	410	* @senses: array of sense values
	411	* @senses_num: number of entries in the array
	412	*
	413	* Note about the sense array. If none is passed, all interrupts are
6cfef5b2	414	* setup to be level negative unless MPIC_U3_HT_IRQS is set in which
14cf11af PM	415	* case they are edge positive (and the array is ignored anyway).
	416	* The values in the array start at the first source of the MPIC,
	417	* that is senses[0] correspond to linux irq "irq_offset".
	418	*/
0ebfff14	419	extern struct mpic mpic_alloc(struct device_node node,
a959ff56	420	phys_addr_t phys_addr,
14cf11af PM	421	unsigned int flags,
14cf11af PM	422	unsigned int isu_size,
14cf11af	423	unsigned int irq_count,
14cf11af PM	424	const char *name);
	425
	426	/* Assign ISUs, to call before mpic_init()
	427	*
	428	* @mpic: controller structure as returned by mpic_alloc()
	429	* @isu_num: ISU number
	430	* @phys_addr: physical address of the ISU
	431	*/
	432	extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
a959ff56	433	phys_addr_t phys_addr);
14cf11af	434
0ebfff14	435
14cf11af PM	436	/* Initialize the controller. After this has been called, none of the above
	437	* should be called again for this mpic
	438	*/
	439	extern void mpic_init(struct mpic *mpic);
	440
14cf11af PM	441	/*
	442	* All of the following functions must only be used after the
	443	* ISUs have been assigned and the controller fully initialized
	444	* with mpic_init()
	445	*/
	446
	447
06a901c5	448	/* Change the priority of an interrupt. Default is 8 for irqs and
14cf11af PM	449	* 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
	450	* IPI number is then the offset'ed (linux irq number mapped to the IPI)
	451	*/
	452	extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
14cf11af PM	453
	454	/* Setup a non-boot CPU */
	455	extern void mpic_setup_this_cpu(void);
	456
	457	/* Clean up for kexec (or cpu offline or ...) */
	458	extern void mpic_teardown_this_cpu(int secondary);
	459
	460	/* Get the current cpu priority for this cpu (0..15) */
	461	extern int mpic_cpu_get_priority(void);
	462
	463	/* Set the current cpu priority for this cpu */
	464	extern void mpic_cpu_set_priority(int prio);
	465
	466	/* Request IPIs on primary mpic */
	467	extern void mpic_request_ipis(void);
	468
a9c59264 PM	469	/* Send a message (IPI) to a given target (cpu number or MSG_) /
	470	void smp_mpic_message_pass(int target, int msg);
	471
f365355e	472	/* Unmask a specific virq */
835c0553	473	extern void mpic_unmask_irq(struct irq_data *d);
f365355e	474	/* Mask a specific virq */
835c0553	475	extern void mpic_mask_irq(struct irq_data *d);
f365355e	476	/* EOI a specific virq */
835c0553	477	extern void mpic_end_irq(struct irq_data *d);
f365355e	478
14cf11af	479	/* Fetch interrupt from a given mpic */
35a84c2f	480	extern unsigned int mpic_get_one_irq(struct mpic *mpic);
f365355e	481	/* This one gets from the primary mpic */
35a84c2f	482	extern unsigned int mpic_get_irq(void);
d91e4ea7 KG	483	/* This one gets from the primary mpic via CoreInt*/
d91e4ea7 KG	484	extern unsigned int mpic_get_coreint_irq(void);
f365355e OJ	485	/* Fetch Machine Check interrupt from primary mpic */
f365355e OJ	486	extern unsigned int mpic_get_mcirq(void);
14cf11af	487
88ced031	488	#endif /* __KERNEL__ */
bbeb3f4c	489	#endif /* _ASM_POWERPC_MPIC_H */