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047ea784 PM |
1 | #ifndef _ASM_POWERPC_MMU_H_ |
2 | #define _ASM_POWERPC_MMU_H_ | |
88ced031 | 3 | #ifdef __KERNEL__ |
047ea784 | 4 | |
cd3db0c4 BH |
5 | #include <linux/types.h> |
6 | ||
7c03d653 BH |
7 | #include <asm/asm-compat.h> |
8 | #include <asm/feature-fixups.h> | |
9 | ||
10 | /* | |
11 | * MMU features bit definitions | |
12 | */ | |
13 | ||
14 | /* | |
15 | * First half is MMU families | |
16 | */ | |
17 | #define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001) | |
18 | #define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002) | |
19 | #define MMU_FTR_TYPE_40x ASM_CONST(0x00000004) | |
20 | #define MMU_FTR_TYPE_44x ASM_CONST(0x00000008) | |
21 | #define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010) | |
cd68098b | 22 | #define MMU_FTR_TYPE_47x ASM_CONST(0x00000020) |
7c03d653 BH |
23 | |
24 | /* | |
25 | * This is individual features | |
26 | */ | |
accfad7d AK |
27 | /* |
28 | * We need to clear top 16bits of va (from the remaining 64 bits )in | |
29 | * tlbie* instructions | |
30 | */ | |
31 | #define MMU_FTR_TLBIE_CROP_VA ASM_CONST(0x00008000) | |
7c03d653 BH |
32 | |
33 | /* Enable use of high BAT registers */ | |
34 | #define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000) | |
35 | ||
36 | /* Enable >32-bit physical addresses on 32-bit processor, only used | |
37 | * by CONFIG_6xx currently as BookE supports that from day 1 | |
38 | */ | |
39 | #define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000) | |
40 | ||
f048aace BH |
41 | /* Enable use of broadcast TLB invalidations. We don't always set it |
42 | * on processors that support it due to other constraints with the | |
43 | * use of such invalidations | |
44 | */ | |
45 | #define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000) | |
46 | ||
c3071951 | 47 | /* Enable use of tlbilx invalidate instructions. |
f048aace | 48 | */ |
c3071951 | 49 | #define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000) |
f048aace BH |
50 | |
51 | /* This indicates that the processor cannot handle multiple outstanding | |
52 | * broadcast tlbivax or tlbsync. This makes the code use a spinlock | |
53 | * around such invalidate forms. | |
54 | */ | |
55 | #define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000) | |
56 | ||
2319f123 KG |
57 | /* This indicates that the processor doesn't handle way selection |
58 | * properly and needs SW to track and update the LRU state. This | |
59 | * is specific to an errata on e300c2/c3/c4 class parts | |
60 | */ | |
61 | #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) | |
62 | ||
df5d6ecf KG |
63 | /* Enable use of TLB reservation. Processor should support tlbsrx. |
64 | * instruction and MAS0[WQ]. | |
65 | */ | |
66 | #define MMU_FTR_USE_TLBRSRV ASM_CONST(0x00800000) | |
67 | ||
68 | /* Use paired MAS registers (MAS7||MAS3, etc.) | |
69 | */ | |
70 | #define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000) | |
71 | ||
13b3d13b | 72 | /* Doesn't support the B bit (1T segment) in SLBIE |
44ae3ab3 | 73 | */ |
13b3d13b | 74 | #define MMU_FTR_NO_SLBIE_B ASM_CONST(0x02000000) |
44ae3ab3 ME |
75 | |
76 | /* Support 16M large pages | |
77 | */ | |
78 | #define MMU_FTR_16M_PAGE ASM_CONST(0x04000000) | |
79 | ||
80 | /* Supports TLBIEL variant | |
81 | */ | |
82 | #define MMU_FTR_TLBIEL ASM_CONST(0x08000000) | |
83 | ||
84 | /* Supports tlbies w/o locking | |
85 | */ | |
86 | #define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000) | |
87 | ||
88 | /* Large pages can be marked CI | |
89 | */ | |
90 | #define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000) | |
91 | ||
92 | /* 1T segments available | |
93 | */ | |
94 | #define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000) | |
95 | ||
a8ed87c9 AK |
96 | /* |
97 | * Radix page table available | |
98 | */ | |
99 | #define MMU_FTR_RADIX ASM_CONST(0x80000000) | |
100 | ||
44ae3ab3 ME |
101 | /* MMU feature bit sets for various CPUs */ |
102 | #define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \ | |
103 | MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2 | |
104 | #define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | |
accfad7d | 105 | #define MMU_FTRS_PPC970 MMU_FTRS_POWER4 | MMU_FTR_TLBIE_CROP_VA |
44ae3ab3 ME |
106 | #define MMU_FTRS_POWER5 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE |
107 | #define MMU_FTRS_POWER6 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE | |
a32e252f | 108 | #define MMU_FTRS_POWER7 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE |
71e18497 | 109 | #define MMU_FTRS_POWER8 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE |
c3ab300e | 110 | #define MMU_FTRS_POWER9 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE |
44ae3ab3 ME |
111 | #define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \ |
112 | MMU_FTR_CI_LARGE_PAGE | |
113 | #define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \ | |
114 | MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B | |
7c03d653 BH |
115 | #ifndef __ASSEMBLY__ |
116 | #include <asm/cputable.h> | |
117 | ||
3160b097 BB |
118 | #ifdef CONFIG_PPC_FSL_BOOK3E |
119 | #include <asm/percpu.h> | |
120 | DECLARE_PER_CPU(int, next_tlbcam_idx); | |
121 | #endif | |
122 | ||
773edead ME |
123 | enum { |
124 | MMU_FTRS_POSSIBLE = MMU_FTR_HPTE_TABLE | MMU_FTR_TYPE_8xx | | |
125 | MMU_FTR_TYPE_40x | MMU_FTR_TYPE_44x | MMU_FTR_TYPE_FSL_E | | |
126 | MMU_FTR_TYPE_47x | MMU_FTR_USE_HIGH_BATS | MMU_FTR_BIG_PHYS | | |
127 | MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_USE_TLBILX | | |
128 | MMU_FTR_LOCK_BCAST_INVAL | MMU_FTR_NEED_DTLB_SW_LRU | | |
129 | MMU_FTR_USE_TLBRSRV | MMU_FTR_USE_PAIRED_MAS | | |
130 | MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL | | |
131 | MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE | | |
accfad7d | 132 | MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA | |
a8ed87c9 AK |
133 | #ifdef CONFIG_PPC_RADIX_MMU |
134 | MMU_FTR_RADIX | | |
135 | #endif | |
136 | 0, | |
773edead ME |
137 | }; |
138 | ||
7c03d653 BH |
139 | static inline int mmu_has_feature(unsigned long feature) |
140 | { | |
773edead | 141 | return (MMU_FTRS_POSSIBLE & cur_cpu_spec->mmu_features & feature); |
7c03d653 BH |
142 | } |
143 | ||
91b191c7 DK |
144 | static inline void mmu_clear_feature(unsigned long feature) |
145 | { | |
146 | cur_cpu_spec->mmu_features &= ~feature; | |
147 | } | |
148 | ||
7c03d653 BH |
149 | extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup; |
150 | ||
cd3db0c4 BH |
151 | #ifdef CONFIG_PPC64 |
152 | /* This is our real memory area size on ppc64 server, on embedded, we | |
153 | * make it match the size our of bolted TLB area | |
154 | */ | |
155 | extern u64 ppc64_rma_size; | |
156 | #endif /* CONFIG_PPC64 */ | |
157 | ||
78f1dbde AK |
158 | struct mm_struct; |
159 | #ifdef CONFIG_DEBUG_VM | |
160 | extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr); | |
161 | #else /* CONFIG_DEBUG_VM */ | |
162 | static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr) | |
163 | { | |
164 | } | |
165 | #endif /* !CONFIG_DEBUG_VM */ | |
166 | ||
7c03d653 BH |
167 | #endif /* !__ASSEMBLY__ */ |
168 | ||
57e2a99f BH |
169 | /* The kernel use the constants below to index in the page sizes array. |
170 | * The use of fixed constants for this purpose is better for performances | |
171 | * of the low level hash refill handlers. | |
172 | * | |
173 | * A non supported page size has a "shift" field set to 0 | |
174 | * | |
175 | * Any new page size being implemented can get a new entry in here. Whether | |
176 | * the kernel will use it or not is a different matter though. The actual page | |
177 | * size used by hugetlbfs is not defined here and may be made variable | |
178 | * | |
179 | * Note: This array ended up being a false good idea as it's growing to the | |
180 | * point where I wonder if we should replace it with something different, | |
181 | * to think about, feedback welcome. --BenH. | |
182 | */ | |
183 | ||
a8b91e43 | 184 | /* These are #defines as they have to be used in assembly */ |
57e2a99f BH |
185 | #define MMU_PAGE_4K 0 |
186 | #define MMU_PAGE_16K 1 | |
187 | #define MMU_PAGE_64K 2 | |
188 | #define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */ | |
189 | #define MMU_PAGE_256K 4 | |
190 | #define MMU_PAGE_1M 5 | |
28efc35f SW |
191 | #define MMU_PAGE_2M 6 |
192 | #define MMU_PAGE_4M 7 | |
193 | #define MMU_PAGE_8M 8 | |
194 | #define MMU_PAGE_16M 9 | |
195 | #define MMU_PAGE_64M 10 | |
196 | #define MMU_PAGE_256M 11 | |
197 | #define MMU_PAGE_1G 12 | |
198 | #define MMU_PAGE_16G 13 | |
199 | #define MMU_PAGE_64G 14 | |
200 | ||
201 | #define MMU_PAGE_COUNT 15 | |
7c03d653 | 202 | |
11a6f6ab AK |
203 | #ifdef CONFIG_PPC_BOOK3S_64 |
204 | #include <asm/book3s/64/mmu.h> | |
205 | #else /* CONFIG_PPC_BOOK3S_64 */ | |
206 | ||
756d08d1 AK |
207 | #ifndef __ASSEMBLY__ |
208 | /* MMU initialization */ | |
209 | extern void early_init_mmu(void); | |
210 | extern void early_init_mmu_secondary(void); | |
211 | extern void setup_initial_memory_limit(phys_addr_t first_memblock_base, | |
212 | phys_addr_t first_memblock_size); | |
1a01dc87 | 213 | static inline void mmu_early_init_devtree(void) { } |
756d08d1 | 214 | #endif /* __ASSEMBLY__ */ |
11a6f6ab AK |
215 | #endif |
216 | ||
217 | #if defined(CONFIG_PPC_STD_MMU_32) | |
4db68bfe | 218 | /* 32-bit classic hash table MMU */ |
f64e8084 | 219 | #include <asm/book3s/32/mmu-hash.h> |
4d922c8d JB |
220 | #elif defined(CONFIG_40x) |
221 | /* 40x-style software loaded TLB */ | |
222 | # include <asm/mmu-40x.h> | |
57d7909e DG |
223 | #elif defined(CONFIG_44x) |
224 | /* 44x-style software loaded TLB */ | |
225 | # include <asm/mmu-44x.h> | |
70fe3af8 KG |
226 | #elif defined(CONFIG_PPC_BOOK3E_MMU) |
227 | /* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */ | |
228 | # include <asm/mmu-book3e.h> | |
31202345 DG |
229 | #elif defined (CONFIG_PPC_8xx) |
230 | /* Motorola/Freescale 8xx software loaded TLB */ | |
231 | # include <asm/mmu-8xx.h> | |
1f8d419e | 232 | #endif |
1f8d419e | 233 | |
566ca99a AK |
234 | #ifndef radix_enabled |
235 | #define radix_enabled() (0) | |
236 | #endif | |
57e2a99f | 237 | |
88ced031 | 238 | #endif /* __KERNEL__ */ |
047ea784 | 239 | #endif /* _ASM_POWERPC_MMU_H_ */ |