Commit | Line | Data |
---|---|---|
d66c82ea KG |
1 | #ifndef _ASM_POWERPC_MMU_BOOK3E_H_ |
2 | #define _ASM_POWERPC_MMU_BOOK3E_H_ | |
67f74c9d | 3 | /* |
d66c82ea | 4 | * Freescale Book-E/Book-3e (ISA 2.06+) MMU support |
67f74c9d DG |
5 | */ |
6 | ||
d66c82ea KG |
7 | /* Book-3e defined page sizes */ |
8 | #define BOOK3E_PAGESZ_1K 0 | |
9 | #define BOOK3E_PAGESZ_2K 1 | |
10 | #define BOOK3E_PAGESZ_4K 2 | |
11 | #define BOOK3E_PAGESZ_8K 3 | |
12 | #define BOOK3E_PAGESZ_16K 4 | |
13 | #define BOOK3E_PAGESZ_32K 5 | |
14 | #define BOOK3E_PAGESZ_64K 6 | |
15 | #define BOOK3E_PAGESZ_128K 7 | |
16 | #define BOOK3E_PAGESZ_256K 8 | |
17 | #define BOOK3E_PAGESZ_512K 9 | |
18 | #define BOOK3E_PAGESZ_1M 10 | |
19 | #define BOOK3E_PAGESZ_2M 11 | |
20 | #define BOOK3E_PAGESZ_4M 12 | |
21 | #define BOOK3E_PAGESZ_8M 13 | |
22 | #define BOOK3E_PAGESZ_16M 14 | |
23 | #define BOOK3E_PAGESZ_32M 15 | |
24 | #define BOOK3E_PAGESZ_64M 16 | |
25 | #define BOOK3E_PAGESZ_128M 17 | |
26 | #define BOOK3E_PAGESZ_256M 18 | |
27 | #define BOOK3E_PAGESZ_512M 19 | |
28 | #define BOOK3E_PAGESZ_1GB 20 | |
29 | #define BOOK3E_PAGESZ_2GB 21 | |
30 | #define BOOK3E_PAGESZ_4GB 22 | |
31 | #define BOOK3E_PAGESZ_8GB 23 | |
32 | #define BOOK3E_PAGESZ_16GB 24 | |
33 | #define BOOK3E_PAGESZ_32GB 25 | |
34 | #define BOOK3E_PAGESZ_64GB 26 | |
35 | #define BOOK3E_PAGESZ_128GB 27 | |
36 | #define BOOK3E_PAGESZ_256GB 28 | |
37 | #define BOOK3E_PAGESZ_512GB 29 | |
38 | #define BOOK3E_PAGESZ_1TB 30 | |
39 | #define BOOK3E_PAGESZ_2TB 31 | |
67f74c9d | 40 | |
1fe1a210 BH |
41 | /* MAS registers bit definitions */ |
42 | ||
9c0d4e0d MC |
43 | #define MAS0_TLBSEL_MASK 0x30000000 |
44 | #define MAS0_TLBSEL_SHIFT 28 | |
45 | #define MAS0_TLBSEL(x) (((x) << MAS0_TLBSEL_SHIFT) & MAS0_TLBSEL_MASK) | |
46 | #define MAS0_GET_TLBSEL(mas0) (((mas0) & MAS0_TLBSEL_MASK) >> \ | |
47 | MAS0_TLBSEL_SHIFT) | |
f0aae323 | 48 | #define MAS0_ESEL_MASK 0x0FFF0000 |
57013524 SW |
49 | #define MAS0_ESEL_SHIFT 16 |
50 | #define MAS0_ESEL(x) (((x) << MAS0_ESEL_SHIFT) & MAS0_ESEL_MASK) | |
51 | #define MAS0_NV(x) ((x) & 0x00000FFF) | |
1fe1a210 BH |
52 | #define MAS0_HES 0x00004000 |
53 | #define MAS0_WQ_ALLWAYS 0x00000000 | |
54 | #define MAS0_WQ_COND 0x00001000 | |
55 | #define MAS0_WQ_CLR_RSRV 0x00002000 | |
56 | ||
57 | #define MAS1_VALID 0x80000000 | |
58 | #define MAS1_IPROT 0x40000000 | |
b51cbd41 | 59 | #define MAS1_TID(x) (((x) << 16) & 0x3FFF0000) |
1fe1a210 BH |
60 | #define MAS1_IND 0x00002000 |
61 | #define MAS1_TS 0x00001000 | |
62 | #define MAS1_TSIZE_MASK 0x00000f80 | |
63 | #define MAS1_TSIZE_SHIFT 7 | |
b51cbd41 | 64 | #define MAS1_TSIZE(x) (((x) << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK) |
9c0d4e0d | 65 | #define MAS1_GET_TSIZE(mas1) (((mas1) & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT) |
1fe1a210 | 66 | |
e9666ea1 | 67 | #define MAS2_EPN (~0xFFFUL) |
1fe1a210 BH |
68 | #define MAS2_X0 0x00000040 |
69 | #define MAS2_X1 0x00000020 | |
70 | #define MAS2_W 0x00000010 | |
71 | #define MAS2_I 0x00000008 | |
72 | #define MAS2_M 0x00000004 | |
73 | #define MAS2_G 0x00000002 | |
74 | #define MAS2_E 0x00000001 | |
41151e77 | 75 | #define MAS2_WIMGE_MASK 0x0000001f |
d66c82ea | 76 | #define MAS2_EPN_MASK(size) (~0 << (size + 10)) |
b3898895 | 77 | #define MAS2_VAL(addr, size, flags) ((addr) & MAS2_EPN_MASK(size) | (flags)) |
67f74c9d | 78 | |
1fe1a210 BH |
79 | #define MAS3_RPN 0xFFFFF000 |
80 | #define MAS3_U0 0x00000200 | |
81 | #define MAS3_U1 0x00000100 | |
82 | #define MAS3_U2 0x00000080 | |
83 | #define MAS3_U3 0x00000040 | |
84 | #define MAS3_UX 0x00000020 | |
85 | #define MAS3_SX 0x00000010 | |
86 | #define MAS3_UW 0x00000008 | |
87 | #define MAS3_SW 0x00000004 | |
88 | #define MAS3_UR 0x00000002 | |
89 | #define MAS3_SR 0x00000001 | |
41151e77 | 90 | #define MAS3_BAP_MASK 0x0000003f |
1fe1a210 BH |
91 | #define MAS3_SPSIZE 0x0000003e |
92 | #define MAS3_SPSIZE_SHIFT 1 | |
93 | ||
d57cef91 | 94 | #define MAS4_TLBSEL_MASK MAS0_TLBSEL_MASK |
1fe1a210 BH |
95 | #define MAS4_TLBSELD(x) MAS0_TLBSEL(x) |
96 | #define MAS4_INDD 0x00008000 /* Default IND */ | |
97 | #define MAS4_TSIZED(x) MAS1_TSIZE(x) | |
98 | #define MAS4_X0D 0x00000040 | |
99 | #define MAS4_X1D 0x00000020 | |
100 | #define MAS4_WD 0x00000010 | |
101 | #define MAS4_ID 0x00000008 | |
102 | #define MAS4_MD 0x00000004 | |
103 | #define MAS4_GD 0x00000002 | |
104 | #define MAS4_ED 0x00000001 | |
105 | #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */ | |
106 | #define MAS4_WIMGED_SHIFT 0 | |
107 | #define MAS4_VLED MAS4_X1D /* Default VLE */ | |
108 | #define MAS4_ACMD 0x000000c0 /* Default ACM */ | |
109 | #define MAS4_ACMD_SHIFT 6 | |
110 | #define MAS4_TSIZED_MASK 0x00000f80 /* Default TSIZE */ | |
111 | #define MAS4_TSIZED_SHIFT 7 | |
112 | ||
d30f6e48 SW |
113 | #define MAS5_SGS 0x80000000 |
114 | ||
1fe1a210 BH |
115 | #define MAS6_SPID0 0x3FFF0000 |
116 | #define MAS6_SPID1 0x00007FFE | |
117 | #define MAS6_ISIZE(x) MAS1_TSIZE(x) | |
118 | #define MAS6_SAS 0x00000001 | |
119 | #define MAS6_SPID MAS6_SPID0 | |
120 | #define MAS6_SIND 0x00000002 /* Indirect page */ | |
121 | #define MAS6_SIND_SHIFT 1 | |
122 | #define MAS6_SPID_MASK 0x3fff0000 | |
123 | #define MAS6_SPID_SHIFT 16 | |
124 | #define MAS6_ISIZE_MASK 0x00000f80 | |
125 | #define MAS6_ISIZE_SHIFT 7 | |
126 | ||
127 | #define MAS7_RPN 0xFFFFFFFF | |
128 | ||
d30f6e48 SW |
129 | #define MAS8_TGS 0x80000000 /* Guest space */ |
130 | #define MAS8_VF 0x40000000 /* Virtualization Fault */ | |
131 | #define MAS8_TLPID 0x000000ff | |
132 | ||
988cf86d KG |
133 | /* Bit definitions for MMUCFG */ |
134 | #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */ | |
135 | #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */ | |
136 | #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */ | |
137 | #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */ | |
138 | #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */ | |
139 | #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */ | |
140 | #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */ | |
141 | #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */ | |
142 | #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */ | |
143 | ||
fc4bdb35 KG |
144 | /* Bit definitions for MMUCSR0 */ |
145 | #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */ | |
146 | #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */ | |
147 | #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */ | |
148 | #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */ | |
149 | #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \ | |
150 | MMUCSR0_TLB2FI | MMUCSR0_TLB3FI) | |
151 | #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */ | |
152 | #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */ | |
153 | #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */ | |
154 | #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */ | |
155 | ||
bd491781 BH |
156 | /* MMUCFG bits */ |
157 | #define MMUCFG_MAVN_NASK 0x00000003 | |
158 | #define MMUCFG_MAVN_V1_0 0x00000000 | |
159 | #define MMUCFG_MAVN_V2_0 0x00000001 | |
160 | #define MMUCFG_NTLB_MASK 0x0000000c | |
161 | #define MMUCFG_NTLB_SHIFT 2 | |
162 | #define MMUCFG_PIDSIZE_MASK 0x000007c0 | |
163 | #define MMUCFG_PIDSIZE_SHIFT 6 | |
164 | #define MMUCFG_TWC 0x00008000 | |
165 | #define MMUCFG_LRAT 0x00010000 | |
166 | #define MMUCFG_RASIZE_MASK 0x00fe0000 | |
167 | #define MMUCFG_RASIZE_SHIFT 17 | |
168 | #define MMUCFG_LPIDSIZE_MASK 0x0f000000 | |
169 | #define MMUCFG_LPIDSIZE_SHIFT 24 | |
170 | ||
1fe1a210 BH |
171 | /* TLBnCFG encoding */ |
172 | #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */ | |
173 | #define TLBnCFG_HES 0x00002000 /* HW select supported */ | |
174 | #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */ | |
175 | #define TLBnCFG_GTWE 0x00010000 /* Guest can write */ | |
176 | #define TLBnCFG_IND 0x00020000 /* IND entries supported */ | |
177 | #define TLBnCFG_PT 0x00040000 /* Can load from page table */ | |
988cf86d KG |
178 | #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */ |
179 | #define TLBnCFG_MINSIZE_SHIFT 20 | |
180 | #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */ | |
181 | #define TLBnCFG_MAXSIZE_SHIFT 16 | |
1fe1a210 | 182 | #define TLBnCFG_ASSOC 0xff000000 /* Associativity */ |
0164c0f0 | 183 | #define TLBnCFG_ASSOC_SHIFT 24 |
1fe1a210 BH |
184 | |
185 | /* TLBnPS encoding */ | |
186 | #define TLBnPS_4K 0x00000004 | |
187 | #define TLBnPS_8K 0x00000008 | |
188 | #define TLBnPS_16K 0x00000010 | |
189 | #define TLBnPS_32K 0x00000020 | |
190 | #define TLBnPS_64K 0x00000040 | |
191 | #define TLBnPS_128K 0x00000080 | |
192 | #define TLBnPS_256K 0x00000100 | |
193 | #define TLBnPS_512K 0x00000200 | |
194 | #define TLBnPS_1M 0x00000400 | |
195 | #define TLBnPS_2M 0x00000800 | |
196 | #define TLBnPS_4M 0x00001000 | |
197 | #define TLBnPS_8M 0x00002000 | |
198 | #define TLBnPS_16M 0x00004000 | |
199 | #define TLBnPS_32M 0x00008000 | |
200 | #define TLBnPS_64M 0x00010000 | |
201 | #define TLBnPS_128M 0x00020000 | |
202 | #define TLBnPS_256M 0x00040000 | |
203 | #define TLBnPS_512M 0x00080000 | |
204 | #define TLBnPS_1G 0x00100000 | |
205 | #define TLBnPS_2G 0x00200000 | |
206 | #define TLBnPS_4G 0x00400000 | |
207 | #define TLBnPS_8G 0x00800000 | |
208 | #define TLBnPS_16G 0x01000000 | |
209 | #define TLBnPS_32G 0x02000000 | |
210 | #define TLBnPS_64G 0x04000000 | |
211 | #define TLBnPS_128G 0x08000000 | |
212 | #define TLBnPS_256G 0x10000000 | |
213 | ||
214 | /* tlbilx action encoding */ | |
215 | #define TLBILX_T_ALL 0 | |
216 | #define TLBILX_T_TID 1 | |
217 | #define TLBILX_T_FULLMATCH 3 | |
218 | #define TLBILX_T_CLASS0 4 | |
219 | #define TLBILX_T_CLASS1 5 | |
220 | #define TLBILX_T_CLASS2 6 | |
221 | #define TLBILX_T_CLASS3 7 | |
67f74c9d DG |
222 | |
223 | #ifndef __ASSEMBLY__ | |
54d5999d | 224 | #include <asm/bug.h> |
67f74c9d | 225 | |
87c656b4 LY |
226 | extern unsigned int tlbcam_index; |
227 | ||
67f74c9d | 228 | typedef struct { |
2ca8cf73 BH |
229 | unsigned int id; |
230 | unsigned int active; | |
231 | unsigned long vdso_base; | |
41151e77 BB |
232 | #ifdef CONFIG_PPC_MM_SLICES |
233 | u64 low_slices_psize; /* SLB page size encodings */ | |
234 | u64 high_slices_psize; /* 4 bits per slice for now */ | |
235 | u16 user_psize; /* page size index */ | |
236 | #endif | |
5c1f6ee9 AK |
237 | #ifdef CONFIG_PPC_64K_PAGES |
238 | /* for 4K PTE fragment support */ | |
239 | void *pte_frag; | |
240 | #endif | |
67f74c9d | 241 | } mm_context_t; |
57e2a99f BH |
242 | |
243 | /* Page size definitions, common between 32 and 64-bit | |
244 | * | |
245 | * shift : is the "PAGE_SHIFT" value for that page size | |
246 | * penc : is the pte encoding mask | |
247 | * | |
248 | */ | |
249 | struct mmu_psize_def | |
250 | { | |
251 | unsigned int shift; /* number of bits */ | |
252 | unsigned int enc; /* PTE encoding */ | |
f2b26c92 BH |
253 | unsigned int ind; /* Corresponding indirect page size shift */ |
254 | unsigned int flags; | |
255 | #define MMU_PAGE_SIZE_DIRECT 0x1 /* Supported as a direct size */ | |
256 | #define MMU_PAGE_SIZE_INDIRECT 0x2 /* Supported as an indirect size */ | |
57e2a99f BH |
257 | }; |
258 | extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; | |
259 | ||
54d5999d AK |
260 | static inline int shift_to_mmu_psize(unsigned int shift) |
261 | { | |
262 | int psize; | |
263 | ||
264 | for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) | |
265 | if (mmu_psize_defs[psize].shift == shift) | |
266 | return psize; | |
267 | return -1; | |
268 | } | |
269 | ||
270 | static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize) | |
271 | { | |
272 | if (mmu_psize_defs[mmu_psize].shift) | |
273 | return mmu_psize_defs[mmu_psize].shift; | |
274 | BUG(); | |
275 | } | |
276 | ||
57e2a99f BH |
277 | /* The page sizes use the same names as 64-bit hash but are |
278 | * constants | |
279 | */ | |
280 | #if defined(CONFIG_PPC_4K_PAGES) | |
281 | #define mmu_virtual_psize MMU_PAGE_4K | |
282 | #elif defined(CONFIG_PPC_64K_PAGES) | |
283 | #define mmu_virtual_psize MMU_PAGE_64K | |
284 | #else | |
285 | #error Unsupported page size | |
286 | #endif | |
287 | ||
288 | extern int mmu_linear_psize; | |
32a74949 | 289 | extern int mmu_vmemmap_psize; |
57e2a99f | 290 | |
28efc35f | 291 | struct tlb_core_data { |
82d86de2 SW |
292 | /* |
293 | * Per-core spinlock for e6500 TLB handlers (no tlbsrx.) | |
294 | * Must be the first struct element. | |
295 | */ | |
296 | u8 lock; | |
297 | ||
28efc35f SW |
298 | /* For software way selection, as on Freescale TLB1 */ |
299 | u8 esel_next, esel_max, esel_first; | |
28efc35f SW |
300 | }; |
301 | ||
40bd587a BH |
302 | #ifdef CONFIG_PPC64 |
303 | extern unsigned long linear_map_top; | |
28efc35f SW |
304 | extern int book3e_htw_mode; |
305 | ||
306 | #define PPC_HTW_NONE 0 | |
307 | #define PPC_HTW_IBM 1 | |
308 | #define PPC_HTW_E6500 2 | |
1f6820b4 BB |
309 | |
310 | /* | |
311 | * 64-bit booke platforms don't load the tlb in the tlb miss handler code. | |
312 | * HUGETLB_NEED_PRELOAD handles this - it causes huge_ptep_set_access_flags to | |
313 | * return 1, indicating that the tlb requires preloading. | |
314 | */ | |
315 | #define HUGETLB_NEED_PRELOAD | |
40bd587a BH |
316 | #endif |
317 | ||
67f74c9d DG |
318 | #endif /* !__ASSEMBLY__ */ |
319 | ||
d66c82ea | 320 | #endif /* _ASM_POWERPC_MMU_BOOK3E_H_ */ |