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31202345 DG |
1 | #ifndef _ASM_POWERPC_MMU_8XX_H_ |
2 | #define _ASM_POWERPC_MMU_8XX_H_ | |
3 | /* | |
4 | * PPC8xx support | |
5 | */ | |
6 | ||
7 | /* Control/status registers for the MPC8xx. | |
8 | * A write operation to these registers causes serialized access. | |
9 | * During software tablewalk, the registers used perform mask/shift-add | |
10 | * operations when written/read. A TLB entry is created when the Mx_RPN | |
11 | * is written, and the contents of several registers are used to | |
12 | * create the entry. | |
13 | */ | |
14 | #define SPRN_MI_CTR 784 /* Instruction TLB control register */ | |
15 | #define MI_GPM 0x80000000 /* Set domain manager mode */ | |
16 | #define MI_PPM 0x40000000 /* Set subpage protection */ | |
17 | #define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ | |
18 | #define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */ | |
19 | #define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ | |
20 | #define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */ | |
21 | #define MI_RESETVAL 0x00000000 /* Value of register at reset */ | |
22 | ||
23 | /* These are the Ks and Kp from the PowerPC books. For proper operation, | |
24 | * Ks = 0, Kp = 1. | |
25 | */ | |
26 | #define SPRN_MI_AP 786 | |
27 | #define MI_Ks 0x80000000 /* Should not be set */ | |
28 | #define MI_Kp 0x40000000 /* Should always be set */ | |
29 | ||
5b2753fc LC |
30 | /* |
31 | * All pages' PP exec bits are set to 000, which means Execute for Supervisor | |
32 | * and no Execute for User. | |
33 | * Then we use the APG to say whether accesses are according to Page rules, | |
34 | * "all Supervisor" rules (Exec for all) and "all User" rules (Exec for noone) | |
35 | * Therefore, we define 4 APG groups. msb is _PAGE_EXEC, lsb is _PAGE_USER | |
36 | * 0 (00) => Not User, no exec => 11 (all accesses performed as user) | |
37 | * 1 (01) => User but no exec => 11 (all accesses performed as user) | |
38 | * 2 (10) => Not User, exec => 01 (rights according to page definition) | |
39 | * 3 (11) => User, exec => 00 (all accesses performed as supervisor) | |
40 | */ | |
41 | #define MI_APG_INIT 0xf4ffffff | |
42 | ||
31202345 DG |
43 | /* The effective page number register. When read, contains the information |
44 | * about the last instruction TLB miss. When MI_RPN is written, bits in | |
45 | * this register are used to create the TLB entry. | |
46 | */ | |
47 | #define SPRN_MI_EPN 787 | |
48 | #define MI_EPNMASK 0xfffff000 /* Effective page number for entry */ | |
49 | #define MI_EVALID 0x00000200 /* Entry is valid */ | |
50 | #define MI_ASIDMASK 0x0000000f /* ASID match value */ | |
51 | /* Reset value is undefined */ | |
52 | ||
53 | /* A "level 1" or "segment" or whatever you want to call it register. | |
54 | * For the instruction TLB, it contains bits that get loaded into the | |
55 | * TLB entry when the MI_RPN is written. | |
56 | */ | |
57 | #define SPRN_MI_TWC 789 | |
58 | #define MI_APG 0x000001e0 /* Access protection group (0) */ | |
59 | #define MI_GUARDED 0x00000010 /* Guarded storage */ | |
60 | #define MI_PSMASK 0x0000000c /* Mask of page size bits */ | |
61 | #define MI_PS8MEG 0x0000000c /* 8M page size */ | |
62 | #define MI_PS512K 0x00000004 /* 512K page size */ | |
63 | #define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */ | |
64 | #define MI_SVALID 0x00000001 /* Segment entry is valid */ | |
65 | /* Reset value is undefined */ | |
66 | ||
67 | /* Real page number. Defined by the pte. Writing this register | |
68 | * causes a TLB entry to be created for the instruction TLB, using | |
69 | * additional information from the MI_EPN, and MI_TWC registers. | |
70 | */ | |
71 | #define SPRN_MI_RPN 790 | |
959d6173 | 72 | #define MI_SPS16K 0x00000008 /* Small page size (0 = 4k, 1 = 16k) */ |
31202345 DG |
73 | |
74 | /* Define an RPN value for mapping kernel memory to large virtual | |
75 | * pages for boot initialization. This has real page number of 0, | |
76 | * large page size, shared page, cache enabled, and valid. | |
77 | * Also mark all subpages valid and write access. | |
78 | */ | |
79 | #define MI_BOOTINIT 0x000001fd | |
80 | ||
81 | #define SPRN_MD_CTR 792 /* Data TLB control register */ | |
82 | #define MD_GPM 0x80000000 /* Set domain manager mode */ | |
83 | #define MD_PPM 0x40000000 /* Set subpage protection */ | |
84 | #define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ | |
85 | #define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */ | |
86 | #define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */ | |
87 | #define MD_TWAM 0x04000000 /* Use 4K page hardware assist */ | |
88 | #define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ | |
89 | #define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */ | |
90 | #define MD_RESETVAL 0x04000000 /* Value of register at reset */ | |
91 | ||
92 | #define SPRN_M_CASID 793 /* Address space ID (context) to match */ | |
93 | #define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */ | |
94 | ||
95 | ||
96 | /* These are the Ks and Kp from the PowerPC books. For proper operation, | |
97 | * Ks = 0, Kp = 1. | |
98 | */ | |
99 | #define SPRN_MD_AP 794 | |
100 | #define MD_Ks 0x80000000 /* Should not be set */ | |
101 | #define MD_Kp 0x40000000 /* Should always be set */ | |
102 | ||
5b2753fc LC |
103 | /* |
104 | * All pages' PP data bits are set to either 000 or 011, which means | |
105 | * respectively RW for Supervisor and no access for User, or RO for | |
106 | * Supervisor and no access for user. | |
107 | * Then we use the APG to say whether accesses are according to Page rules or | |
108 | * "all Supervisor" rules (Access to all) | |
109 | * Therefore, we define 2 APG groups. lsb is _PAGE_USER | |
110 | * 0 => No user => 01 (all accesses performed according to page definition) | |
111 | * 1 => User => 00 (all accesses performed as supervisor | |
112 | * according to page definition) | |
113 | */ | |
114 | #define MD_APG_INIT 0x4fffffff | |
115 | ||
31202345 DG |
116 | /* The effective page number register. When read, contains the information |
117 | * about the last instruction TLB miss. When MD_RPN is written, bits in | |
118 | * this register are used to create the TLB entry. | |
119 | */ | |
120 | #define SPRN_MD_EPN 795 | |
121 | #define MD_EPNMASK 0xfffff000 /* Effective page number for entry */ | |
122 | #define MD_EVALID 0x00000200 /* Entry is valid */ | |
123 | #define MD_ASIDMASK 0x0000000f /* ASID match value */ | |
124 | /* Reset value is undefined */ | |
125 | ||
126 | /* The pointer to the base address of the first level page table. | |
127 | * During a software tablewalk, reading this register provides the address | |
128 | * of the entry associated with MD_EPN. | |
129 | */ | |
130 | #define SPRN_M_TWB 796 | |
131 | #define M_L1TB 0xfffff000 /* Level 1 table base address */ | |
132 | #define M_L1INDX 0x00000ffc /* Level 1 index, when read */ | |
133 | /* Reset value is undefined */ | |
134 | ||
135 | /* A "level 1" or "segment" or whatever you want to call it register. | |
136 | * For the data TLB, it contains bits that get loaded into the TLB entry | |
137 | * when the MD_RPN is written. It is also provides the hardware assist | |
138 | * for finding the PTE address during software tablewalk. | |
139 | */ | |
140 | #define SPRN_MD_TWC 797 | |
141 | #define MD_L2TB 0xfffff000 /* Level 2 table base address */ | |
142 | #define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */ | |
143 | #define MD_APG 0x000001e0 /* Access protection group (0) */ | |
144 | #define MD_GUARDED 0x00000010 /* Guarded storage */ | |
145 | #define MD_PSMASK 0x0000000c /* Mask of page size bits */ | |
146 | #define MD_PS8MEG 0x0000000c /* 8M page size */ | |
147 | #define MD_PS512K 0x00000004 /* 512K page size */ | |
148 | #define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */ | |
149 | #define MD_WT 0x00000002 /* Use writethrough page attribute */ | |
150 | #define MD_SVALID 0x00000001 /* Segment entry is valid */ | |
151 | /* Reset value is undefined */ | |
152 | ||
153 | ||
154 | /* Real page number. Defined by the pte. Writing this register | |
155 | * causes a TLB entry to be created for the data TLB, using | |
156 | * additional information from the MD_EPN, and MD_TWC registers. | |
157 | */ | |
158 | #define SPRN_MD_RPN 798 | |
959d6173 | 159 | #define MD_SPS16K 0x00000008 /* Small page size (0 = 4k, 1 = 16k) */ |
31202345 DG |
160 | |
161 | /* This is a temporary storage register that could be used to save | |
162 | * a processor working register during a tablewalk. | |
163 | */ | |
164 | #define SPRN_M_TW 799 | |
165 | ||
166 | #ifndef __ASSEMBLY__ | |
31202345 | 167 | typedef struct { |
2ca8cf73 BH |
168 | unsigned int id; |
169 | unsigned int active; | |
31202345 DG |
170 | unsigned long vdso_base; |
171 | } mm_context_t; | |
f86ef74e CL |
172 | |
173 | #define PHYS_IMMR_BASE (mfspr(SPRN_IMMR) & 0xfff80000) | |
174 | #define VIRT_IMMR_BASE (__fix_to_virt(FIX_IMMR_BASE)) | |
4b914286 CL |
175 | |
176 | /* Page size definitions, common between 32 and 64-bit | |
177 | * | |
178 | * shift : is the "PAGE_SHIFT" value for that page size | |
179 | * penc : is the pte encoding mask | |
180 | * | |
181 | */ | |
182 | struct mmu_psize_def { | |
183 | unsigned int shift; /* number of bits */ | |
184 | unsigned int enc; /* PTE encoding */ | |
185 | unsigned int ind; /* Corresponding indirect page size shift */ | |
186 | unsigned int flags; | |
187 | #define MMU_PAGE_SIZE_DIRECT 0x1 /* Supported as a direct size */ | |
188 | #define MMU_PAGE_SIZE_INDIRECT 0x2 /* Supported as an indirect size */ | |
189 | }; | |
190 | ||
191 | extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; | |
192 | ||
193 | static inline int shift_to_mmu_psize(unsigned int shift) | |
194 | { | |
195 | int psize; | |
196 | ||
197 | for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) | |
198 | if (mmu_psize_defs[psize].shift == shift) | |
199 | return psize; | |
200 | return -1; | |
201 | } | |
202 | ||
203 | static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize) | |
204 | { | |
205 | if (mmu_psize_defs[mmu_psize].shift) | |
206 | return mmu_psize_defs[mmu_psize].shift; | |
207 | BUG(); | |
208 | } | |
209 | ||
31202345 DG |
210 | #endif /* !__ASSEMBLY__ */ |
211 | ||
7ee5cf6b | 212 | #if defined(CONFIG_PPC_4K_PAGES) |
25d21ad6 | 213 | #define mmu_virtual_psize MMU_PAGE_4K |
7ee5cf6b | 214 | #elif defined(CONFIG_PPC_16K_PAGES) |
86c3b16e LC |
215 | #define mmu_virtual_psize MMU_PAGE_16K |
216 | #else | |
217 | #error "Unsupported PAGE_SIZE" | |
218 | #endif | |
219 | ||
25d21ad6 BH |
220 | #define mmu_linear_psize MMU_PAGE_8M |
221 | ||
31202345 | 222 | #endif /* _ASM_POWERPC_MMU_8XX_H_ */ |