[linux-2.6-block.git] / arch / powerpc / include / asm / kvm_book3s_64.h

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2, as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 *
 * Copyright SUSE Linux Products GmbH 2010
 *
 * Authors: Alexander Graf <agraf@suse.de>
 */

#ifndef __ASM_KVM_BOOK3S_64_H__
#define __ASM_KVM_BOOK3S_64_H__

#ifdef CONFIG_KVM_BOOK3S_PR
static inline struct kvmppc_book3s_shadow_vcpu *svcpu_get(struct kvm_vcpu *vcpu)
{
	preempt_disable();
	return &get_paca()->shadow_vcpu;
}

static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu)
{
	preempt_enable();
}
#endif

#define SPAPR_TCE_SHIFT		12

#ifdef CONFIG_KVM_BOOK3S_64_HV
#define KVM_DEFAULT_HPT_ORDER	24	/* 16MB HPT by default */
extern int kvm_hpt_order;		/* order of preallocated HPTs */
#endif

#define VRMA_VSID	0x1ffffffUL	/* 1TB VSID reserved for VRMA */

/*
 * We use a lock bit in HPTE dword 0 to synchronize updates and
 * accesses to each HPTE, and another bit to indicate non-present
 * HPTEs.
 */
#define HPTE_V_HVLOCK	0x40UL
#define HPTE_V_ABSENT	0x20UL

/*
 * We use this bit in the guest_rpte field of the revmap entry
 * to indicate a modified HPTE.
 */
#define HPTE_GR_MODIFIED	(1ul << 62)

/* These bits are reserved in the guest view of the HPTE */
#define HPTE_GR_RESERVED	HPTE_GR_MODIFIED

static inline long try_lock_hpte(unsigned long *hpte, unsigned long bits)
{
	unsigned long tmp, old;

	asm volatile("	ldarx	%0,0,%2\n"
		     "	and.	%1,%0,%3\n"
		     "	bne	2f\n"
		     "	ori	%0,%0,%4\n"
		     "  stdcx.	%0,0,%2\n"
		     "	beq+	2f\n"
		     "	mr	%1,%3\n"
		     "2:	isync"
		     : "=&r" (tmp), "=&r" (old)
		     : "r" (hpte), "r" (bits), "i" (HPTE_V_HVLOCK)
		     : "cc", "memory");
	return old == 0;
}

static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
					     unsigned long pte_index)
{
	unsigned long rb, va_low;

	rb = (v & ~0x7fUL) << 16;		/* AVA field */
	va_low = pte_index >> 3;
	if (v & HPTE_V_SECONDARY)
		va_low = ~va_low;
	/* xor vsid from AVA */
	if (!(v & HPTE_V_1TB_SEG))
		va_low ^= v >> 12;
	else
		va_low ^= v >> 24;
	va_low &= 0x7ff;
	if (v & HPTE_V_LARGE) {
		rb |= 1;			/* L field */
		if (cpu_has_feature(CPU_FTR_ARCH_206) &&
		    (r & 0xff000)) {
			/* non-16MB large page, must be 64k */
			/* (masks depend on page size) */
			rb |= 0x1000;		/* page encoding in LP field */
			rb |= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */
			rb |= (va_low & 0xfe);	/* AVAL field (P7 doesn't seem to care) */
		}
	} else {
		/* 4kB page */
		rb |= (va_low & 0x7ff) << 12;	/* remaining 11b of VA */
	}
	rb |= (v >> 54) & 0x300;		/* B field */
	return rb;
}

static inline unsigned long hpte_page_size(unsigned long h, unsigned long l)
{
	/* only handle 4k, 64k and 16M pages for now */
	if (!(h & HPTE_V_LARGE))
		return 1ul << 12;		/* 4k page */
	if ((l & 0xf000) == 0x1000 && cpu_has_feature(CPU_FTR_ARCH_206))
		return 1ul << 16;		/* 64k page */
	if ((l & 0xff000) == 0)
		return 1ul << 24;		/* 16M page */
	return 0;				/* error */
}

static inline unsigned long hpte_rpn(unsigned long ptel, unsigned long psize)
{
	return ((ptel & HPTE_R_RPN) & ~(psize - 1)) >> PAGE_SHIFT;
}

static inline int hpte_is_writable(unsigned long ptel)
{
	unsigned long pp = ptel & (HPTE_R_PP0 | HPTE_R_PP);

	return pp != PP_RXRX && pp != PP_RXXX;
}

static inline unsigned long hpte_make_readonly(unsigned long ptel)
{
	if ((ptel & HPTE_R_PP0) || (ptel & HPTE_R_PP) == PP_RWXX)
		ptel = (ptel & ~HPTE_R_PP) | PP_RXXX;
	else
		ptel |= PP_RXRX;
	return ptel;
}

static inline int hpte_cache_flags_ok(unsigned long ptel, unsigned long io_type)
{
	unsigned int wimg = ptel & HPTE_R_WIMG;

	/* Handle SAO */
	if (wimg == (HPTE_R_W | HPTE_R_I | HPTE_R_M) &&
	    cpu_has_feature(CPU_FTR_ARCH_206))
		wimg = HPTE_R_M;

	if (!io_type)
		return wimg == HPTE_R_M;

	return (wimg & (HPTE_R_W | HPTE_R_I)) == io_type;
}

/*
 * Lock and read a linux PTE.  If it's present and writable, atomically
 * set dirty and referenced bits and return the PTE, otherwise return 0.
 */
static inline pte_t kvmppc_read_update_linux_pte(pte_t *p, int writing)
{
	pte_t pte, tmp;

	/* wait until _PAGE_BUSY is clear then set it atomically */
	__asm__ __volatile__ (
		"1:	ldarx	%0,0,%3\n"
		"	andi.	%1,%0,%4\n"
		"	bne-	1b\n"
		"	ori	%1,%0,%4\n"
		"	stdcx.	%1,0,%3\n"
		"	bne-	1b"
		: "=&r" (pte), "=&r" (tmp), "=m" (*p)
		: "r" (p), "i" (_PAGE_BUSY)
		: "cc");

	if (pte_present(pte)) {
		pte = pte_mkyoung(pte);
		if (writing && pte_write(pte))
			pte = pte_mkdirty(pte);
	}

	*p = pte;	/* clears _PAGE_BUSY */

	return pte;
}

/* Return HPTE cache control bits corresponding to Linux pte bits */
static inline unsigned long hpte_cache_bits(unsigned long pte_val)
{
#if _PAGE_NO_CACHE == HPTE_R_I && _PAGE_WRITETHRU == HPTE_R_W
	return pte_val & (HPTE_R_W | HPTE_R_I);
#else
	return ((pte_val & _PAGE_NO_CACHE) ? HPTE_R_I : 0) +
		((pte_val & _PAGE_WRITETHRU) ? HPTE_R_W : 0);
#endif
}

static inline bool hpte_read_permission(unsigned long pp, unsigned long key)
{
	if (key)
		return PP_RWRX <= pp && pp <= PP_RXRX;
	return 1;
}

static inline bool hpte_write_permission(unsigned long pp, unsigned long key)
{
	if (key)
		return pp == PP_RWRW;
	return pp <= PP_RWRW;
}

static inline int hpte_get_skey_perm(unsigned long hpte_r, unsigned long amr)
{
	unsigned long skey;

	skey = ((hpte_r & HPTE_R_KEY_HI) >> 57) |
		((hpte_r & HPTE_R_KEY_LO) >> 9);
	return (amr >> (62 - 2 * skey)) & 3;
}

static inline void lock_rmap(unsigned long *rmap)
{
	do {
		while (test_bit(KVMPPC_RMAP_LOCK_BIT, rmap))
			cpu_relax();
	} while (test_and_set_bit_lock(KVMPPC_RMAP_LOCK_BIT, rmap));
}

static inline void unlock_rmap(unsigned long *rmap)
{
	__clear_bit_unlock(KVMPPC_RMAP_LOCK_BIT, rmap);
}

static inline bool slot_is_aligned(struct kvm_memory_slot *memslot,
				   unsigned long pagesize)
{
	unsigned long mask = (pagesize >> PAGE_SHIFT) - 1;

	if (pagesize <= PAGE_SIZE)
		return 1;
	return !(memslot->base_gfn & mask) && !(memslot->npages & mask);
}

/*
 * This works for 4k, 64k and 16M pages on POWER7,
 * and 4k and 16M pages on PPC970.
 */
static inline unsigned long slb_pgsize_encoding(unsigned long psize)
{
	unsigned long senc = 0;

	if (psize > 0x1000) {
		senc = SLB_VSID_L;
		if (psize == 0x10000)
			senc |= SLB_VSID_LP_01;
	}
	return senc;
}

static inline int is_vrma_hpte(unsigned long hpte_v)
{
	return (hpte_v & ~0xffffffUL) ==
		(HPTE_V_1TB_SEG | (VRMA_VSID << (40 - 16)));
}

#ifdef CONFIG_KVM_BOOK3S_64_HV
/*
 * Note modification of an HPTE; set the HPTE modified bit
 * if anyone is interested.
 */
static inline void note_hpte_modification(struct kvm *kvm,
					  struct revmap_entry *rev)
{
	if (atomic_read(&kvm->arch.hpte_mod_interest))
		rev->guest_rpte |= HPTE_GR_MODIFIED;
}
#endif /* CONFIG_KVM_BOOK3S_64_HV */

#endif /* __ASM_KVM_BOOK3S_64_H__ */
Commit	Line	Data
3ae07890 AG	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License, version 2, as
	4	* published by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope that it will be useful,
	7	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	8	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	9	* GNU General Public License for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License
	12	* along with this program; if not, write to the Free Software
	13	* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
	14	*
	15	* Copyright SUSE Linux Products GmbH 2010
	16	*
	17	* Authors: Alexander Graf <agraf@suse.de>
	18	*/
	19
	20	#ifndef __ASM_KVM_BOOK3S_64_H__
	21	#define __ASM_KVM_BOOK3S_64_H__
	22
de56a948	23	#ifdef CONFIG_KVM_BOOK3S_PR
468a12c2	24	static inline struct kvmppc_book3s_shadow_vcpu svcpu_get(struct kvm_vcpu vcpu)
3ae07890	25	{
468a12c2	26	preempt_disable();
3ae07890 AG	27	return &get_paca()->shadow_vcpu;
3ae07890 AG	28	}
468a12c2 AG	29
	30	static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu)
	31	{
	32	preempt_enable();
	33	}
de56a948	34	#endif
3ae07890	35
54738c09 DG	36	#define SPAPR_TCE_SHIFT 12
54738c09 DG	37
8936dda4	38	#ifdef CONFIG_KVM_BOOK3S_64_HV
32fad281 PM	39	#define KVM_DEFAULT_HPT_ORDER 24 /* 16MB HPT by default */
32fad281 PM	40	extern int kvm_hpt_order; /* order of preallocated HPTs */
8936dda4 PM	41	#endif
8936dda4 PM	42
697d3899 PM	43	#define VRMA_VSID 0x1ffffffUL /* 1TB VSID reserved for VRMA */
697d3899 PM	44
075295dd PM	45	/*
	46	* We use a lock bit in HPTE dword 0 to synchronize updates and
	47	* accesses to each HPTE, and another bit to indicate non-present
	48	* HPTEs.
	49	*/
	50	#define HPTE_V_HVLOCK 0x40UL
697d3899	51	#define HPTE_V_ABSENT 0x20UL
075295dd	52
44e5f6be PM	53	/*
	54	* We use this bit in the guest_rpte field of the revmap entry
	55	* to indicate a modified HPTE.
	56	*/
	57	#define HPTE_GR_MODIFIED (1ul << 62)
	58
	59	/* These bits are reserved in the guest view of the HPTE */
	60	#define HPTE_GR_RESERVED HPTE_GR_MODIFIED
	61
075295dd PM	62	static inline long try_lock_hpte(unsigned long *hpte, unsigned long bits)
	63	{
	64	unsigned long tmp, old;
	65
	66	asm volatile(" ldarx %0,0,%2\n"
	67	" and. %1,%0,%3\n"
	68	" bne 2f\n"
	69	" ori %0,%0,%4\n"
	70	" stdcx. %0,0,%2\n"
	71	" beq+ 2f\n"
8b5869ad	72	" mr %1,%3\n"
075295dd PM	73	"2: isync"
	74	: "=&r" (tmp), "=&r" (old)
	75	: "r" (hpte), "r" (bits), "i" (HPTE_V_HVLOCK)
	76	: "cc", "memory");
	77	return old == 0;
	78	}
	79
36cc66d6 AS	80	static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
	81	unsigned long pte_index)
	82	{
	83	unsigned long rb, va_low;
	84
	85	rb = (v & ~0x7fUL) << 16; /* AVA field */
	86	va_low = pte_index >> 3;
	87	if (v & HPTE_V_SECONDARY)
	88	va_low = ~va_low;
	89	/* xor vsid from AVA */
	90	if (!(v & HPTE_V_1TB_SEG))
	91	va_low ^= v >> 12;
	92	else
	93	va_low ^= v >> 24;
	94	va_low &= 0x7ff;
	95	if (v & HPTE_V_LARGE) {
	96	rb \|= 1; /* L field */
	97	if (cpu_has_feature(CPU_FTR_ARCH_206) &&
	98	(r & 0xff000)) {
	99	/* non-16MB large page, must be 64k */
	100	/* (masks depend on page size) */
	101	rb \|= 0x1000; /* page encoding in LP field */
	102	rb \|= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */
	103	rb \|= (va_low & 0xfe); /* AVAL field (P7 doesn't seem to care) */
	104	}
	105	} else {
	106	/* 4kB page */
	107	rb \|= (va_low & 0x7ff) << 12; /* remaining 11b of VA */
	108	}
	109	rb \|= (v >> 54) & 0x300; /* B field */
	110	return rb;
	111	}
	112
c77162de PM	113	static inline unsigned long hpte_page_size(unsigned long h, unsigned long l)
	114	{
	115	/* only handle 4k, 64k and 16M pages for now */
	116	if (!(h & HPTE_V_LARGE))
	117	return 1ul << 12; /* 4k page */
	118	if ((l & 0xf000) == 0x1000 && cpu_has_feature(CPU_FTR_ARCH_206))
	119	return 1ul << 16; /* 64k page */
	120	if ((l & 0xff000) == 0)
	121	return 1ul << 24; /* 16M page */
	122	return 0; /* error */
	123	}
	124
06ce2c63 PM	125	static inline unsigned long hpte_rpn(unsigned long ptel, unsigned long psize)
	126	{
	127	return ((ptel & HPTE_R_RPN) & ~(psize - 1)) >> PAGE_SHIFT;
	128	}
	129
4cf302bc PM	130	static inline int hpte_is_writable(unsigned long ptel)
	131	{
	132	unsigned long pp = ptel & (HPTE_R_PP0 \| HPTE_R_PP);
	133
	134	return pp != PP_RXRX && pp != PP_RXXX;
	135	}
	136
	137	static inline unsigned long hpte_make_readonly(unsigned long ptel)
	138	{
	139	if ((ptel & HPTE_R_PP0) \|\| (ptel & HPTE_R_PP) == PP_RWXX)
	140	ptel = (ptel & ~HPTE_R_PP) \| PP_RXXX;
	141	else
	142	ptel \|= PP_RXRX;
	143	return ptel;
	144	}
	145
9d0ef5ea PM	146	static inline int hpte_cache_flags_ok(unsigned long ptel, unsigned long io_type)
	147	{
	148	unsigned int wimg = ptel & HPTE_R_WIMG;
	149
	150	/* Handle SAO */
	151	if (wimg == (HPTE_R_W \| HPTE_R_I \| HPTE_R_M) &&
	152	cpu_has_feature(CPU_FTR_ARCH_206))
	153	wimg = HPTE_R_M;
	154
	155	if (!io_type)
	156	return wimg == HPTE_R_M;
	157
	158	return (wimg & (HPTE_R_W \| HPTE_R_I)) == io_type;
	159	}
	160
342d3db7 PM	161	/*
	162	* Lock and read a linux PTE. If it's present and writable, atomically
	163	* set dirty and referenced bits and return the PTE, otherwise return 0.
	164	*/
4cf302bc	165	static inline pte_t kvmppc_read_update_linux_pte(pte_t *p, int writing)
342d3db7 PM	166	{
	167	pte_t pte, tmp;
	168
	169	/* wait until _PAGE_BUSY is clear then set it atomically */
	170	__asm__ __volatile__ (
	171	"1: ldarx %0,0,%3\n"
	172	" andi. %1,%0,%4\n"
	173	" bne- 1b\n"
	174	" ori %1,%0,%4\n"
	175	" stdcx. %1,0,%3\n"
	176	" bne- 1b"
	177	: "=&r" (pte), "=&r" (tmp), "=m" (*p)
	178	: "r" (p), "i" (_PAGE_BUSY)
	179	: "cc");
	180
	181	if (pte_present(pte)) {
	182	pte = pte_mkyoung(pte);
4cf302bc	183	if (writing && pte_write(pte))
342d3db7 PM	184	pte = pte_mkdirty(pte);
	185	}
	186
	187	p = pte; / clears _PAGE_BUSY */
	188
	189	return pte;
	190	}
	191
9d0ef5ea PM	192	/* Return HPTE cache control bits corresponding to Linux pte bits */
	193	static inline unsigned long hpte_cache_bits(unsigned long pte_val)
	194	{
	195	#if _PAGE_NO_CACHE == HPTE_R_I && _PAGE_WRITETHRU == HPTE_R_W
	196	return pte_val & (HPTE_R_W \| HPTE_R_I);
	197	#else
	198	return ((pte_val & _PAGE_NO_CACHE) ? HPTE_R_I : 0) +
	199	((pte_val & _PAGE_WRITETHRU) ? HPTE_R_W : 0);
	200	#endif
	201	}
	202
697d3899 PM	203	static inline bool hpte_read_permission(unsigned long pp, unsigned long key)
	204	{
	205	if (key)
	206	return PP_RWRX <= pp && pp <= PP_RXRX;
	207	return 1;
	208	}
	209
	210	static inline bool hpte_write_permission(unsigned long pp, unsigned long key)
	211	{
	212	if (key)
	213	return pp == PP_RWRW;
	214	return pp <= PP_RWRW;
	215	}
	216
	217	static inline int hpte_get_skey_perm(unsigned long hpte_r, unsigned long amr)
	218	{
	219	unsigned long skey;
	220
	221	skey = ((hpte_r & HPTE_R_KEY_HI) >> 57) \|
	222	((hpte_r & HPTE_R_KEY_LO) >> 9);
	223	return (amr >> (62 - 2 * skey)) & 3;
	224	}
	225
06ce2c63 PM	226	static inline void lock_rmap(unsigned long *rmap)
	227	{
	228	do {
	229	while (test_bit(KVMPPC_RMAP_LOCK_BIT, rmap))
	230	cpu_relax();
	231	} while (test_and_set_bit_lock(KVMPPC_RMAP_LOCK_BIT, rmap));
	232	}
	233
	234	static inline void unlock_rmap(unsigned long *rmap)
	235	{
	236	__clear_bit_unlock(KVMPPC_RMAP_LOCK_BIT, rmap);
	237	}
	238
da9d1d7f PM	239	static inline bool slot_is_aligned(struct kvm_memory_slot *memslot,
	240	unsigned long pagesize)
	241	{
	242	unsigned long mask = (pagesize >> PAGE_SHIFT) - 1;
	243
	244	if (pagesize <= PAGE_SIZE)
	245	return 1;
	246	return !(memslot->base_gfn & mask) && !(memslot->npages & mask);
	247	}
	248
a2932923 PM	249	/*
	250	* This works for 4k, 64k and 16M pages on POWER7,
	251	* and 4k and 16M pages on PPC970.
	252	*/
	253	static inline unsigned long slb_pgsize_encoding(unsigned long psize)
	254	{
	255	unsigned long senc = 0;
	256
	257	if (psize > 0x1000) {
	258	senc = SLB_VSID_L;
	259	if (psize == 0x10000)
	260	senc \|= SLB_VSID_LP_01;
	261	}
	262	return senc;
	263	}
	264
	265	static inline int is_vrma_hpte(unsigned long hpte_v)
	266	{
	267	return (hpte_v & ~0xffffffUL) ==
	268	(HPTE_V_1TB_SEG \| (VRMA_VSID << (40 - 16)));
	269	}
	270
a1b4a0f6 PM	271	#ifdef CONFIG_KVM_BOOK3S_64_HV
	272	/*
	273	* Note modification of an HPTE; set the HPTE modified bit
	274	* if anyone is interested.
	275	*/
	276	static inline void note_hpte_modification(struct kvm *kvm,
	277	struct revmap_entry *rev)
	278	{
	279	if (atomic_read(&kvm->arch.hpte_mod_interest))
	280	rev->guest_rpte \|= HPTE_GR_MODIFIED;
	281	}
	282	#endif /* CONFIG_KVM_BOOK3S_64_HV */
	283
3ae07890	284	#endif /* __ASM_KVM_BOOK3S_64_H__ */