[linux-2.6-block.git] / arch / powerpc / include / asm / iommu.h

/*
 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
 * Rewrite, cleanup:
 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

#ifndef _ASM_IOMMU_H
#define _ASM_IOMMU_H
#ifdef __KERNEL__

#include <linux/compiler.h>
#include <linux/spinlock.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/bitops.h>
#include <asm/machdep.h>
#include <asm/types.h>
#include <asm/pci-bridge.h>
#include <asm/asm-const.h>

#define IOMMU_PAGE_SHIFT_4K      12
#define IOMMU_PAGE_SIZE_4K       (ASM_CONST(1) << IOMMU_PAGE_SHIFT_4K)
#define IOMMU_PAGE_MASK_4K       (~((1 << IOMMU_PAGE_SHIFT_4K) - 1))
#define IOMMU_PAGE_ALIGN_4K(addr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE_4K)

#define IOMMU_PAGE_SIZE(tblptr) (ASM_CONST(1) << (tblptr)->it_page_shift)
#define IOMMU_PAGE_MASK(tblptr) (~((1 << (tblptr)->it_page_shift) - 1))
#define IOMMU_PAGE_ALIGN(addr, tblptr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE(tblptr))

/* Boot time flags */
extern int iommu_is_off;
extern int iommu_force_on;

struct iommu_table_ops {
	/*
	 * When called with direction==DMA_NONE, it is equal to clear().
	 * uaddr is a linear map address.
	 */
	int (*set)(struct iommu_table *tbl,
			long index, long npages,
			unsigned long uaddr,
			enum dma_data_direction direction,
			unsigned long attrs);
#ifdef CONFIG_IOMMU_API
	/*
	 * Exchanges existing TCE with new TCE plus direction bits;
	 * returns old TCE and DMA direction mask.
	 * @tce is a physical address.
	 */
	int (*exchange)(struct iommu_table *tbl,
			long index,
			unsigned long *hpa,
			enum dma_data_direction *direction);
	/* Real mode */
	int (*exchange_rm)(struct iommu_table *tbl,
			long index,
			unsigned long *hpa,
			enum dma_data_direction *direction);

	__be64 *(*useraddrptr)(struct iommu_table *tbl, long index, bool alloc);
#endif
	void (*clear)(struct iommu_table *tbl,
			long index, long npages);
	/* get() returns a physical address */
	unsigned long (*get)(struct iommu_table *tbl, long index);
	void (*flush)(struct iommu_table *tbl);
	void (*free)(struct iommu_table *tbl);
};

/* These are used by VIO */
extern struct iommu_table_ops iommu_table_lpar_multi_ops;
extern struct iommu_table_ops iommu_table_pseries_ops;

/*
 * IOMAP_MAX_ORDER defines the largest contiguous block
 * of dma space we can get.  IOMAP_MAX_ORDER = 13
 * allows up to 2**12 pages (4096 * 4096) = 16 MB
 */
#define IOMAP_MAX_ORDER		13

#define IOMMU_POOL_HASHBITS	2
#define IOMMU_NR_POOLS		(1 << IOMMU_POOL_HASHBITS)

struct iommu_pool {
	unsigned long start;
	unsigned long end;
	unsigned long hint;
	spinlock_t lock;
} ____cacheline_aligned_in_smp;

struct iommu_table {
	unsigned long  it_busno;     /* Bus number this table belongs to */
	unsigned long  it_size;      /* Size of iommu table in entries */
	unsigned long  it_indirect_levels;
	unsigned long  it_level_size;
	unsigned long  it_allocated_size;
	unsigned long  it_offset;    /* Offset into global table */
	unsigned long  it_base;      /* mapped address of tce table */
	unsigned long  it_index;     /* which iommu table this is */
	unsigned long  it_type;      /* type: PCI or Virtual Bus */
	unsigned long  it_blocksize; /* Entries in each block (cacheline) */
	unsigned long  poolsize;
	unsigned long  nr_pools;
	struct iommu_pool large_pool;
	struct iommu_pool pools[IOMMU_NR_POOLS];
	unsigned long *it_map;       /* A simple allocation bitmap for now */
	unsigned long  it_page_shift;/* table iommu page size */
	struct list_head it_group_list;/* List of iommu_table_group_link */
	__be64 *it_userspace; /* userspace view of the table */
	struct iommu_table_ops *it_ops;
	struct kref    it_kref;
	int it_nid;
};

#define IOMMU_TABLE_USERSPACE_ENTRY_RO(tbl, entry) \
		((tbl)->it_ops->useraddrptr((tbl), (entry), false))
#define IOMMU_TABLE_USERSPACE_ENTRY(tbl, entry) \
		((tbl)->it_ops->useraddrptr((tbl), (entry), true))

/* Pure 2^n version of get_order */
static inline __attribute_const__
int get_iommu_order(unsigned long size, struct iommu_table *tbl)
{
	return __ilog2((size - 1) >> tbl->it_page_shift) + 1;
}


struct scatterlist;

#ifdef CONFIG_PPC64

static inline void set_iommu_table_base(struct device *dev,
					struct iommu_table *base)
{
	dev->archdata.iommu_table_base = base;
}

static inline void *get_iommu_table_base(struct device *dev)
{
	return dev->archdata.iommu_table_base;
}

extern int dma_iommu_dma_supported(struct device *dev, u64 mask);

extern struct iommu_table *iommu_tce_table_get(struct iommu_table *tbl);
extern int iommu_tce_table_put(struct iommu_table *tbl);

/* Initializes an iommu_table based in values set in the passed-in
 * structure
 */
extern struct iommu_table *iommu_init_table(struct iommu_table * tbl,
					    int nid);
#define IOMMU_TABLE_GROUP_MAX_TABLES	2

struct iommu_table_group;

struct iommu_table_group_ops {
	unsigned long (*get_table_size)(
			__u32 page_shift,
			__u64 window_size,
			__u32 levels);
	long (*create_table)(struct iommu_table_group *table_group,
			int num,
			__u32 page_shift,
			__u64 window_size,
			__u32 levels,
			struct iommu_table **ptbl);
	long (*set_window)(struct iommu_table_group *table_group,
			int num,
			struct iommu_table *tblnew);
	long (*unset_window)(struct iommu_table_group *table_group,
			int num);
	/* Switch ownership from platform code to external user (e.g. VFIO) */
	void (*take_ownership)(struct iommu_table_group *table_group);
	/* Switch ownership from external user (e.g. VFIO) back to core */
	void (*release_ownership)(struct iommu_table_group *table_group);
};

struct iommu_table_group_link {
	struct list_head next;
	struct rcu_head rcu;
	struct iommu_table_group *table_group;
};

struct iommu_table_group {
	/* IOMMU properties */
	__u32 tce32_start;
	__u32 tce32_size;
	__u64 pgsizes; /* Bitmap of supported page sizes */
	__u32 max_dynamic_windows_supported;
	__u32 max_levels;

	struct iommu_group *group;
	struct iommu_table *tables[IOMMU_TABLE_GROUP_MAX_TABLES];
	struct iommu_table_group_ops *ops;
};

#ifdef CONFIG_IOMMU_API

extern void iommu_register_group(struct iommu_table_group *table_group,
				 int pci_domain_number, unsigned long pe_num);
extern int iommu_add_device(struct iommu_table_group *table_group,
		struct device *dev);
extern void iommu_del_device(struct device *dev);
extern long iommu_tce_xchg(struct mm_struct *mm, struct iommu_table *tbl,
		unsigned long entry, unsigned long *hpa,
		enum dma_data_direction *direction);
#else
static inline void iommu_register_group(struct iommu_table_group *table_group,
					int pci_domain_number,
					unsigned long pe_num)
{
}

static inline int iommu_add_device(struct iommu_table_group *table_group,
		struct device *dev)
{
	return 0;
}

static inline void iommu_del_device(struct device *dev)
{
}
#endif /* !CONFIG_IOMMU_API */

u64 dma_iommu_get_required_mask(struct device *dev);
#else

static inline void *get_iommu_table_base(struct device *dev)
{
	return NULL;
}

static inline int dma_iommu_dma_supported(struct device *dev, u64 mask)
{
	return 0;
}

#endif /* CONFIG_PPC64 */

extern int ppc_iommu_map_sg(struct device *dev, struct iommu_table *tbl,
			    struct scatterlist *sglist, int nelems,
			    unsigned long mask,
			    enum dma_data_direction direction,
			    unsigned long attrs);
extern void ppc_iommu_unmap_sg(struct iommu_table *tbl,
			       struct scatterlist *sglist,
			       int nelems,
			       enum dma_data_direction direction,
			       unsigned long attrs);

extern void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,
				  size_t size, dma_addr_t *dma_handle,
				  unsigned long mask, gfp_t flag, int node);
extern void iommu_free_coherent(struct iommu_table *tbl, size_t size,
				void *vaddr, dma_addr_t dma_handle);
extern dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl,
				 struct page *page, unsigned long offset,
				 size_t size, unsigned long mask,
				 enum dma_data_direction direction,
				 unsigned long attrs);
extern void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle,
			     size_t size, enum dma_data_direction direction,
			     unsigned long attrs);

extern void iommu_init_early_pSeries(void);
extern void iommu_init_early_dart(struct pci_controller_ops *controller_ops);
extern void iommu_init_early_pasemi(void);

#if defined(CONFIG_PPC64) && defined(CONFIG_PM)
static inline void iommu_save(void)
{
	if (ppc_md.iommu_save)
		ppc_md.iommu_save();
}

static inline void iommu_restore(void)
{
	if (ppc_md.iommu_restore)
		ppc_md.iommu_restore();
}
#endif

/* The API to support IOMMU operations for VFIO */
extern int iommu_tce_check_ioba(unsigned long page_shift,
		unsigned long offset, unsigned long size,
		unsigned long ioba, unsigned long npages);
extern int iommu_tce_check_gpa(unsigned long page_shift,
		unsigned long gpa);

#define iommu_tce_clear_param_check(tbl, ioba, tce_value, npages) \
		(iommu_tce_check_ioba((tbl)->it_page_shift,       \
				(tbl)->it_offset, (tbl)->it_size, \
				(ioba), (npages)) || (tce_value))
#define iommu_tce_put_param_check(tbl, ioba, gpa)                 \
		(iommu_tce_check_ioba((tbl)->it_page_shift,       \
				(tbl)->it_offset, (tbl)->it_size, \
				(ioba), 1) ||                     \
		iommu_tce_check_gpa((tbl)->it_page_shift, (gpa)))

extern void iommu_flush_tce(struct iommu_table *tbl);
extern int iommu_take_ownership(struct iommu_table *tbl);
extern void iommu_release_ownership(struct iommu_table *tbl);

extern enum dma_data_direction iommu_tce_direction(unsigned long tce);
extern unsigned long iommu_direction_to_tce_perm(enum dma_data_direction dir);

#ifdef CONFIG_PPC_CELL_NATIVE
extern bool iommu_fixed_is_weak;
#else
#define iommu_fixed_is_weak false
#endif

extern const struct dma_map_ops dma_iommu_ops;

static inline unsigned long device_to_mask(struct device *dev)
{
	if (dev->dma_mask && *dev->dma_mask)
		return *dev->dma_mask;
	/* Assume devices without mask can take 32 bit addresses */
	return 0xfffffffful;
}

#endif /* __KERNEL__ */
#endif /* _ASM_IOMMU_H */
Commit	Line	Data
9b6b563c PM	1	/*
	2	* Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
	3	* Rewrite, cleanup:
91f14480	4	* Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
2db4928b	5	*
9b6b563c PM	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
2db4928b	10	*
9b6b563c PM	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
2db4928b	15	*
9b6b563c PM	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20
	21	#ifndef _ASM_IOMMU_H
	22	#define _ASM_IOMMU_H
88ced031	23	#ifdef __KERNEL__
9b6b563c	24
5d2efba6	25	#include <linux/compiler.h>
9b6b563c PM	26	#include <linux/spinlock.h>
	27	#include <linux/device.h>
	28	#include <linux/dma-mapping.h>
1977f032	29	#include <linux/bitops.h>
7e11580b	30	#include <asm/machdep.h>
5d2efba6	31	#include <asm/types.h>
798248a3	32	#include <asm/pci-bridge.h>
ec0c464c	33	#include <asm/asm-const.h>
5d2efba6	34
e589a440 AP	35	#define IOMMU_PAGE_SHIFT_4K 12
	36	#define IOMMU_PAGE_SIZE_4K (ASM_CONST(1) << IOMMU_PAGE_SHIFT_4K)
	37	#define IOMMU_PAGE_MASK_4K (~((1 << IOMMU_PAGE_SHIFT_4K) - 1))
	38	#define IOMMU_PAGE_ALIGN_4K(addr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE_4K)
5d2efba6	39
d0847757 AP	40	#define IOMMU_PAGE_SIZE(tblptr) (ASM_CONST(1) << (tblptr)->it_page_shift)
	41	#define IOMMU_PAGE_MASK(tblptr) (~((1 << (tblptr)->it_page_shift) - 1))
	42	#define IOMMU_PAGE_ALIGN(addr, tblptr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE(tblptr))
	43
165785e5 JK	44	/* Boot time flags */
	45	extern int iommu_is_off;
	46	extern int iommu_force_on;
5d2efba6	47
da004c36	48	struct iommu_table_ops {
05c6cfb9 AK	49	/*
	50	* When called with direction==DMA_NONE, it is equal to clear().
	51	* uaddr is a linear map address.
	52	*/
da004c36 AK	53	int (set)(struct iommu_table tbl,
	54	long index, long npages,
	55	unsigned long uaddr,
	56	enum dma_data_direction direction,
00085f1e	57	unsigned long attrs);
05c6cfb9 AK	58	#ifdef CONFIG_IOMMU_API
	59	/*
	60	* Exchanges existing TCE with new TCE plus direction bits;
	61	* returns old TCE and DMA direction mask.
	62	* @tce is a physical address.
	63	*/
	64	int (exchange)(struct iommu_table tbl,
	65	long index,
	66	unsigned long *hpa,
	67	enum dma_data_direction *direction);
a540aa56 AK	68	/* Real mode */
	69	int (exchange_rm)(struct iommu_table tbl,
	70	long index,
	71	unsigned long *hpa,
	72	enum dma_data_direction *direction);
090bad39	73
a68bd126	74	__be64 (useraddrptr)(struct iommu_table *tbl, long index, bool alloc);
05c6cfb9	75	#endif
da004c36 AK	76	void (clear)(struct iommu_table tbl,
da004c36 AK	77	long index, long npages);
05c6cfb9	78	/* get() returns a physical address */
da004c36 AK	79	unsigned long (get)(struct iommu_table tbl, long index);
da004c36 AK	80	void (flush)(struct iommu_table tbl);
4793d65d	81	void (free)(struct iommu_table tbl);
da004c36 AK	82	};
	83
	84	/* These are used by VIO */
	85	extern struct iommu_table_ops iommu_table_lpar_multi_ops;
	86	extern struct iommu_table_ops iommu_table_pseries_ops;
	87
9b6b563c PM	88	/*
	89	* IOMAP_MAX_ORDER defines the largest contiguous block
	90	* of dma space we can get. IOMAP_MAX_ORDER = 13
	91	* allows up to 2*12 pages (4096 4096) = 16 MB
	92	*/
5d2efba6	93	#define IOMAP_MAX_ORDER 13
9b6b563c	94
b4c3a872 AB	95	#define IOMMU_POOL_HASHBITS 2
	96	#define IOMMU_NR_POOLS (1 << IOMMU_POOL_HASHBITS)
	97
	98	struct iommu_pool {
	99	unsigned long start;
	100	unsigned long end;
	101	unsigned long hint;
	102	spinlock_t lock;
	103	} ____cacheline_aligned_in_smp;
	104
9b6b563c PM	105	struct iommu_table {
	106	unsigned long it_busno; /* Bus number this table belongs to */
	107	unsigned long it_size; /* Size of iommu table in entries */
bbb845c4 AK	108	unsigned long it_indirect_levels;
bbb845c4 AK	109	unsigned long it_level_size;
00547193	110	unsigned long it_allocated_size;
9b6b563c PM	111	unsigned long it_offset; /* Offset into global table */
	112	unsigned long it_base; /* mapped address of tce table */
	113	unsigned long it_index; /* which iommu table this is */
	114	unsigned long it_type; /* type: PCI or Virtual Bus */
	115	unsigned long it_blocksize; /* Entries in each block (cacheline) */
b4c3a872 AB	116	unsigned long poolsize;
	117	unsigned long nr_pools;
	118	struct iommu_pool large_pool;
	119	struct iommu_pool pools[IOMMU_NR_POOLS];
9b6b563c	120	unsigned long it_map; / A simple allocation bitmap for now */
3a553170	121	unsigned long it_page_shift;/* table iommu page size */
0eaf4def	122	struct list_head it_group_list;/* List of iommu_table_group_link */
00a5c58d	123	__be64 it_userspace; / userspace view of the table */
da004c36	124	struct iommu_table_ops *it_ops;
e5afdf9d	125	struct kref it_kref;
a68bd126	126	int it_nid;
9b6b563c PM	127	};
9b6b563c PM	128
6e301a8e	129	#define IOMMU_TABLE_USERSPACE_ENTRY_RO(tbl, entry) \
a68bd126	130	((tbl)->it_ops->useraddrptr((tbl), (entry), false))
2157e7b8	131	#define IOMMU_TABLE_USERSPACE_ENTRY(tbl, entry) \
a68bd126	132	((tbl)->it_ops->useraddrptr((tbl), (entry), true))
2157e7b8	133
d0847757 AP	134	/* Pure 2^n version of get_order */
	135	static inline __attribute_const__
	136	int get_iommu_order(unsigned long size, struct iommu_table *tbl)
	137	{
	138	return __ilog2((size - 1) >> tbl->it_page_shift) + 1;
	139	}
	140
	141
9b6b563c	142	struct scatterlist;
9b6b563c	143
2db4928b BH	144	#ifdef CONFIG_PPC64
	145
	146	static inline void set_iommu_table_base(struct device *dev,
	147	struct iommu_table *base)
738ef42e	148	{
2db4928b	149	dev->archdata.iommu_table_base = base;
738ef42e BB	150	}
	151
	152	static inline void get_iommu_table_base(struct device dev)
	153	{
2db4928b	154	return dev->archdata.iommu_table_base;
738ef42e BB	155	}
738ef42e BB	156
2db4928b BH	157	extern int dma_iommu_dma_supported(struct device *dev, u64 mask);
2db4928b BH	158
e5afdf9d AK	159	extern struct iommu_table iommu_tce_table_get(struct iommu_table tbl);
e5afdf9d AK	160	extern int iommu_tce_table_put(struct iommu_table *tbl);
9b6b563c	161
9b6b563c PM	162	/* Initializes an iommu_table based in values set in the passed-in
	163	* structure
	164	*/
ca1588e7 AB	165	extern struct iommu_table iommu_init_table(struct iommu_table tbl,
ca1588e7 AB	166	int nid);
e633bc86	167	#define IOMMU_TABLE_GROUP_MAX_TABLES 2
b348aa65	168
f87a8864 AK	169	struct iommu_table_group;
	170
	171	struct iommu_table_group_ops {
00547193 AK	172	unsigned long (*get_table_size)(
	173	__u32 page_shift,
	174	__u64 window_size,
	175	__u32 levels);
4793d65d AK	176	long (create_table)(struct iommu_table_group table_group,
	177	int num,
	178	__u32 page_shift,
	179	__u64 window_size,
	180	__u32 levels,
	181	struct iommu_table **ptbl);
	182	long (set_window)(struct iommu_table_group table_group,
	183	int num,
	184	struct iommu_table *tblnew);
	185	long (unset_window)(struct iommu_table_group table_group,
	186	int num);
f87a8864 AK	187	/* Switch ownership from platform code to external user (e.g. VFIO) */
	188	void (take_ownership)(struct iommu_table_group table_group);
	189	/* Switch ownership from external user (e.g. VFIO) back to core */
	190	void (release_ownership)(struct iommu_table_group table_group);
	191	};
	192
0eaf4def AK	193	struct iommu_table_group_link {
	194	struct list_head next;
	195	struct rcu_head rcu;
	196	struct iommu_table_group *table_group;
	197	};
	198
b348aa65	199	struct iommu_table_group {
4793d65d AK	200	/* IOMMU properties */
	201	__u32 tce32_start;
	202	__u32 tce32_size;
	203	__u64 pgsizes; /* Bitmap of supported page sizes */
	204	__u32 max_dynamic_windows_supported;
	205	__u32 max_levels;
	206
b348aa65 AK	207	struct iommu_group *group;
b348aa65 AK	208	struct iommu_table *tables[IOMMU_TABLE_GROUP_MAX_TABLES];
f87a8864	209	struct iommu_table_group_ops *ops;
b348aa65 AK	210	};
b348aa65 AK	211
d905c5df	212	#ifdef CONFIG_IOMMU_API
b348aa65 AK	213
b348aa65 AK	214	extern void iommu_register_group(struct iommu_table_group *table_group,
4e13c1ac	215	int pci_domain_number, unsigned long pe_num);
c4e9d3c1 AK	216	extern int iommu_add_device(struct iommu_table_group *table_group,
c4e9d3c1 AK	217	struct device *dev);
d905c5df	218	extern void iommu_del_device(struct device *dev);
c10c21ef AK	219	extern long iommu_tce_xchg(struct mm_struct mm, struct iommu_table tbl,
	220	unsigned long entry, unsigned long *hpa,
	221	enum dma_data_direction *direction);
d905c5df	222	#else
b348aa65	223	static inline void iommu_register_group(struct iommu_table_group *table_group,
d905c5df AK	224	int pci_domain_number,
	225	unsigned long pe_num)
	226	{
	227	}
	228
c4e9d3c1 AK	229	static inline int iommu_add_device(struct iommu_table_group *table_group,
c4e9d3c1 AK	230	struct device *dev)
d905c5df AK	231	{
	232	return 0;
	233	}
	234
	235	static inline void iommu_del_device(struct device *dev)
	236	{
	237	}
	238	#endif /* !CONFIG_IOMMU_API */
	239
a20f507f	240	u64 dma_iommu_get_required_mask(struct device *dev);
2db4928b BH	241	#else
	242
	243	static inline void get_iommu_table_base(struct device dev)
	244	{
	245	return NULL;
	246	}
	247
	248	static inline int dma_iommu_dma_supported(struct device *dev, u64 mask)
	249	{
	250	return 0;
	251	}
	252
	253	#endif /* CONFIG_PPC64 */
	254
0690cbd2 JR	255	extern int ppc_iommu_map_sg(struct device dev, struct iommu_table tbl,
	256	struct scatterlist *sglist, int nelems,
	257	unsigned long mask,
	258	enum dma_data_direction direction,
00085f1e	259	unsigned long attrs);
0690cbd2 JR	260	extern void ppc_iommu_unmap_sg(struct iommu_table *tbl,
	261	struct scatterlist *sglist,
	262	int nelems,
	263	enum dma_data_direction direction,
00085f1e	264	unsigned long attrs);
9b6b563c	265
fb3475e9 FT	266	extern void iommu_alloc_coherent(struct device dev, struct iommu_table *tbl,
	267	size_t size, dma_addr_t *dma_handle,
	268	unsigned long mask, gfp_t flag, int node);
9b6b563c	269	extern void iommu_free_coherent(struct iommu_table *tbl, size_t size,
12d04eef	270	void *vaddr, dma_addr_t dma_handle);
f9226d57 MN	271	extern dma_addr_t iommu_map_page(struct device dev, struct iommu_table tbl,
	272	struct page *page, unsigned long offset,
	273	size_t size, unsigned long mask,
	274	enum dma_data_direction direction,
00085f1e	275	unsigned long attrs);
f9226d57 MN	276	extern void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle,
f9226d57 MN	277	size_t size, enum dma_data_direction direction,
00085f1e	278	unsigned long attrs);
9b6b563c PM	279
9b6b563c PM	280	extern void iommu_init_early_pSeries(void);
798248a3	281	extern void iommu_init_early_dart(struct pci_controller_ops *controller_ops);
31c56d82	282	extern void iommu_init_early_pasemi(void);
9b6b563c	283
7e11580b JB	284	#if defined(CONFIG_PPC64) && defined(CONFIG_PM)
	285	static inline void iommu_save(void)
	286	{
	287	if (ppc_md.iommu_save)
	288	ppc_md.iommu_save();
	289	}
	290
	291	static inline void iommu_restore(void)
	292	{
	293	if (ppc_md.iommu_restore)
	294	ppc_md.iommu_restore();
	295	}
	296	#endif
9b6b563c	297
4e13c1ac	298	/* The API to support IOMMU operations for VFIO */
b1af23d8 AK	299	extern int iommu_tce_check_ioba(unsigned long page_shift,
	300	unsigned long offset, unsigned long size,
	301	unsigned long ioba, unsigned long npages);
	302	extern int iommu_tce_check_gpa(unsigned long page_shift,
	303	unsigned long gpa);
	304
	305	#define iommu_tce_clear_param_check(tbl, ioba, tce_value, npages) \
	306	(iommu_tce_check_ioba((tbl)->it_page_shift, \
	307	(tbl)->it_offset, (tbl)->it_size, \
	308	(ioba), (npages)) \|\| (tce_value))
	309	#define iommu_tce_put_param_check(tbl, ioba, gpa) \
	310	(iommu_tce_check_ioba((tbl)->it_page_shift, \
	311	(tbl)->it_offset, (tbl)->it_size, \
	312	(ioba), 1) \|\| \
	313	iommu_tce_check_gpa((tbl)->it_page_shift, (gpa)))
4e13c1ac AK	314
	315	extern void iommu_flush_tce(struct iommu_table *tbl);
	316	extern int iommu_take_ownership(struct iommu_table *tbl);
	317	extern void iommu_release_ownership(struct iommu_table *tbl);
	318
	319	extern enum dma_data_direction iommu_tce_direction(unsigned long tce);
10b35b2b	320	extern unsigned long iommu_direction_to_tce_perm(enum dma_data_direction dir);
4e13c1ac	321
ba767b52 CH	322	#ifdef CONFIG_PPC_CELL_NATIVE
	323	extern bool iommu_fixed_is_weak;
	324	#else
	325	#define iommu_fixed_is_weak false
	326	#endif
	327
4a605e2d CH	328	extern const struct dma_map_ops dma_iommu_ops;
	329
	330	static inline unsigned long device_to_mask(struct device *dev)
	331	{
	332	if (dev->dma_mask && *dev->dma_mask)
	333	return *dev->dma_mask;
	334	/* Assume devices without mask can take 32 bit addresses */
	335	return 0xfffffffful;
	336	}
	337
88ced031	338	#endif /* __KERNEL__ */
9b6b563c	339	#endif /* _ASM_IOMMU_H */